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12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/math64.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_graph.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/videodev2.h>
25
26#include <media/v4l2-ctrls.h>
27#include <media/v4l2-device.h>
28#include <media/v4l2-event.h>
29#include <media/v4l2-image-sizes.h>
30#include <media/v4l2-ioctl.h>
31#include <media/v4l2-fwnode.h>
32#include <media/v4l2-subdev.h>
33#include <media/videobuf2-dma-contig.h>
34
35#include "atmel-isc-regs.h"
36#include "atmel-isc.h"
37
38static unsigned int debug;
39module_param(debug, int, 0644);
40MODULE_PARM_DESC(debug, "debug level (0-2)");
41
42static unsigned int sensor_preferred = 1;
43module_param(sensor_preferred, uint, 0644);
44MODULE_PARM_DESC(sensor_preferred,
45 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
46
47
48const struct isc_format controller_formats[] = {
49 {
50 .fourcc = V4L2_PIX_FMT_ARGB444,
51 },
52 {
53 .fourcc = V4L2_PIX_FMT_ARGB555,
54 },
55 {
56 .fourcc = V4L2_PIX_FMT_RGB565,
57 },
58 {
59 .fourcc = V4L2_PIX_FMT_ABGR32,
60 },
61 {
62 .fourcc = V4L2_PIX_FMT_XBGR32,
63 },
64 {
65 .fourcc = V4L2_PIX_FMT_YUV420,
66 },
67 {
68 .fourcc = V4L2_PIX_FMT_YUYV,
69 },
70 {
71 .fourcc = V4L2_PIX_FMT_YUV422P,
72 },
73 {
74 .fourcc = V4L2_PIX_FMT_GREY,
75 },
76 {
77 .fourcc = V4L2_PIX_FMT_Y10,
78 },
79};
80
81
82struct isc_format formats_list[] = {
83 {
84 .fourcc = V4L2_PIX_FMT_SBGGR8,
85 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
86 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
87 .cfa_baycfg = ISC_BAY_CFG_BGBG,
88 },
89 {
90 .fourcc = V4L2_PIX_FMT_SGBRG8,
91 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
92 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
93 .cfa_baycfg = ISC_BAY_CFG_GBGB,
94 },
95 {
96 .fourcc = V4L2_PIX_FMT_SGRBG8,
97 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
98 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
99 .cfa_baycfg = ISC_BAY_CFG_GRGR,
100 },
101 {
102 .fourcc = V4L2_PIX_FMT_SRGGB8,
103 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
104 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
105 .cfa_baycfg = ISC_BAY_CFG_RGRG,
106 },
107 {
108 .fourcc = V4L2_PIX_FMT_SBGGR10,
109 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
110 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
111 .cfa_baycfg = ISC_BAY_CFG_RGRG,
112 },
113 {
114 .fourcc = V4L2_PIX_FMT_SGBRG10,
115 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
116 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
117 .cfa_baycfg = ISC_BAY_CFG_GBGB,
118 },
119 {
120 .fourcc = V4L2_PIX_FMT_SGRBG10,
121 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
122 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
123 .cfa_baycfg = ISC_BAY_CFG_GRGR,
124 },
125 {
126 .fourcc = V4L2_PIX_FMT_SRGGB10,
127 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
128 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
129 .cfa_baycfg = ISC_BAY_CFG_RGRG,
130 },
131 {
132 .fourcc = V4L2_PIX_FMT_SBGGR12,
133 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
134 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
135 .cfa_baycfg = ISC_BAY_CFG_BGBG,
136 },
137 {
138 .fourcc = V4L2_PIX_FMT_SGBRG12,
139 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
140 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
141 .cfa_baycfg = ISC_BAY_CFG_GBGB,
142 },
143 {
144 .fourcc = V4L2_PIX_FMT_SGRBG12,
145 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
146 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
147 .cfa_baycfg = ISC_BAY_CFG_GRGR,
148 },
149 {
150 .fourcc = V4L2_PIX_FMT_SRGGB12,
151 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
152 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
153 .cfa_baycfg = ISC_BAY_CFG_RGRG,
154 },
155 {
156 .fourcc = V4L2_PIX_FMT_GREY,
157 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
158 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
159 },
160 {
161 .fourcc = V4L2_PIX_FMT_YUYV,
162 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
163 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
164 },
165 {
166 .fourcc = V4L2_PIX_FMT_RGB565,
167 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
168 .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
169 },
170 {
171 .fourcc = V4L2_PIX_FMT_Y10,
172 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
173 .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
174 },
175
176};
177
178
179const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {
180
181 { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A,
182 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
183 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
184 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
185 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
186 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
187 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
188 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
189 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
190 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
191 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
192
193
194 { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B,
195 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
196 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
197 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
198 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
199 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
200 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
201 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
202 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
203 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
204 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
205
206
207 { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B,
208 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
209 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
210 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
211 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
212 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
213 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
214 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
215 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
216 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
217 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
218};
219
220#define ISC_IS_FORMAT_RAW(mbus_code) \
221 (((mbus_code) & 0xf000) == 0x3000)
222
223#define ISC_IS_FORMAT_GREY(mbus_code) \
224 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
225 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
226
227static inline void isc_update_awb_ctrls(struct isc_device *isc)
228{
229 struct isc_ctrls *ctrls = &isc->ctrls;
230
231 regmap_write(isc->regmap, ISC_WB_O_RGR,
232 (ISC_WB_O_ZERO_VAL - (ctrls->offset[ISC_HIS_CFG_MODE_R])) |
233 ((ISC_WB_O_ZERO_VAL - ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
234 regmap_write(isc->regmap, ISC_WB_O_BGB,
235 (ISC_WB_O_ZERO_VAL - (ctrls->offset[ISC_HIS_CFG_MODE_B])) |
236 ((ISC_WB_O_ZERO_VAL - ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
237 regmap_write(isc->regmap, ISC_WB_G_RGR,
238 ctrls->gain[ISC_HIS_CFG_MODE_R] |
239 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
240 regmap_write(isc->regmap, ISC_WB_G_BGB,
241 ctrls->gain[ISC_HIS_CFG_MODE_B] |
242 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
243}
244
245static inline void isc_reset_awb_ctrls(struct isc_device *isc)
246{
247 unsigned int c;
248
249 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
250
251 isc->ctrls.gain[c] = 1 << 9;
252
253
254
255
256
257 isc->ctrls.offset[c] = ISC_WB_O_ZERO_VAL;
258 }
259}
260
261static int isc_wait_clk_stable(struct clk_hw *hw)
262{
263 struct isc_clk *isc_clk = to_isc_clk(hw);
264 struct regmap *regmap = isc_clk->regmap;
265 unsigned long timeout = jiffies + usecs_to_jiffies(1000);
266 unsigned int status;
267
268 while (time_before(jiffies, timeout)) {
269 regmap_read(regmap, ISC_CLKSR, &status);
270 if (!(status & ISC_CLKSR_SIP))
271 return 0;
272
273 usleep_range(10, 250);
274 }
275
276 return -ETIMEDOUT;
277}
278
279static int isc_clk_prepare(struct clk_hw *hw)
280{
281 struct isc_clk *isc_clk = to_isc_clk(hw);
282
283 if (isc_clk->id == ISC_ISPCK)
284 pm_runtime_get_sync(isc_clk->dev);
285
286 return isc_wait_clk_stable(hw);
287}
288
289static void isc_clk_unprepare(struct clk_hw *hw)
290{
291 struct isc_clk *isc_clk = to_isc_clk(hw);
292
293 isc_wait_clk_stable(hw);
294
295 if (isc_clk->id == ISC_ISPCK)
296 pm_runtime_put_sync(isc_clk->dev);
297}
298
299static int isc_clk_enable(struct clk_hw *hw)
300{
301 struct isc_clk *isc_clk = to_isc_clk(hw);
302 u32 id = isc_clk->id;
303 struct regmap *regmap = isc_clk->regmap;
304 unsigned long flags;
305 unsigned int status;
306
307 dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
308 __func__, isc_clk->div, isc_clk->parent_id);
309
310 spin_lock_irqsave(&isc_clk->lock, flags);
311 regmap_update_bits(regmap, ISC_CLKCFG,
312 ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),
313 (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |
314 (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));
315
316 regmap_write(regmap, ISC_CLKEN, ISC_CLK(id));
317 spin_unlock_irqrestore(&isc_clk->lock, flags);
318
319 regmap_read(regmap, ISC_CLKSR, &status);
320 if (status & ISC_CLK(id))
321 return 0;
322 else
323 return -EINVAL;
324}
325
326static void isc_clk_disable(struct clk_hw *hw)
327{
328 struct isc_clk *isc_clk = to_isc_clk(hw);
329 u32 id = isc_clk->id;
330 unsigned long flags;
331
332 spin_lock_irqsave(&isc_clk->lock, flags);
333 regmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));
334 spin_unlock_irqrestore(&isc_clk->lock, flags);
335}
336
337static int isc_clk_is_enabled(struct clk_hw *hw)
338{
339 struct isc_clk *isc_clk = to_isc_clk(hw);
340 u32 status;
341
342 if (isc_clk->id == ISC_ISPCK)
343 pm_runtime_get_sync(isc_clk->dev);
344
345 regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
346
347 if (isc_clk->id == ISC_ISPCK)
348 pm_runtime_put_sync(isc_clk->dev);
349
350 return status & ISC_CLK(isc_clk->id) ? 1 : 0;
351}
352
353static unsigned long
354isc_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
355{
356 struct isc_clk *isc_clk = to_isc_clk(hw);
357
358 return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1);
359}
360
361static int isc_clk_determine_rate(struct clk_hw *hw,
362 struct clk_rate_request *req)
363{
364 struct isc_clk *isc_clk = to_isc_clk(hw);
365 long best_rate = -EINVAL;
366 int best_diff = -1;
367 unsigned int i, div;
368
369 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
370 struct clk_hw *parent;
371 unsigned long parent_rate;
372
373 parent = clk_hw_get_parent_by_index(hw, i);
374 if (!parent)
375 continue;
376
377 parent_rate = clk_hw_get_rate(parent);
378 if (!parent_rate)
379 continue;
380
381 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) {
382 unsigned long rate;
383 int diff;
384
385 rate = DIV_ROUND_CLOSEST(parent_rate, div);
386 diff = abs(req->rate - rate);
387
388 if (best_diff < 0 || best_diff > diff) {
389 best_rate = rate;
390 best_diff = diff;
391 req->best_parent_rate = parent_rate;
392 req->best_parent_hw = parent;
393 }
394
395 if (!best_diff || rate < req->rate)
396 break;
397 }
398
399 if (!best_diff)
400 break;
401 }
402
403 dev_dbg(isc_clk->dev,
404 "ISC CLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
405 __func__, best_rate,
406 __clk_get_name((req->best_parent_hw)->clk),
407 req->best_parent_rate);
408
409 if (best_rate < 0)
410 return best_rate;
411
412 req->rate = best_rate;
413
414 return 0;
415}
416
417static int isc_clk_set_parent(struct clk_hw *hw, u8 index)
418{
419 struct isc_clk *isc_clk = to_isc_clk(hw);
420
421 if (index >= clk_hw_get_num_parents(hw))
422 return -EINVAL;
423
424 isc_clk->parent_id = index;
425
426 return 0;
427}
428
429static u8 isc_clk_get_parent(struct clk_hw *hw)
430{
431 struct isc_clk *isc_clk = to_isc_clk(hw);
432
433 return isc_clk->parent_id;
434}
435
436static int isc_clk_set_rate(struct clk_hw *hw,
437 unsigned long rate,
438 unsigned long parent_rate)
439{
440 struct isc_clk *isc_clk = to_isc_clk(hw);
441 u32 div;
442
443 if (!rate)
444 return -EINVAL;
445
446 div = DIV_ROUND_CLOSEST(parent_rate, rate);
447 if (div > (ISC_CLK_MAX_DIV + 1) || !div)
448 return -EINVAL;
449
450 isc_clk->div = div - 1;
451
452 return 0;
453}
454
455static const struct clk_ops isc_clk_ops = {
456 .prepare = isc_clk_prepare,
457 .unprepare = isc_clk_unprepare,
458 .enable = isc_clk_enable,
459 .disable = isc_clk_disable,
460 .is_enabled = isc_clk_is_enabled,
461 .recalc_rate = isc_clk_recalc_rate,
462 .determine_rate = isc_clk_determine_rate,
463 .set_parent = isc_clk_set_parent,
464 .get_parent = isc_clk_get_parent,
465 .set_rate = isc_clk_set_rate,
466};
467
468static int isc_clk_register(struct isc_device *isc, unsigned int id)
469{
470 struct regmap *regmap = isc->regmap;
471 struct device_node *np = isc->dev->of_node;
472 struct isc_clk *isc_clk;
473 struct clk_init_data init;
474 const char *clk_name = np->name;
475 const char *parent_names[3];
476 int num_parents;
477
478 num_parents = of_clk_get_parent_count(np);
479 if (num_parents < 1 || num_parents > 3)
480 return -EINVAL;
481
482 if (num_parents > 2 && id == ISC_ISPCK)
483 num_parents = 2;
484
485 of_clk_parent_fill(np, parent_names, num_parents);
486
487 if (id == ISC_MCK)
488 of_property_read_string(np, "clock-output-names", &clk_name);
489 else
490 clk_name = "isc-ispck";
491
492 init.parent_names = parent_names;
493 init.num_parents = num_parents;
494 init.name = clk_name;
495 init.ops = &isc_clk_ops;
496 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
497
498 isc_clk = &isc->isc_clks[id];
499 isc_clk->hw.init = &init;
500 isc_clk->regmap = regmap;
501 isc_clk->id = id;
502 isc_clk->dev = isc->dev;
503 spin_lock_init(&isc_clk->lock);
504
505 isc_clk->clk = clk_register(isc->dev, &isc_clk->hw);
506 if (IS_ERR(isc_clk->clk)) {
507 dev_err(isc->dev, "%s: clock register fail\n", clk_name);
508 return PTR_ERR(isc_clk->clk);
509 } else if (id == ISC_MCK)
510 of_clk_add_provider(np, of_clk_src_simple_get, isc_clk->clk);
511
512 return 0;
513}
514
515int isc_clk_init(struct isc_device *isc)
516{
517 unsigned int i;
518 int ret;
519
520 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++)
521 isc->isc_clks[i].clk = ERR_PTR(-EINVAL);
522
523 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
524 ret = isc_clk_register(isc, i);
525 if (ret)
526 return ret;
527 }
528
529 return 0;
530}
531
532void isc_clk_cleanup(struct isc_device *isc)
533{
534 unsigned int i;
535
536 of_clk_del_provider(isc->dev->of_node);
537
538 for (i = 0; i < ARRAY_SIZE(isc->isc_clks); i++) {
539 struct isc_clk *isc_clk = &isc->isc_clks[i];
540
541 if (!IS_ERR(isc_clk->clk))
542 clk_unregister(isc_clk->clk);
543 }
544}
545
546static int isc_queue_setup(struct vb2_queue *vq,
547 unsigned int *nbuffers, unsigned int *nplanes,
548 unsigned int sizes[], struct device *alloc_devs[])
549{
550 struct isc_device *isc = vb2_get_drv_priv(vq);
551 unsigned int size = isc->fmt.fmt.pix.sizeimage;
552
553 if (*nplanes)
554 return sizes[0] < size ? -EINVAL : 0;
555
556 *nplanes = 1;
557 sizes[0] = size;
558
559 return 0;
560}
561
562static int isc_buffer_prepare(struct vb2_buffer *vb)
563{
564 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
565 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
566 unsigned long size = isc->fmt.fmt.pix.sizeimage;
567
568 if (vb2_plane_size(vb, 0) < size) {
569 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
570 vb2_plane_size(vb, 0), size);
571 return -EINVAL;
572 }
573
574 vb2_set_plane_payload(vb, 0, size);
575
576 vbuf->field = isc->fmt.fmt.pix.field;
577
578 return 0;
579}
580
581static void isc_start_dma(struct isc_device *isc)
582{
583 struct regmap *regmap = isc->regmap;
584 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
585 u32 dctrl_dview;
586 dma_addr_t addr0;
587 u32 h, w;
588
589 h = isc->fmt.fmt.pix.height;
590 w = isc->fmt.fmt.pix.width;
591
592
593
594
595
596
597
598 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
599 h <<= 1;
600 w <<= 1;
601 }
602
603
604
605
606
607
608
609
610 regmap_write(regmap, ISC_PFE_CFG1,
611 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
612 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
613
614 regmap_write(regmap, ISC_PFE_CFG2,
615 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
616 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
617
618 regmap_update_bits(regmap, ISC_PFE_CFG0,
619 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
620 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
621
622 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
623 regmap_write(regmap, ISC_DAD0, addr0);
624
625 switch (isc->config.fourcc) {
626 case V4L2_PIX_FMT_YUV420:
627 regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
628 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
629 break;
630 case V4L2_PIX_FMT_YUV422P:
631 regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
632 regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
633 break;
634 default:
635 break;
636 }
637
638 dctrl_dview = isc->config.dctrl_dview;
639
640 regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
641 spin_lock(&isc->awb_lock);
642 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
643 spin_unlock(&isc->awb_lock);
644}
645
646static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
647{
648 struct regmap *regmap = isc->regmap;
649 struct isc_ctrls *ctrls = &isc->ctrls;
650 u32 val, bay_cfg;
651 const u32 *gamma;
652 unsigned int i;
653
654
655 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
656 val = pipeline & BIT(i) ? 1 : 0;
657 regmap_field_write(isc->pipeline[i], val);
658 }
659
660 if (!pipeline)
661 return;
662
663 bay_cfg = isc->config.sd_format->cfa_baycfg;
664
665 if (ctrls->awb == ISC_WB_NONE)
666 isc_reset_awb_ctrls(isc);
667
668 regmap_write(regmap, ISC_WB_CFG, bay_cfg);
669 isc_update_awb_ctrls(isc);
670
671 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
672
673 gamma = &isc_gamma_table[ctrls->gamma_index][0];
674 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
675 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
676 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
677
678
679 regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
680 regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
681 regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
682 regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
683 regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
684 regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
685
686 regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
687 regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
688}
689
690static int isc_update_profile(struct isc_device *isc)
691{
692 struct regmap *regmap = isc->regmap;
693 u32 sr;
694 int counter = 100;
695
696 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
697
698 regmap_read(regmap, ISC_CTRLSR, &sr);
699 while ((sr & ISC_CTRL_UPPRO) && counter--) {
700 usleep_range(1000, 2000);
701 regmap_read(regmap, ISC_CTRLSR, &sr);
702 }
703
704 if (counter < 0) {
705 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
706 return -ETIMEDOUT;
707 }
708
709 return 0;
710}
711
712static void isc_set_histogram(struct isc_device *isc, bool enable)
713{
714 struct regmap *regmap = isc->regmap;
715 struct isc_ctrls *ctrls = &isc->ctrls;
716
717 if (enable) {
718 regmap_write(regmap, ISC_HIS_CFG,
719 ISC_HIS_CFG_MODE_GR |
720 (isc->config.sd_format->cfa_baycfg
721 << ISC_HIS_CFG_BAYSEL_SHIFT) |
722 ISC_HIS_CFG_RAR);
723 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
724 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
725 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
726 isc_update_profile(isc);
727 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
728
729 ctrls->hist_stat = HIST_ENABLED;
730 } else {
731 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
732 regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
733
734 ctrls->hist_stat = HIST_DISABLED;
735 }
736}
737
738static int isc_configure(struct isc_device *isc)
739{
740 struct regmap *regmap = isc->regmap;
741 u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
742 struct isc_subdev_entity *subdev = isc->current_subdev;
743
744 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
745 rlp_mode = isc->config.rlp_cfg_mode;
746 pipeline = isc->config.bits_pipeline;
747
748 dcfg = isc->config.dcfg_imode |
749 ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
750
751 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
752 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
753 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
754 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
755 ISC_PFE_CFG0_CCIR656;
756
757 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
758
759 regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
760 rlp_mode);
761
762 regmap_write(regmap, ISC_DCFG, dcfg);
763
764
765 isc_set_pipeline(isc, pipeline);
766
767
768
769
770
771 if (isc->ctrls.awb &&
772 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
773 isc_set_histogram(isc, true);
774 else
775 isc_set_histogram(isc, false);
776
777
778 return isc_update_profile(isc);
779}
780
781static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
782{
783 struct isc_device *isc = vb2_get_drv_priv(vq);
784 struct regmap *regmap = isc->regmap;
785 struct isc_buffer *buf;
786 unsigned long flags;
787 int ret;
788
789
790 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
791 if (ret && ret != -ENOIOCTLCMD) {
792 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
793 ret);
794 goto err_start_stream;
795 }
796
797 pm_runtime_get_sync(isc->dev);
798
799 ret = isc_configure(isc);
800 if (unlikely(ret))
801 goto err_configure;
802
803
804 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
805
806 spin_lock_irqsave(&isc->dma_queue_lock, flags);
807
808 isc->sequence = 0;
809 isc->stop = false;
810 reinit_completion(&isc->comp);
811
812 isc->cur_frm = list_first_entry(&isc->dma_queue,
813 struct isc_buffer, list);
814 list_del(&isc->cur_frm->list);
815
816 isc_start_dma(isc);
817
818 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
819
820
821 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
822 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
823
824 return 0;
825
826err_configure:
827 pm_runtime_put_sync(isc->dev);
828
829 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
830
831err_start_stream:
832 spin_lock_irqsave(&isc->dma_queue_lock, flags);
833 list_for_each_entry(buf, &isc->dma_queue, list)
834 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
835 INIT_LIST_HEAD(&isc->dma_queue);
836 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
837
838 return ret;
839}
840
841static void isc_stop_streaming(struct vb2_queue *vq)
842{
843 struct isc_device *isc = vb2_get_drv_priv(vq);
844 unsigned long flags;
845 struct isc_buffer *buf;
846 int ret;
847
848 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
849
850 isc->stop = true;
851
852
853 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
854 v4l2_err(&isc->v4l2_dev,
855 "Timeout waiting for end of the capture\n");
856
857
858 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
859
860 pm_runtime_put_sync(isc->dev);
861
862
863 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
864 if (ret && ret != -ENOIOCTLCMD)
865 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
866
867
868 spin_lock_irqsave(&isc->dma_queue_lock, flags);
869 if (unlikely(isc->cur_frm)) {
870 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
871 VB2_BUF_STATE_ERROR);
872 isc->cur_frm = NULL;
873 }
874 list_for_each_entry(buf, &isc->dma_queue, list)
875 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
876 INIT_LIST_HEAD(&isc->dma_queue);
877 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
878}
879
880static void isc_buffer_queue(struct vb2_buffer *vb)
881{
882 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
883 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
884 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
885 unsigned long flags;
886
887 spin_lock_irqsave(&isc->dma_queue_lock, flags);
888 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
889 vb2_is_streaming(vb->vb2_queue)) {
890 isc->cur_frm = buf;
891 isc_start_dma(isc);
892 } else
893 list_add_tail(&buf->list, &isc->dma_queue);
894 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
895}
896
897static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
898 unsigned int fourcc)
899{
900 unsigned int num_formats = isc->num_user_formats;
901 struct isc_format *fmt;
902 unsigned int i;
903
904 for (i = 0; i < num_formats; i++) {
905 fmt = isc->user_formats[i];
906 if (fmt->fourcc == fourcc)
907 return fmt;
908 }
909
910 return NULL;
911}
912
913static const struct vb2_ops isc_vb2_ops = {
914 .queue_setup = isc_queue_setup,
915 .wait_prepare = vb2_ops_wait_prepare,
916 .wait_finish = vb2_ops_wait_finish,
917 .buf_prepare = isc_buffer_prepare,
918 .start_streaming = isc_start_streaming,
919 .stop_streaming = isc_stop_streaming,
920 .buf_queue = isc_buffer_queue,
921};
922
923static int isc_querycap(struct file *file, void *priv,
924 struct v4l2_capability *cap)
925{
926 struct isc_device *isc = video_drvdata(file);
927
928 strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));
929 strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
930 snprintf(cap->bus_info, sizeof(cap->bus_info),
931 "platform:%s", isc->v4l2_dev.name);
932
933 return 0;
934}
935
936static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
937 struct v4l2_fmtdesc *f)
938{
939 u32 index = f->index;
940 u32 i, supported_index;
941
942 if (index < ARRAY_SIZE(controller_formats)) {
943 f->pixelformat = controller_formats[index].fourcc;
944 return 0;
945 }
946
947 index -= ARRAY_SIZE(controller_formats);
948
949 i = 0;
950 supported_index = 0;
951
952 for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
953 if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
954 !formats_list[i].sd_support)
955 continue;
956 if (supported_index == index) {
957 f->pixelformat = formats_list[i].fourcc;
958 return 0;
959 }
960 supported_index++;
961 }
962
963 return -EINVAL;
964}
965
966static int isc_g_fmt_vid_cap(struct file *file, void *priv,
967 struct v4l2_format *fmt)
968{
969 struct isc_device *isc = video_drvdata(file);
970
971 *fmt = isc->fmt;
972
973 return 0;
974}
975
976
977
978
979
980static int isc_try_validate_formats(struct isc_device *isc)
981{
982 int ret;
983 bool bayer = false, yuv = false, rgb = false, grey = false;
984
985
986 switch (isc->try_config.fourcc) {
987 case V4L2_PIX_FMT_SBGGR8:
988 case V4L2_PIX_FMT_SGBRG8:
989 case V4L2_PIX_FMT_SGRBG8:
990 case V4L2_PIX_FMT_SRGGB8:
991 case V4L2_PIX_FMT_SBGGR10:
992 case V4L2_PIX_FMT_SGBRG10:
993 case V4L2_PIX_FMT_SGRBG10:
994 case V4L2_PIX_FMT_SRGGB10:
995 case V4L2_PIX_FMT_SBGGR12:
996 case V4L2_PIX_FMT_SGBRG12:
997 case V4L2_PIX_FMT_SGRBG12:
998 case V4L2_PIX_FMT_SRGGB12:
999 ret = 0;
1000 bayer = true;
1001 break;
1002
1003 case V4L2_PIX_FMT_YUV420:
1004 case V4L2_PIX_FMT_YUV422P:
1005 case V4L2_PIX_FMT_YUYV:
1006 ret = 0;
1007 yuv = true;
1008 break;
1009
1010 case V4L2_PIX_FMT_RGB565:
1011 case V4L2_PIX_FMT_ABGR32:
1012 case V4L2_PIX_FMT_XBGR32:
1013 case V4L2_PIX_FMT_ARGB444:
1014 case V4L2_PIX_FMT_ARGB555:
1015 ret = 0;
1016 rgb = true;
1017 break;
1018 case V4L2_PIX_FMT_GREY:
1019 case V4L2_PIX_FMT_Y10:
1020 ret = 0;
1021 grey = true;
1022 break;
1023 default:
1024
1025 ret = -EINVAL;
1026 }
1027 v4l2_dbg(1, debug, &isc->v4l2_dev,
1028 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
1029 rgb, yuv, grey, bayer);
1030
1031
1032 if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
1033 return -EINVAL;
1034
1035
1036 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
1037 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
1038 return -EINVAL;
1039
1040 return ret;
1041}
1042
1043
1044
1045
1046
1047
1048static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
1049{
1050 switch (isc->try_config.fourcc) {
1051 case V4L2_PIX_FMT_SBGGR8:
1052 case V4L2_PIX_FMT_SGBRG8:
1053 case V4L2_PIX_FMT_SGRBG8:
1054 case V4L2_PIX_FMT_SRGGB8:
1055 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1056 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1057 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1058 isc->try_config.bpp = 8;
1059 break;
1060 case V4L2_PIX_FMT_SBGGR10:
1061 case V4L2_PIX_FMT_SGBRG10:
1062 case V4L2_PIX_FMT_SGRBG10:
1063 case V4L2_PIX_FMT_SRGGB10:
1064 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
1065 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1066 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1067 isc->try_config.bpp = 16;
1068 break;
1069 case V4L2_PIX_FMT_SBGGR12:
1070 case V4L2_PIX_FMT_SGBRG12:
1071 case V4L2_PIX_FMT_SGRBG12:
1072 case V4L2_PIX_FMT_SRGGB12:
1073 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
1074 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1075 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1076 isc->try_config.bpp = 16;
1077 break;
1078 case V4L2_PIX_FMT_RGB565:
1079 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
1080 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1081 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1082 isc->try_config.bpp = 16;
1083 break;
1084 case V4L2_PIX_FMT_ARGB444:
1085 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
1086 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1087 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1088 isc->try_config.bpp = 16;
1089 break;
1090 case V4L2_PIX_FMT_ARGB555:
1091 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
1092 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1093 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1094 isc->try_config.bpp = 16;
1095 break;
1096 case V4L2_PIX_FMT_ABGR32:
1097 case V4L2_PIX_FMT_XBGR32:
1098 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
1099 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1100 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1101 isc->try_config.bpp = 32;
1102 break;
1103 case V4L2_PIX_FMT_YUV420:
1104 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1105 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
1106 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1107 isc->try_config.bpp = 12;
1108 break;
1109 case V4L2_PIX_FMT_YUV422P:
1110 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1111 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
1112 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
1113 isc->try_config.bpp = 16;
1114 break;
1115 case V4L2_PIX_FMT_YUYV:
1116 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
1117 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
1118 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1119 isc->try_config.bpp = 16;
1120 break;
1121 case V4L2_PIX_FMT_GREY:
1122 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
1123 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1124 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1125 isc->try_config.bpp = 8;
1126 break;
1127 case V4L2_PIX_FMT_Y10:
1128 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
1129 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
1130 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1131 isc->try_config.bpp = 16;
1132 break;
1133 default:
1134 return -EINVAL;
1135 }
1136
1137 if (direct_dump) {
1138 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
1139 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
1140 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
1141 return 0;
1142 }
1143
1144 return 0;
1145}
1146
1147
1148
1149
1150
1151static int isc_try_configure_pipeline(struct isc_device *isc)
1152{
1153 switch (isc->try_config.fourcc) {
1154 case V4L2_PIX_FMT_RGB565:
1155 case V4L2_PIX_FMT_ARGB555:
1156 case V4L2_PIX_FMT_ARGB444:
1157 case V4L2_PIX_FMT_ABGR32:
1158 case V4L2_PIX_FMT_XBGR32:
1159
1160 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1161 isc->try_config.bits_pipeline = CFA_ENABLE |
1162 WB_ENABLE | GAM_ENABLES;
1163 } else {
1164 isc->try_config.bits_pipeline = 0x0;
1165 }
1166 break;
1167 case V4L2_PIX_FMT_YUV420:
1168
1169 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1170 isc->try_config.bits_pipeline = CFA_ENABLE |
1171 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1172 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
1173 } else {
1174 isc->try_config.bits_pipeline = 0x0;
1175 }
1176 break;
1177 case V4L2_PIX_FMT_YUV422P:
1178
1179 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1180 isc->try_config.bits_pipeline = CFA_ENABLE |
1181 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1182 SUB422_ENABLE | CBC_ENABLE;
1183 } else {
1184 isc->try_config.bits_pipeline = 0x0;
1185 }
1186 break;
1187 case V4L2_PIX_FMT_YUYV:
1188
1189 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1190 isc->try_config.bits_pipeline = CFA_ENABLE |
1191 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1192 SUB422_ENABLE | CBC_ENABLE;
1193 } else {
1194 isc->try_config.bits_pipeline = 0x0;
1195 }
1196 break;
1197 case V4L2_PIX_FMT_GREY:
1198 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
1199
1200 isc->try_config.bits_pipeline = CFA_ENABLE |
1201 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
1202 CBC_ENABLE;
1203 } else {
1204 isc->try_config.bits_pipeline = 0x0;
1205 }
1206 break;
1207 default:
1208 isc->try_config.bits_pipeline = 0x0;
1209 }
1210 return 0;
1211}
1212
1213static void isc_try_fse(struct isc_device *isc,
1214 struct v4l2_subdev_pad_config *pad_cfg)
1215{
1216 int ret;
1217 struct v4l2_subdev_frame_size_enum fse = {};
1218
1219
1220
1221
1222
1223 if (!isc->try_config.sd_format)
1224 return;
1225
1226 fse.code = isc->try_config.sd_format->mbus_code;
1227 fse.which = V4L2_SUBDEV_FORMAT_TRY;
1228
1229 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1230 pad_cfg, &fse);
1231
1232
1233
1234
1235 if (ret) {
1236 pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH;
1237 pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT;
1238 } else {
1239 pad_cfg->try_crop.width = fse.max_width;
1240 pad_cfg->try_crop.height = fse.max_height;
1241 }
1242}
1243
1244static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
1245 u32 *code)
1246{
1247 int i;
1248 struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
1249 struct v4l2_pix_format *pixfmt = &f->fmt.pix;
1250 struct v4l2_subdev_pad_config pad_cfg = {};
1251 struct v4l2_subdev_format format = {
1252 .which = V4L2_SUBDEV_FORMAT_TRY,
1253 };
1254 u32 mbus_code;
1255 int ret;
1256 bool rlp_dma_direct_dump = false;
1257
1258 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1259 return -EINVAL;
1260
1261
1262 for (i = 0; i < isc->num_user_formats; i++) {
1263 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
1264 sd_fmt = isc->user_formats[i];
1265 break;
1266 }
1267 }
1268
1269
1270
1271 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
1272
1273
1274
1275
1276 if (direct_fmt && sd_fmt && sensor_preferred)
1277 sd_fmt = direct_fmt;
1278
1279
1280 if (direct_fmt && !sd_fmt)
1281 sd_fmt = direct_fmt;
1282
1283
1284
1285
1286 if (sd_fmt == direct_fmt)
1287 rlp_dma_direct_dump = true;
1288
1289
1290
1291
1292
1293 if (!sd_fmt && !direct_fmt) {
1294 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
1295 v4l2_dbg(1, debug, &isc->v4l2_dev,
1296 "Sensor not supporting %.4s, using %.4s\n",
1297 (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
1298 }
1299
1300 if (!sd_fmt) {
1301 ret = -EINVAL;
1302 goto isc_try_fmt_err;
1303 }
1304
1305
1306 v4l2_dbg(1, debug, &isc->v4l2_dev,
1307 "Preferring to have sensor using format %.4s\n",
1308 (char *)&sd_fmt->fourcc);
1309
1310
1311 isc->try_config.sd_format = sd_fmt;
1312
1313
1314 if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
1315 pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
1316 if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
1317 pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
1318
1319
1320
1321
1322
1323 mbus_code = sd_fmt->mbus_code;
1324
1325
1326
1327
1328
1329 isc->try_config.fourcc = pixfmt->pixelformat;
1330
1331 if (isc_try_validate_formats(isc)) {
1332 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
1333
1334 ret = isc_try_validate_formats(isc);
1335 if (ret)
1336 goto isc_try_fmt_err;
1337 }
1338
1339 ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
1340 if (ret)
1341 goto isc_try_fmt_err;
1342
1343 ret = isc_try_configure_pipeline(isc);
1344 if (ret)
1345 goto isc_try_fmt_err;
1346
1347
1348 isc_try_fse(isc, &pad_cfg);
1349
1350 v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
1351 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
1352 &pad_cfg, &format);
1353 if (ret < 0)
1354 goto isc_try_fmt_subdev_err;
1355
1356 v4l2_fill_pix_format(pixfmt, &format.format);
1357
1358 pixfmt->field = V4L2_FIELD_NONE;
1359 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
1360 pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
1361
1362 if (code)
1363 *code = mbus_code;
1364
1365 return 0;
1366
1367isc_try_fmt_err:
1368 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
1369isc_try_fmt_subdev_err:
1370 memset(&isc->try_config, 0, sizeof(isc->try_config));
1371
1372 return ret;
1373}
1374
1375static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
1376{
1377 struct v4l2_subdev_format format = {
1378 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1379 };
1380 u32 mbus_code = 0;
1381 int ret;
1382
1383 ret = isc_try_fmt(isc, f, &mbus_code);
1384 if (ret)
1385 return ret;
1386
1387 v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1388 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1389 set_fmt, NULL, &format);
1390 if (ret < 0)
1391 return ret;
1392
1393 isc->fmt = *f;
1394
1395 if (isc->try_config.sd_format && isc->config.sd_format &&
1396 isc->try_config.sd_format != isc->config.sd_format) {
1397 isc->ctrls.hist_stat = HIST_INIT;
1398 isc_reset_awb_ctrls(isc);
1399 }
1400
1401 isc->config = isc->try_config;
1402
1403 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1404
1405 return 0;
1406}
1407
1408static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1409 struct v4l2_format *f)
1410{
1411 struct isc_device *isc = video_drvdata(file);
1412
1413 if (vb2_is_streaming(&isc->vb2_vidq))
1414 return -EBUSY;
1415
1416 return isc_set_fmt(isc, f);
1417}
1418
1419static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1420 struct v4l2_format *f)
1421{
1422 struct isc_device *isc = video_drvdata(file);
1423
1424 return isc_try_fmt(isc, f, NULL);
1425}
1426
1427static int isc_enum_input(struct file *file, void *priv,
1428 struct v4l2_input *inp)
1429{
1430 if (inp->index != 0)
1431 return -EINVAL;
1432
1433 inp->type = V4L2_INPUT_TYPE_CAMERA;
1434 inp->std = 0;
1435 strscpy(inp->name, "Camera", sizeof(inp->name));
1436
1437 return 0;
1438}
1439
1440static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1441{
1442 *i = 0;
1443
1444 return 0;
1445}
1446
1447static int isc_s_input(struct file *file, void *priv, unsigned int i)
1448{
1449 if (i > 0)
1450 return -EINVAL;
1451
1452 return 0;
1453}
1454
1455static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1456{
1457 struct isc_device *isc = video_drvdata(file);
1458
1459 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1460}
1461
1462static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1463{
1464 struct isc_device *isc = video_drvdata(file);
1465
1466 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1467}
1468
1469static int isc_enum_framesizes(struct file *file, void *fh,
1470 struct v4l2_frmsizeenum *fsize)
1471{
1472 struct isc_device *isc = video_drvdata(file);
1473 struct v4l2_subdev_frame_size_enum fse = {
1474 .code = isc->config.sd_format->mbus_code,
1475 .index = fsize->index,
1476 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1477 };
1478 int ret = -EINVAL;
1479 int i;
1480
1481 for (i = 0; i < isc->num_user_formats; i++)
1482 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1483 ret = 0;
1484
1485 for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1486 if (controller_formats[i].fourcc == fsize->pixel_format)
1487 ret = 0;
1488
1489 if (ret)
1490 return ret;
1491
1492 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
1493 NULL, &fse);
1494 if (ret)
1495 return ret;
1496
1497 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1498 fsize->discrete.width = fse.max_width;
1499 fsize->discrete.height = fse.max_height;
1500
1501 return 0;
1502}
1503
1504static int isc_enum_frameintervals(struct file *file, void *fh,
1505 struct v4l2_frmivalenum *fival)
1506{
1507 struct isc_device *isc = video_drvdata(file);
1508 struct v4l2_subdev_frame_interval_enum fie = {
1509 .code = isc->config.sd_format->mbus_code,
1510 .index = fival->index,
1511 .width = fival->width,
1512 .height = fival->height,
1513 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1514 };
1515 int ret = -EINVAL;
1516 unsigned int i;
1517
1518 for (i = 0; i < isc->num_user_formats; i++)
1519 if (isc->user_formats[i]->fourcc == fival->pixel_format)
1520 ret = 0;
1521
1522 for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
1523 if (controller_formats[i].fourcc == fival->pixel_format)
1524 ret = 0;
1525
1526 if (ret)
1527 return ret;
1528
1529 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1530 enum_frame_interval, NULL, &fie);
1531 if (ret)
1532 return ret;
1533
1534 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1535 fival->discrete = fie.interval;
1536
1537 return 0;
1538}
1539
1540static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1541 .vidioc_querycap = isc_querycap,
1542 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
1543 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
1544 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
1545 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
1546
1547 .vidioc_enum_input = isc_enum_input,
1548 .vidioc_g_input = isc_g_input,
1549 .vidioc_s_input = isc_s_input,
1550
1551 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1552 .vidioc_querybuf = vb2_ioctl_querybuf,
1553 .vidioc_qbuf = vb2_ioctl_qbuf,
1554 .vidioc_expbuf = vb2_ioctl_expbuf,
1555 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1556 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1557 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1558 .vidioc_streamon = vb2_ioctl_streamon,
1559 .vidioc_streamoff = vb2_ioctl_streamoff,
1560
1561 .vidioc_g_parm = isc_g_parm,
1562 .vidioc_s_parm = isc_s_parm,
1563 .vidioc_enum_framesizes = isc_enum_framesizes,
1564 .vidioc_enum_frameintervals = isc_enum_frameintervals,
1565
1566 .vidioc_log_status = v4l2_ctrl_log_status,
1567 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1568 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1569};
1570
1571static int isc_open(struct file *file)
1572{
1573 struct isc_device *isc = video_drvdata(file);
1574 struct v4l2_subdev *sd = isc->current_subdev->sd;
1575 int ret;
1576
1577 if (mutex_lock_interruptible(&isc->lock))
1578 return -ERESTARTSYS;
1579
1580 ret = v4l2_fh_open(file);
1581 if (ret < 0)
1582 goto unlock;
1583
1584 if (!v4l2_fh_is_singular_file(file))
1585 goto unlock;
1586
1587 ret = v4l2_subdev_call(sd, core, s_power, 1);
1588 if (ret < 0 && ret != -ENOIOCTLCMD) {
1589 v4l2_fh_release(file);
1590 goto unlock;
1591 }
1592
1593 ret = isc_set_fmt(isc, &isc->fmt);
1594 if (ret) {
1595 v4l2_subdev_call(sd, core, s_power, 0);
1596 v4l2_fh_release(file);
1597 }
1598
1599unlock:
1600 mutex_unlock(&isc->lock);
1601 return ret;
1602}
1603
1604static int isc_release(struct file *file)
1605{
1606 struct isc_device *isc = video_drvdata(file);
1607 struct v4l2_subdev *sd = isc->current_subdev->sd;
1608 bool fh_singular;
1609 int ret;
1610
1611 mutex_lock(&isc->lock);
1612
1613 fh_singular = v4l2_fh_is_singular_file(file);
1614
1615 ret = _vb2_fop_release(file, NULL);
1616
1617 if (fh_singular)
1618 v4l2_subdev_call(sd, core, s_power, 0);
1619
1620 mutex_unlock(&isc->lock);
1621
1622 return ret;
1623}
1624
1625static const struct v4l2_file_operations isc_fops = {
1626 .owner = THIS_MODULE,
1627 .open = isc_open,
1628 .release = isc_release,
1629 .unlocked_ioctl = video_ioctl2,
1630 .read = vb2_fop_read,
1631 .mmap = vb2_fop_mmap,
1632 .poll = vb2_fop_poll,
1633};
1634
1635irqreturn_t isc_interrupt(int irq, void *dev_id)
1636{
1637 struct isc_device *isc = (struct isc_device *)dev_id;
1638 struct regmap *regmap = isc->regmap;
1639 u32 isc_intsr, isc_intmask, pending;
1640 irqreturn_t ret = IRQ_NONE;
1641
1642 regmap_read(regmap, ISC_INTSR, &isc_intsr);
1643 regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1644
1645 pending = isc_intsr & isc_intmask;
1646
1647 if (likely(pending & ISC_INT_DDONE)) {
1648 spin_lock(&isc->dma_queue_lock);
1649 if (isc->cur_frm) {
1650 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1651 struct vb2_buffer *vb = &vbuf->vb2_buf;
1652
1653 vb->timestamp = ktime_get_ns();
1654 vbuf->sequence = isc->sequence++;
1655 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1656 isc->cur_frm = NULL;
1657 }
1658
1659 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1660 isc->cur_frm = list_first_entry(&isc->dma_queue,
1661 struct isc_buffer, list);
1662 list_del(&isc->cur_frm->list);
1663
1664 isc_start_dma(isc);
1665 }
1666
1667 if (isc->stop)
1668 complete(&isc->comp);
1669
1670 ret = IRQ_HANDLED;
1671 spin_unlock(&isc->dma_queue_lock);
1672 }
1673
1674 if (pending & ISC_INT_HISDONE) {
1675 schedule_work(&isc->awb_work);
1676 ret = IRQ_HANDLED;
1677 }
1678
1679 return ret;
1680}
1681
1682static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1683{
1684 struct regmap *regmap = isc->regmap;
1685 struct isc_ctrls *ctrls = &isc->ctrls;
1686 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1687 u32 *hist_entry = &ctrls->hist_entry[0];
1688 u32 i;
1689
1690 *min = 0;
1691 *max = HIST_ENTRIES;
1692
1693 regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
1694
1695 *hist_count = 0;
1696
1697
1698
1699
1700 for (i = 1; i < HIST_ENTRIES; i++) {
1701 if (*hist_entry && !*min)
1702 *min = i;
1703 if (*hist_entry)
1704 *max = i;
1705 *hist_count += i * (*hist_entry++);
1706 }
1707
1708 if (!*min)
1709 *min = 1;
1710}
1711
1712static void isc_wb_update(struct isc_ctrls *ctrls)
1713{
1714 u32 *hist_count = &ctrls->hist_count[0];
1715 u32 c, offset[4];
1716 u64 avg = 0;
1717
1718 u32 s_gain[4], gw_gain[4];
1719
1720
1721
1722
1723
1724
1725
1726 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1727 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1728 avg >>= 1;
1729
1730
1731 if (!avg)
1732 return;
1733
1734 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1735
1736
1737
1738
1739
1740 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750 ctrls->offset[c] = (offset[c] - 1) << 3;
1751
1752
1753 if (!ctrls->offset[c])
1754 ctrls->offset[c] = ISC_WB_O_ZERO_VAL;
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764 s_gain[c] = (HIST_ENTRIES << 9) /
1765 (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1766 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1767
1768
1769
1770
1771
1772
1773
1774 if (hist_count[c])
1775 gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1776 else
1777 gw_gain[c] = 1 << 9;
1778
1779
1780 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1781 ctrls->gain[c] >>= 9;
1782 }
1783}
1784
1785static void isc_awb_work(struct work_struct *w)
1786{
1787 struct isc_device *isc =
1788 container_of(w, struct isc_device, awb_work);
1789 struct regmap *regmap = isc->regmap;
1790 struct isc_ctrls *ctrls = &isc->ctrls;
1791 u32 hist_id = ctrls->hist_id;
1792 u32 baysel;
1793 unsigned long flags;
1794 u32 min, max;
1795
1796
1797 if (isc->stop)
1798 return;
1799
1800 if (ctrls->hist_stat != HIST_ENABLED)
1801 return;
1802
1803 isc_hist_count(isc, &min, &max);
1804 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1805 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1806
1807 if (hist_id != ISC_HIS_CFG_MODE_B) {
1808 hist_id++;
1809 } else {
1810 isc_wb_update(ctrls);
1811 hist_id = ISC_HIS_CFG_MODE_GR;
1812 }
1813
1814 ctrls->hist_id = hist_id;
1815 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1816
1817
1818 if (ctrls->awb == ISC_WB_NONE)
1819 isc_reset_awb_ctrls(isc);
1820
1821 pm_runtime_get_sync(isc->dev);
1822
1823
1824
1825
1826
1827 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1828
1829
1830
1831
1832
1833
1834 spin_lock_irqsave(&isc->awb_lock, flags);
1835 isc_update_awb_ctrls(isc);
1836 spin_unlock_irqrestore(&isc->awb_lock, flags);
1837
1838
1839
1840
1841
1842 if (ctrls->awb == ISC_WB_ONETIME) {
1843 v4l2_info(&isc->v4l2_dev,
1844 "Completed one time white-balance adjustment.\n");
1845 ctrls->awb = ISC_WB_NONE;
1846 }
1847 }
1848 regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
1849 isc_update_profile(isc);
1850
1851 if (ctrls->awb)
1852 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1853
1854 pm_runtime_put_sync(isc->dev);
1855}
1856
1857static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1858{
1859 struct isc_device *isc = container_of(ctrl->handler,
1860 struct isc_device, ctrls.handler);
1861 struct isc_ctrls *ctrls = &isc->ctrls;
1862
1863 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1864 return 0;
1865
1866 switch (ctrl->id) {
1867 case V4L2_CID_BRIGHTNESS:
1868 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1869 break;
1870 case V4L2_CID_CONTRAST:
1871 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1872 break;
1873 case V4L2_CID_GAMMA:
1874 ctrls->gamma_index = ctrl->val;
1875 break;
1876 case V4L2_CID_AUTO_WHITE_BALANCE:
1877 if (ctrl->val == 1)
1878 ctrls->awb = ISC_WB_AUTO;
1879 else
1880 ctrls->awb = ISC_WB_NONE;
1881
1882
1883 if (!isc->config.sd_format)
1884 break;
1885
1886 if (ctrls->hist_stat != HIST_ENABLED)
1887 isc_reset_awb_ctrls(isc);
1888
1889 if (isc->ctrls.awb == ISC_WB_AUTO &&
1890 vb2_is_streaming(&isc->vb2_vidq) &&
1891 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1892 isc_set_histogram(isc, true);
1893
1894 break;
1895 case V4L2_CID_DO_WHITE_BALANCE:
1896
1897 if (ctrls->awb == ISC_WB_AUTO)
1898 return 0;
1899
1900 ctrls->awb = ISC_WB_ONETIME;
1901 isc_set_histogram(isc, true);
1902 v4l2_dbg(1, debug, &isc->v4l2_dev,
1903 "One time white-balance started.\n");
1904 break;
1905 default:
1906 return -EINVAL;
1907 }
1908
1909 return 0;
1910}
1911
1912static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1913 .s_ctrl = isc_s_ctrl,
1914};
1915
1916static int isc_ctrl_init(struct isc_device *isc)
1917{
1918 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1919 struct isc_ctrls *ctrls = &isc->ctrls;
1920 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1921 int ret;
1922
1923 ctrls->hist_stat = HIST_INIT;
1924 isc_reset_awb_ctrls(isc);
1925
1926 ret = v4l2_ctrl_handler_init(hdl, 5);
1927 if (ret < 0)
1928 return ret;
1929
1930 ctrls->brightness = 0;
1931 ctrls->contrast = 256;
1932
1933 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1934 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
1935 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);
1936 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1937
1938
1939 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DO_WHITE_BALANCE,
1940 0, 0, 0, 0);
1941
1942 if (!isc->do_wb_ctrl) {
1943 ret = hdl->error;
1944 v4l2_ctrl_handler_free(hdl);
1945 return ret;
1946 }
1947
1948 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1949
1950 v4l2_ctrl_handler_setup(hdl);
1951
1952 return 0;
1953}
1954
1955static int isc_async_bound(struct v4l2_async_notifier *notifier,
1956 struct v4l2_subdev *subdev,
1957 struct v4l2_async_subdev *asd)
1958{
1959 struct isc_device *isc = container_of(notifier->v4l2_dev,
1960 struct isc_device, v4l2_dev);
1961 struct isc_subdev_entity *subdev_entity =
1962 container_of(notifier, struct isc_subdev_entity, notifier);
1963
1964 if (video_is_registered(&isc->video_dev)) {
1965 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1966 return -EBUSY;
1967 }
1968
1969 subdev_entity->sd = subdev;
1970
1971 return 0;
1972}
1973
1974static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1975 struct v4l2_subdev *subdev,
1976 struct v4l2_async_subdev *asd)
1977{
1978 struct isc_device *isc = container_of(notifier->v4l2_dev,
1979 struct isc_device, v4l2_dev);
1980 cancel_work_sync(&isc->awb_work);
1981 video_unregister_device(&isc->video_dev);
1982 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1983}
1984
1985static struct isc_format *find_format_by_code(unsigned int code, int *index)
1986{
1987 struct isc_format *fmt = &formats_list[0];
1988 unsigned int i;
1989
1990 for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
1991 if (fmt->mbus_code == code) {
1992 *index = i;
1993 return fmt;
1994 }
1995
1996 fmt++;
1997 }
1998
1999 return NULL;
2000}
2001
2002static int isc_formats_init(struct isc_device *isc)
2003{
2004 struct isc_format *fmt;
2005 struct v4l2_subdev *subdev = isc->current_subdev->sd;
2006 unsigned int num_fmts, i, j;
2007 u32 list_size = ARRAY_SIZE(formats_list);
2008 struct v4l2_subdev_mbus_code_enum mbus_code = {
2009 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2010 };
2011
2012 num_fmts = 0;
2013 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
2014 NULL, &mbus_code)) {
2015 mbus_code.index++;
2016
2017 fmt = find_format_by_code(mbus_code.code, &i);
2018 if (!fmt) {
2019 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
2020 mbus_code.code);
2021 continue;
2022 }
2023
2024 fmt->sd_support = true;
2025 num_fmts++;
2026 }
2027
2028 if (!num_fmts)
2029 return -ENXIO;
2030
2031 isc->num_user_formats = num_fmts;
2032 isc->user_formats = devm_kcalloc(isc->dev,
2033 num_fmts, sizeof(*isc->user_formats),
2034 GFP_KERNEL);
2035 if (!isc->user_formats)
2036 return -ENOMEM;
2037
2038 fmt = &formats_list[0];
2039 for (i = 0, j = 0; i < list_size; i++) {
2040 if (fmt->sd_support)
2041 isc->user_formats[j++] = fmt;
2042 fmt++;
2043 }
2044
2045 return 0;
2046}
2047
2048static int isc_set_default_fmt(struct isc_device *isc)
2049{
2050 struct v4l2_format f = {
2051 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
2052 .fmt.pix = {
2053 .width = VGA_WIDTH,
2054 .height = VGA_HEIGHT,
2055 .field = V4L2_FIELD_NONE,
2056 .pixelformat = isc->user_formats[0]->fourcc,
2057 },
2058 };
2059 int ret;
2060
2061 ret = isc_try_fmt(isc, &f, NULL);
2062 if (ret)
2063 return ret;
2064
2065 isc->fmt = f;
2066 return 0;
2067}
2068
2069static int isc_async_complete(struct v4l2_async_notifier *notifier)
2070{
2071 struct isc_device *isc = container_of(notifier->v4l2_dev,
2072 struct isc_device, v4l2_dev);
2073 struct video_device *vdev = &isc->video_dev;
2074 struct vb2_queue *q = &isc->vb2_vidq;
2075 int ret = 0;
2076
2077 INIT_WORK(&isc->awb_work, isc_awb_work);
2078
2079 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
2080 if (ret < 0) {
2081 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
2082 return ret;
2083 }
2084
2085 isc->current_subdev = container_of(notifier,
2086 struct isc_subdev_entity, notifier);
2087 mutex_init(&isc->lock);
2088 init_completion(&isc->comp);
2089
2090
2091 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2092 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
2093 q->drv_priv = isc;
2094 q->buf_struct_size = sizeof(struct isc_buffer);
2095 q->ops = &isc_vb2_ops;
2096 q->mem_ops = &vb2_dma_contig_memops;
2097 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2098 q->lock = &isc->lock;
2099 q->min_buffers_needed = 1;
2100 q->dev = isc->dev;
2101
2102 ret = vb2_queue_init(q);
2103 if (ret < 0) {
2104 v4l2_err(&isc->v4l2_dev,
2105 "vb2_queue_init() failed: %d\n", ret);
2106 goto isc_async_complete_err;
2107 }
2108
2109
2110 INIT_LIST_HEAD(&isc->dma_queue);
2111 spin_lock_init(&isc->dma_queue_lock);
2112 spin_lock_init(&isc->awb_lock);
2113
2114 ret = isc_formats_init(isc);
2115 if (ret < 0) {
2116 v4l2_err(&isc->v4l2_dev,
2117 "Init format failed: %d\n", ret);
2118 goto isc_async_complete_err;
2119 }
2120
2121 ret = isc_set_default_fmt(isc);
2122 if (ret) {
2123 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
2124 goto isc_async_complete_err;
2125 }
2126
2127 ret = isc_ctrl_init(isc);
2128 if (ret) {
2129 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
2130 goto isc_async_complete_err;
2131 }
2132
2133
2134 strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
2135 vdev->release = video_device_release_empty;
2136 vdev->fops = &isc_fops;
2137 vdev->ioctl_ops = &isc_ioctl_ops;
2138 vdev->v4l2_dev = &isc->v4l2_dev;
2139 vdev->vfl_dir = VFL_DIR_RX;
2140 vdev->queue = q;
2141 vdev->lock = &isc->lock;
2142 vdev->ctrl_handler = &isc->ctrls.handler;
2143 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
2144 video_set_drvdata(vdev, isc);
2145
2146 ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
2147 if (ret < 0) {
2148 v4l2_err(&isc->v4l2_dev,
2149 "video_register_device failed: %d\n", ret);
2150 goto isc_async_complete_err;
2151 }
2152
2153 return 0;
2154
2155isc_async_complete_err:
2156 mutex_destroy(&isc->lock);
2157 return ret;
2158}
2159
2160const struct v4l2_async_notifier_operations isc_async_ops = {
2161 .bound = isc_async_bound,
2162 .unbind = isc_async_unbind,
2163 .complete = isc_async_complete,
2164};
2165
2166void isc_subdev_cleanup(struct isc_device *isc)
2167{
2168 struct isc_subdev_entity *subdev_entity;
2169
2170 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
2171 v4l2_async_notifier_unregister(&subdev_entity->notifier);
2172 v4l2_async_notifier_cleanup(&subdev_entity->notifier);
2173 }
2174
2175 INIT_LIST_HEAD(&isc->subdev_entities);
2176}
2177
2178int isc_pipeline_init(struct isc_device *isc)
2179{
2180 struct device *dev = isc->dev;
2181 struct regmap *regmap = isc->regmap;
2182 struct regmap_field *regs;
2183 unsigned int i;
2184
2185
2186 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
2187 REG_FIELD(ISC_WB_CTRL, 0, 0),
2188 REG_FIELD(ISC_CFA_CTRL, 0, 0),
2189 REG_FIELD(ISC_CC_CTRL, 0, 0),
2190 REG_FIELD(ISC_GAM_CTRL, 0, 0),
2191 REG_FIELD(ISC_GAM_CTRL, 1, 1),
2192 REG_FIELD(ISC_GAM_CTRL, 2, 2),
2193 REG_FIELD(ISC_GAM_CTRL, 3, 3),
2194 REG_FIELD(ISC_CSC_CTRL, 0, 0),
2195 REG_FIELD(ISC_CBC_CTRL, 0, 0),
2196 REG_FIELD(ISC_SUB422_CTRL, 0, 0),
2197 REG_FIELD(ISC_SUB420_CTRL, 0, 0),
2198 };
2199
2200 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
2201 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
2202 if (IS_ERR(regs))
2203 return PTR_ERR(regs);
2204
2205 isc->pipeline[i] = regs;
2206 }
2207
2208 return 0;
2209}
2210
2211
2212#define ATMEL_ISC_REG_MAX 0xbfc
2213const struct regmap_config isc_regmap_config = {
2214 .reg_bits = 32,
2215 .reg_stride = 4,
2216 .val_bits = 32,
2217 .max_register = ATMEL_ISC_REG_MAX,
2218};
2219
2220
