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7#ifndef _MCAM_CORE_H
8#define _MCAM_CORE_H
9
10#include <linux/list.h>
11#include <linux/clk-provider.h>
12#include <media/v4l2-common.h>
13#include <media/v4l2-ctrls.h>
14#include <media/v4l2-dev.h>
15#include <media/videobuf2-v4l2.h>
16
17
18
19
20
21#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
22#define MCAM_MODE_VMALLOC 1
23#endif
24
25#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
26#define MCAM_MODE_DMA_CONTIG 1
27#endif
28
29#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
30#define MCAM_MODE_DMA_SG 1
31#endif
32
33#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
34 !defined(MCAM_MODE_DMA_SG)
35#error One of the videobuf buffer modes must be selected in the config
36#endif
37
38
39enum mcam_state {
40 S_NOTREADY,
41 S_IDLE,
42 S_FLAKED,
43 S_STREAMING,
44 S_BUFWAIT
45};
46#define MAX_DMA_BUFS 3
47
48
49
50
51
52enum mcam_buffer_mode {
53 B_vmalloc = 0,
54 B_DMA_contig = 1,
55 B_DMA_sg = 2
56};
57
58enum mcam_chip_id {
59 MCAM_CAFE,
60 MCAM_ARMADA610,
61};
62
63
64
65
66static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
67{
68 switch (mode) {
69#ifdef MCAM_MODE_VMALLOC
70 case B_vmalloc:
71#endif
72#ifdef MCAM_MODE_DMA_CONTIG
73 case B_DMA_contig:
74#endif
75#ifdef MCAM_MODE_DMA_SG
76 case B_DMA_sg:
77#endif
78 return 1;
79 default:
80 return 0;
81 }
82}
83
84
85
86
87struct mcam_frame_state {
88 unsigned int frames;
89 unsigned int singles;
90 unsigned int delivered;
91};
92
93#define NR_MCAM_CLK 3
94
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96
97
98
99
100
101struct mcam_camera {
102
103
104
105
106 unsigned char __iomem *regs;
107 unsigned regs_size;
108 spinlock_t dev_lock;
109 struct device *dev;
110 enum mcam_chip_id chip_id;
111 enum mcam_buffer_mode buffer_mode;
112
113 int mclk_src;
114 int mclk_div;
115
116 enum v4l2_mbus_type bus_type;
117
118
119
120
121
122
123 int *dphy;
124 bool mipi_enabled;
125 int lane;
126
127
128 struct clk *clk[NR_MCAM_CLK];
129 struct clk_hw mclk_hw;
130 struct clk *mclk;
131
132
133
134
135 int (*plat_power_up) (struct mcam_camera *cam);
136 void (*plat_power_down) (struct mcam_camera *cam);
137 void (*calc_dphy) (struct mcam_camera *cam);
138
139
140
141
142
143 struct v4l2_device v4l2_dev;
144 struct v4l2_ctrl_handler ctrl_handler;
145 enum mcam_state state;
146 unsigned long flags;
147
148 struct mcam_frame_state frame_state;
149
150
151
152 struct video_device vdev;
153 struct v4l2_async_notifier notifier;
154 struct v4l2_async_subdev asd;
155 struct v4l2_subdev *sensor;
156
157
158 struct vb2_queue vb_queue;
159 struct list_head buffers;
160
161 unsigned int nbufs;
162 int next_buf;
163
164 char bus_info[32];
165
166
167#ifdef MCAM_MODE_VMALLOC
168 unsigned int dma_buf_size;
169 void *dma_bufs[MAX_DMA_BUFS];
170 dma_addr_t dma_handles[MAX_DMA_BUFS];
171 struct tasklet_struct s_tasklet;
172#endif
173 unsigned int sequence;
174 unsigned int buf_seq[MAX_DMA_BUFS];
175
176
177 struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
178
179
180 void (*dma_setup)(struct mcam_camera *cam);
181 void (*frame_complete)(struct mcam_camera *cam, int frame);
182
183
184 struct v4l2_pix_format pix_format;
185 u32 mbus_code;
186
187
188 struct mutex s_mutex;
189};
190
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195
196
197
198
199static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
200 unsigned int val)
201{
202 iowrite32(val, cam->regs + reg);
203}
204
205static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
206 unsigned int reg)
207{
208 return ioread32(cam->regs + reg);
209}
210
211
212static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
213 unsigned int val, unsigned int mask)
214{
215 unsigned int v = mcam_reg_read(cam, reg);
216
217 v = (v & ~mask) | (val & mask);
218 mcam_reg_write(cam, reg, v);
219}
220
221static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
222 unsigned int reg, unsigned int val)
223{
224 mcam_reg_write_mask(cam, reg, 0, val);
225}
226
227static inline void mcam_reg_set_bit(struct mcam_camera *cam,
228 unsigned int reg, unsigned int val)
229{
230 mcam_reg_write_mask(cam, reg, val, val);
231}
232
233
234
235
236int mccic_register(struct mcam_camera *cam);
237int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
238void mccic_shutdown(struct mcam_camera *cam);
239#ifdef CONFIG_PM
240void mccic_suspend(struct mcam_camera *cam);
241int mccic_resume(struct mcam_camera *cam);
242#endif
243
244
245
246
247
248#define REG_Y0BAR 0x00
249#define REG_Y1BAR 0x04
250#define REG_Y2BAR 0x08
251#define REG_U0BAR 0x0c
252#define REG_U1BAR 0x10
253#define REG_U2BAR 0x14
254#define REG_V0BAR 0x18
255#define REG_V1BAR 0x1C
256#define REG_V2BAR 0x20
257
258
259
260
261#define REG_CSI2_CTRL0 0x100
262#define CSI2_C0_MIPI_EN (0x1 << 0)
263#define CSI2_C0_ACT_LANE(n) ((n-1) << 1)
264#define REG_CSI2_DPHY3 0x12c
265#define REG_CSI2_DPHY5 0x134
266#define REG_CSI2_DPHY6 0x138
267
268
269
270#define REG_IMGPITCH 0x24
271#define IMGP_YP_SHFT 2
272#define IMGP_YP_MASK 0x00003ffc
273#define IMGP_UVP_SHFT 18
274#define IMGP_UVP_MASK 0x3ffc0000
275#define REG_IRQSTATRAW 0x28
276#define IRQ_EOF0 0x00000001
277#define IRQ_EOF1 0x00000002
278#define IRQ_EOF2 0x00000004
279#define IRQ_SOF0 0x00000008
280#define IRQ_SOF1 0x00000010
281#define IRQ_SOF2 0x00000020
282#define IRQ_OVERFLOW 0x00000040
283#define IRQ_TWSIW 0x00010000
284#define IRQ_TWSIR 0x00020000
285#define IRQ_TWSIE 0x00040000
286#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
287#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
288#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
289#define REG_IRQMASK 0x2c
290#define REG_IRQSTAT 0x30
291
292#define REG_IMGSIZE 0x34
293#define IMGSZ_V_MASK 0x1fff0000
294#define IMGSZ_V_SHIFT 16
295#define IMGSZ_H_MASK 0x00003fff
296#define REG_IMGOFFSET 0x38
297
298#define REG_CTRL0 0x3c
299#define C0_ENABLE 0x00000001
300
301
302#define C0_DF_MASK 0x00fffffc
303
304
305#define C0_RGB4_RGBX 0x00000000
306#define C0_RGB4_XRGB 0x00000004
307#define C0_RGB4_BGRX 0x00000008
308#define C0_RGB4_XBGR 0x0000000c
309#define C0_RGB5_RGGB 0x00000000
310#define C0_RGB5_GRBG 0x00000004
311#define C0_RGB5_GBRG 0x00000008
312#define C0_RGB5_BGGR 0x0000000c
313
314
315
316#define C0_DF_YUV 0x00000000
317#define C0_DF_RGB 0x000000a0
318#define C0_DF_BAYER 0x00000140
319
320#define C0_RGBF_565 0x00000000
321#define C0_RGBF_444 0x00000800
322#define C0_RGB_BGR 0x00001000
323#define C0_YUV_PLANAR 0x00000000
324#define C0_YUV_PACKED 0x00008000
325#define C0_YUV_420PL 0x0000a000
326
327#define C0_YUVE_YUYV 0x00000000
328#define C0_YUVE_YVYU 0x00010000
329#define C0_YUVE_VYUY 0x00020000
330#define C0_YUVE_UYVY 0x00030000
331#define C0_YUVE_NOSWAP 0x00000000
332#define C0_YUVE_SWAP13 0x00010000
333#define C0_YUVE_SWAP24 0x00020000
334#define C0_YUVE_SWAP1324 0x00030000
335
336#define C0_EOF_VSYNC 0x00400000
337#define C0_VEDGE_CTRL 0x00800000
338#define C0_HPOL_LOW 0x01000000
339#define C0_VPOL_LOW 0x02000000
340#define C0_VCLK_LOW 0x04000000
341#define C0_DOWNSCALE 0x08000000
342
343#define C0_SIF_HVSYNC 0x00000000
344#define C0_SOF_NOSYNC 0x40000000
345#define C0_SIFM_MASK 0xc0000000
346
347
348#define REG_CTRL1 0x40
349#define C1_CLKGATE 0x00000001
350#define C1_DESC_ENA 0x00000100
351#define C1_DESC_3WORD 0x00000200
352#define C1_444ALPHA 0x00f00000
353#define C1_ALPHA_SHFT 20
354#define C1_DMAB32 0x00000000
355#define C1_DMAB16 0x02000000
356#define C1_DMAB64 0x04000000
357#define C1_DMAB_MASK 0x06000000
358#define C1_TWOBUFS 0x08000000
359#define C1_PWRDWN 0x10000000
360
361#define REG_CLKCTRL 0x88
362#define CLK_DIV_MASK 0x0000ffff
363
364
365#define REG_UBAR 0xc4
366
367
368#define REG_DMA_DESC_Y 0x200
369#define REG_DMA_DESC_U 0x204
370#define REG_DMA_DESC_V 0x208
371#define REG_DESC_LEN_Y 0x20c
372#define REG_DESC_LEN_U 0x210
373#define REG_DESC_LEN_V 0x214
374
375
376
377
378#define VGA_WIDTH 640
379#define VGA_HEIGHT 480
380
381#endif
382