1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35
36#include <linux/fsl/guts.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/module.h>
40#include <linux/of_platform.h>
41#include <linux/clk.h>
42#include <linux/of_address.h>
43#include <linux/of_irq.h>
44#include <linux/interrupt.h>
45#include <linux/libfdt_env.h>
46
47#include "fman.h"
48#include "fman_muram.h"
49#include "fman_keygen.h"
50
51
52#define FMAN_LIODN_TBL 64
53#define MAX_NUM_OF_MACS 10
54#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
55#define BASE_RX_PORTID 0x08
56#define BASE_TX_PORTID 0x28
57
58
59#define BMI_OFFSET 0x00080000
60#define QMI_OFFSET 0x00080400
61#define KG_OFFSET 0x000C1000
62#define DMA_OFFSET 0x000C2000
63#define FPM_OFFSET 0x000C3000
64#define IMEM_OFFSET 0x000C4000
65#define HWP_OFFSET 0x000C7000
66#define CGP_OFFSET 0x000DB000
67
68
69#define EX_DMA_BUS_ERROR 0x80000000
70#define EX_DMA_READ_ECC 0x40000000
71#define EX_DMA_SYSTEM_WRITE_ECC 0x20000000
72#define EX_DMA_FM_WRITE_ECC 0x10000000
73#define EX_FPM_STALL_ON_TASKS 0x08000000
74#define EX_FPM_SINGLE_ECC 0x04000000
75#define EX_FPM_DOUBLE_ECC 0x02000000
76#define EX_QMI_SINGLE_ECC 0x01000000
77#define EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000
78#define EX_QMI_DOUBLE_ECC 0x00400000
79#define EX_BMI_LIST_RAM_ECC 0x00200000
80#define EX_BMI_STORAGE_PROFILE_ECC 0x00100000
81#define EX_BMI_STATISTICS_RAM_ECC 0x00080000
82#define EX_IRAM_ECC 0x00040000
83#define EX_MURAM_ECC 0x00020000
84#define EX_BMI_DISPATCH_RAM_ECC 0x00010000
85#define EX_DMA_SINGLE_PORT_ECC 0x00008000
86
87
88
89#define DMA_MODE_BER 0x00200000
90#define DMA_MODE_ECC 0x00000020
91#define DMA_MODE_SECURE_PROT 0x00000800
92#define DMA_MODE_AXI_DBG_MASK 0x0F000000
93
94#define DMA_TRANSFER_PORTID_MASK 0xFF000000
95#define DMA_TRANSFER_TNUM_MASK 0x00FF0000
96#define DMA_TRANSFER_LIODN_MASK 0x00000FFF
97
98#define DMA_STATUS_BUS_ERR 0x08000000
99#define DMA_STATUS_READ_ECC 0x04000000
100#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000
101#define DMA_STATUS_FM_WRITE_ECC 0x01000000
102#define DMA_STATUS_FM_SPDAT_ECC 0x00080000
103
104#define DMA_MODE_CACHE_OR_SHIFT 30
105#define DMA_MODE_AXI_DBG_SHIFT 24
106#define DMA_MODE_CEN_SHIFT 13
107#define DMA_MODE_CEN_MASK 0x00000007
108#define DMA_MODE_DBG_SHIFT 7
109#define DMA_MODE_AID_MODE_SHIFT 4
110
111#define DMA_THRESH_COMMQ_SHIFT 24
112#define DMA_THRESH_READ_INT_BUF_SHIFT 16
113#define DMA_THRESH_READ_INT_BUF_MASK 0x0000003f
114#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000003f
115
116#define DMA_TRANSFER_PORTID_SHIFT 24
117#define DMA_TRANSFER_TNUM_SHIFT 16
118
119#define DMA_CAM_SIZEOF_ENTRY 0x40
120#define DMA_CAM_UNITS 8
121
122#define DMA_LIODN_SHIFT 16
123#define DMA_LIODN_BASE_MASK 0x00000FFF
124
125
126#define FPM_EV_MASK_DOUBLE_ECC 0x80000000
127#define FPM_EV_MASK_STALL 0x40000000
128#define FPM_EV_MASK_SINGLE_ECC 0x20000000
129#define FPM_EV_MASK_RELEASE_FM 0x00010000
130#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000
131#define FPM_EV_MASK_STALL_EN 0x00004000
132#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000
133#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008
134#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004
135
136#define FPM_RAM_MURAM_ECC 0x00008000
137#define FPM_RAM_IRAM_ECC 0x00004000
138#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000
139#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
140#define FPM_RAM_IRAM_ECC_EN 0x40000000
141#define FPM_RAM_RAMS_ECC_EN 0x80000000
142#define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000
143
144#define FPM_REV1_MAJOR_MASK 0x0000FF00
145#define FPM_REV1_MINOR_MASK 0x000000FF
146
147#define FPM_DISP_LIMIT_SHIFT 24
148
149#define FPM_PRT_FM_CTL1 0x00000001
150#define FPM_PRT_FM_CTL2 0x00000002
151#define FPM_PORT_FM_CTL_PORTID_SHIFT 24
152#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16
153
154#define FPM_THR1_PRS_SHIFT 24
155#define FPM_THR1_KG_SHIFT 16
156#define FPM_THR1_PLCR_SHIFT 8
157#define FPM_THR1_BMI_SHIFT 0
158
159#define FPM_THR2_QMI_ENQ_SHIFT 24
160#define FPM_THR2_QMI_DEQ_SHIFT 0
161#define FPM_THR2_FM_CTL1_SHIFT 16
162#define FPM_THR2_FM_CTL2_SHIFT 8
163
164#define FPM_EV_MASK_CAT_ERR_SHIFT 1
165#define FPM_EV_MASK_DMA_ERR_SHIFT 0
166
167#define FPM_REV1_MAJOR_SHIFT 8
168
169#define FPM_RSTC_FM_RESET 0x80000000
170#define FPM_RSTC_MAC0_RESET 0x40000000
171#define FPM_RSTC_MAC1_RESET 0x20000000
172#define FPM_RSTC_MAC2_RESET 0x10000000
173#define FPM_RSTC_MAC3_RESET 0x08000000
174#define FPM_RSTC_MAC8_RESET 0x04000000
175#define FPM_RSTC_MAC4_RESET 0x02000000
176#define FPM_RSTC_MAC5_RESET 0x01000000
177#define FPM_RSTC_MAC6_RESET 0x00800000
178#define FPM_RSTC_MAC7_RESET 0x00400000
179#define FPM_RSTC_MAC9_RESET 0x00200000
180
181#define FPM_TS_INT_SHIFT 16
182#define FPM_TS_CTL_EN 0x80000000
183
184
185#define BMI_INIT_START 0x80000000
186#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
187#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
188#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
189#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
190#define BMI_NUM_OF_TASKS_MASK 0x3F000000
191#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000
192#define BMI_NUM_OF_DMAS_MASK 0x00000F00
193#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F
194#define BMI_FIFO_SIZE_MASK 0x000003FF
195#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000
196#define BMI_CFG2_DMAS_MASK 0x0000003F
197#define BMI_CFG2_TASKS_MASK 0x0000003F
198
199#define BMI_CFG2_TASKS_SHIFT 16
200#define BMI_CFG2_DMAS_SHIFT 0
201#define BMI_CFG1_FIFO_SIZE_SHIFT 16
202#define BMI_NUM_OF_TASKS_SHIFT 24
203#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16
204#define BMI_NUM_OF_DMAS_SHIFT 8
205#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0
206
207#define BMI_FIFO_ALIGN 0x100
208
209#define BMI_EXTRA_FIFO_SIZE_SHIFT 16
210
211
212#define QMI_CFG_ENQ_EN 0x80000000
213#define QMI_CFG_DEQ_EN 0x40000000
214#define QMI_CFG_EN_COUNTERS 0x10000000
215#define QMI_CFG_DEQ_MASK 0x0000003F
216#define QMI_CFG_ENQ_MASK 0x00003F00
217#define QMI_CFG_ENQ_SHIFT 8
218
219#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
220#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
221#define QMI_INTR_EN_SINGLE_ECC 0x80000000
222
223#define QMI_GS_HALT_NOT_BUSY 0x00000002
224
225
226#define HWP_RPIMAC_PEN 0x00000001
227
228
229#define IRAM_IADD_AIE 0x80000000
230#define IRAM_READY 0x80000000
231
232
233#define DEFAULT_CATASTROPHIC_ERR 0
234#define DEFAULT_DMA_ERR 0
235#define DEFAULT_AID_MODE FMAN_DMA_AID_OUT_TNUM
236#define DEFAULT_DMA_COMM_Q_LOW 0x2A
237#define DEFAULT_DMA_COMM_Q_HIGH 0x3F
238#define DEFAULT_CACHE_OVERRIDE 0
239#define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64
240#define DEFAULT_DMA_DBG_CNT_MODE 0
241#define DEFAULT_DMA_SOS_EMERGENCY 0
242#define DEFAULT_DMA_WATCHDOG 0
243#define DEFAULT_DISP_LIMIT 0
244#define DEFAULT_PRS_DISP_TH 16
245#define DEFAULT_PLCR_DISP_TH 16
246#define DEFAULT_KG_DISP_TH 16
247#define DEFAULT_BMI_DISP_TH 16
248#define DEFAULT_QMI_ENQ_DISP_TH 16
249#define DEFAULT_QMI_DEQ_DISP_TH 16
250#define DEFAULT_FM_CTL1_DISP_TH 16
251#define DEFAULT_FM_CTL2_DISP_TH 16
252
253#define DFLT_AXI_DBG_NUM_OF_BEATS 1
254
255#define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf) \
256 ((dma_thresh_max_buf + 1) / 2)
257#define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf) \
258 ((dma_thresh_max_buf + 1) * 3 / 4)
259#define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf) \
260 ((dma_thresh_max_buf + 1) / 2)
261#define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\
262 ((dma_thresh_max_buf + 1) * 3 / 4)
263
264#define DMA_COMM_Q_LOW_FMAN_V3 0x2A
265#define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq) \
266 ((dma_thresh_max_commq + 1) / 2)
267#define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq) \
268 ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 : \
269 DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq))
270
271#define DMA_COMM_Q_HIGH_FMAN_V3 0x3f
272#define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq) \
273 ((dma_thresh_max_commq + 1) * 3 / 4)
274#define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq) \
275 ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 : \
276 DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq))
277
278#define TOTAL_NUM_OF_TASKS_FMAN_V3L 59
279#define TOTAL_NUM_OF_TASKS_FMAN_V3H 124
280#define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks) \
281 ((major == 6) ? ((minor == 1 || minor == 4) ? \
282 TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) : \
283 bmi_max_num_of_tasks)
284
285#define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 64
286#define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2 32
287#define DFLT_DMA_CAM_NUM_OF_ENTRIES(major) \
288 (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 : \
289 DMA_CAM_NUM_OF_ENTRIES_FMAN_V2)
290
291#define FM_TIMESTAMP_1_USEC_BIT 8
292
293
294#define ERR_INTR_EN_DMA 0x00010000
295#define ERR_INTR_EN_FPM 0x80000000
296#define ERR_INTR_EN_BMI 0x00800000
297#define ERR_INTR_EN_QMI 0x00400000
298#define ERR_INTR_EN_MURAM 0x00040000
299#define ERR_INTR_EN_MAC0 0x00004000
300#define ERR_INTR_EN_MAC1 0x00002000
301#define ERR_INTR_EN_MAC2 0x00001000
302#define ERR_INTR_EN_MAC3 0x00000800
303#define ERR_INTR_EN_MAC4 0x00000400
304#define ERR_INTR_EN_MAC5 0x00000200
305#define ERR_INTR_EN_MAC6 0x00000100
306#define ERR_INTR_EN_MAC7 0x00000080
307#define ERR_INTR_EN_MAC8 0x00008000
308#define ERR_INTR_EN_MAC9 0x00000040
309
310#define INTR_EN_QMI 0x40000000
311#define INTR_EN_MAC0 0x00080000
312#define INTR_EN_MAC1 0x00040000
313#define INTR_EN_MAC2 0x00020000
314#define INTR_EN_MAC3 0x00010000
315#define INTR_EN_MAC4 0x00000040
316#define INTR_EN_MAC5 0x00000020
317#define INTR_EN_MAC6 0x00000008
318#define INTR_EN_MAC7 0x00000002
319#define INTR_EN_MAC8 0x00200000
320#define INTR_EN_MAC9 0x00100000
321#define INTR_EN_REV0 0x00008000
322#define INTR_EN_REV1 0x00004000
323#define INTR_EN_REV2 0x00002000
324#define INTR_EN_REV3 0x00001000
325#define INTR_EN_TMR 0x01000000
326
327enum fman_dma_aid_mode {
328 FMAN_DMA_AID_OUT_PORT_ID = 0,
329 FMAN_DMA_AID_OUT_TNUM
330};
331
332struct fman_iram_regs {
333 u32 iadd;
334 u32 idata;
335 u32 itcfg;
336 u32 iready;
337};
338
339struct fman_fpm_regs {
340 u32 fmfp_tnc;
341 u32 fmfp_prc;
342 u32 fmfp_brkc;
343 u32 fmfp_mxd;
344 u32 fmfp_dist1;
345 u32 fmfp_dist2;
346 u32 fm_epi;
347 u32 fm_rie;
348 u32 fmfp_fcev[4];
349 u32 res0030[4];
350 u32 fmfp_cee[4];
351 u32 res0050[4];
352 u32 fmfp_tsc1;
353 u32 fmfp_tsc2;
354 u32 fmfp_tsp;
355 u32 fmfp_tsf;
356 u32 fm_rcr;
357 u32 fmfp_extc;
358 u32 fmfp_ext1;
359 u32 fmfp_ext2;
360 u32 fmfp_drd[16];
361 u32 fmfp_dra;
362 u32 fm_ip_rev_1;
363 u32 fm_ip_rev_2;
364 u32 fm_rstc;
365 u32 fm_cld;
366 u32 fm_npi;
367 u32 fmfp_exte;
368 u32 fmfp_ee;
369 u32 fmfp_cev[4];
370 u32 res00f0[4];
371 u32 fmfp_ps[50];
372 u32 res01c8[14];
373 u32 fmfp_clfabc;
374 u32 fmfp_clfcc;
375 u32 fmfp_clfaval;
376 u32 fmfp_clfbval;
377 u32 fmfp_clfcval;
378 u32 fmfp_clfamsk;
379 u32 fmfp_clfbmsk;
380 u32 fmfp_clfcmsk;
381 u32 fmfp_clfamc;
382 u32 fmfp_clfbmc;
383 u32 fmfp_clfcmc;
384 u32 fmfp_decceh;
385 u32 res0230[116];
386 u32 fmfp_ts[128];
387 u32 res0600[0x400 - 384];
388};
389
390struct fman_bmi_regs {
391 u32 fmbm_init;
392 u32 fmbm_cfg1;
393 u32 fmbm_cfg2;
394 u32 res000c[5];
395 u32 fmbm_ievr;
396 u32 fmbm_ier;
397 u32 fmbm_ifr;
398 u32 res002c[5];
399 u32 fmbm_arb[8];
400 u32 res0060[12];
401 u32 fmbm_dtc[3];
402 u32 res009c;
403 u32 fmbm_dcv[3][4];
404 u32 fmbm_dcm[3][4];
405 u32 fmbm_gde;
406 u32 fmbm_pp[63];
407 u32 res0200;
408 u32 fmbm_pfs[63];
409 u32 res0300;
410 u32 fmbm_spliodn[63];
411};
412
413struct fman_qmi_regs {
414 u32 fmqm_gc;
415 u32 res0004;
416 u32 fmqm_eie;
417 u32 fmqm_eien;
418 u32 fmqm_eif;
419 u32 fmqm_ie;
420 u32 fmqm_ien;
421 u32 fmqm_if;
422 u32 fmqm_gs;
423 u32 fmqm_ts;
424 u32 fmqm_etfc;
425 u32 fmqm_dtfc;
426 u32 fmqm_dc0;
427 u32 fmqm_dc1;
428 u32 fmqm_dc2;
429 u32 fmqm_dc3;
430 u32 fmqm_dfdc;
431 u32 fmqm_dfcc;
432 u32 fmqm_dffc;
433 u32 fmqm_dcc;
434 u32 res0050[7];
435 u32 fmqm_tapc;
436 u32 fmqm_dmcvc;
437 u32 fmqm_difdcc;
438 u32 fmqm_da1v;
439 u32 res007c;
440 u32 fmqm_dtc;
441 u32 fmqm_efddd;
442 u32 res0088[2];
443 struct {
444 u32 fmqm_dtcfg1;
445 u32 fmqm_dtval1;
446 u32 fmqm_dtm1;
447 u32 fmqm_dtc1;
448 u32 fmqm_dtcfg2;
449 u32 fmqm_dtval2;
450 u32 fmqm_dtm2;
451 u32 res001c;
452 } dbg_traps[3];
453 u8 res00f0[0x400 - 0xf0];
454};
455
456struct fman_dma_regs {
457 u32 fmdmsr;
458 u32 fmdmmr;
459 u32 fmdmtr;
460 u32 fmdmhy;
461 u32 fmdmsetr;
462 u32 fmdmtah;
463 u32 fmdmtal;
464 u32 fmdmtcid;
465 u32 fmdmra;
466 u32 fmdmrd;
467 u32 fmdmwcr;
468 u32 fmdmebcr;
469 u32 fmdmccqdr;
470 u32 fmdmccqvr1;
471 u32 fmdmccqvr2;
472 u32 fmdmcqvr3;
473 u32 fmdmcqvr4;
474 u32 fmdmcqvr5;
475 u32 fmdmsefrc;
476 u32 fmdmsqfrc;
477 u32 fmdmssrc;
478 u32 fmdmdcr;
479 u32 fmdmemsr;
480 u32 res005c;
481 u32 fmdmplr[FMAN_LIODN_TBL / 2];
482 u32 res00e0[0x400 - 56];
483};
484
485struct fman_hwp_regs {
486 u32 res0000[0x844 / 4];
487 u32 fmprrpimac;
488 u32 res[(0x1000 - 0x848) / 4];
489};
490
491
492
493
494struct fman_state_struct {
495 u8 fm_id;
496 u16 fm_clk_freq;
497 struct fman_rev_info rev_info;
498 bool enabled_time_stamp;
499 u8 count1_micro_bit;
500 u8 total_num_of_tasks;
501 u8 accumulated_num_of_tasks;
502 u32 accumulated_fifo_size;
503 u8 accumulated_num_of_open_dmas;
504 u8 accumulated_num_of_deq_tnums;
505 u32 exceptions;
506 u32 extra_fifo_pool_size;
507 u8 extra_tasks_pool_size;
508 u8 extra_open_dmas_pool_size;
509 u16 port_mfl[MAX_NUM_OF_MACS];
510 u16 mac_mfl[MAX_NUM_OF_MACS];
511
512
513 u32 fm_iram_size;
514
515 u32 dma_thresh_max_commq;
516 u32 dma_thresh_max_buf;
517 u32 max_num_of_open_dmas;
518
519 u32 qmi_max_num_of_tnums;
520 u32 qmi_def_tnums_thresh;
521
522 u32 bmi_max_num_of_tasks;
523 u32 bmi_max_fifo_size;
524
525 u32 fm_port_num_of_cg;
526 u32 num_of_rx_ports;
527 u32 total_fifo_size;
528
529 u32 qman_channel_base;
530 u32 num_of_qman_channels;
531
532 struct resource *res;
533};
534
535
536struct fman_cfg {
537 u8 disp_limit_tsh;
538 u8 prs_disp_tsh;
539 u8 plcr_disp_tsh;
540 u8 kg_disp_tsh;
541 u8 bmi_disp_tsh;
542 u8 qmi_enq_disp_tsh;
543 u8 qmi_deq_disp_tsh;
544 u8 fm_ctl1_disp_tsh;
545 u8 fm_ctl2_disp_tsh;
546 int dma_cache_override;
547 enum fman_dma_aid_mode dma_aid_mode;
548 u32 dma_axi_dbg_num_of_beats;
549 u32 dma_cam_num_of_entries;
550 u32 dma_watchdog;
551 u8 dma_comm_qtsh_asrt_emer;
552 u32 dma_write_buf_tsh_asrt_emer;
553 u32 dma_read_buf_tsh_asrt_emer;
554 u8 dma_comm_qtsh_clr_emer;
555 u32 dma_write_buf_tsh_clr_emer;
556 u32 dma_read_buf_tsh_clr_emer;
557 u32 dma_sos_emergency;
558 int dma_dbg_cnt_mode;
559 int catastrophic_err;
560 int dma_err;
561 u32 exceptions;
562 u16 clk_freq;
563 u32 cam_base_addr;
564 u32 fifo_base_addr;
565 u32 total_fifo_size;
566 u32 total_num_of_tasks;
567 u32 qmi_def_tnums_thresh;
568};
569
570#ifdef CONFIG_DPAA_ERRATUM_A050385
571static bool fman_has_err_a050385;
572#endif
573
574static irqreturn_t fman_exceptions(struct fman *fman,
575 enum fman_exceptions exception)
576{
577 dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n",
578 __func__, fman->state->fm_id, exception);
579
580 return IRQ_HANDLED;
581}
582
583static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id,
584 u64 __maybe_unused addr,
585 u8 __maybe_unused tnum,
586 u16 __maybe_unused liodn)
587{
588 dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n",
589 __func__, fman->state->fm_id, port_id);
590
591 return IRQ_HANDLED;
592}
593
594static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id)
595{
596 if (fman->intr_mng[id].isr_cb) {
597 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle);
598
599 return IRQ_HANDLED;
600 }
601
602 return IRQ_NONE;
603}
604
605static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id)
606{
607 u8 sw_port_id = 0;
608
609 if (hw_port_id >= BASE_TX_PORTID)
610 sw_port_id = hw_port_id - BASE_TX_PORTID;
611 else if (hw_port_id >= BASE_RX_PORTID)
612 sw_port_id = hw_port_id - BASE_RX_PORTID;
613 else
614 sw_port_id = 0;
615
616 return sw_port_id;
617}
618
619static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg,
620 u8 port_id)
621{
622 u32 tmp = 0;
623
624 tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT;
625
626 tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
627
628
629 if (port_id % 2)
630 tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
631 else
632 tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
633
634 iowrite32be(tmp, &fpm_rg->fmfp_prc);
635}
636
637static void set_port_liodn(struct fman *fman, u8 port_id,
638 u32 liodn_base, u32 liodn_ofst)
639{
640 u32 tmp;
641
642 iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
643 if (!IS_ENABLED(CONFIG_FSL_PAMU))
644 return;
645
646 tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
647 if (port_id % 2) {
648 tmp &= ~DMA_LIODN_BASE_MASK;
649 tmp |= liodn_base;
650 } else {
651 tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
652 tmp |= liodn_base << DMA_LIODN_SHIFT;
653 }
654 iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
655}
656
657static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
658{
659 u32 tmp;
660
661 tmp = ioread32be(&fpm_rg->fm_rcr);
662 if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
663 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
664 else
665 iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
666 FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
667}
668
669static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
670{
671 u32 tmp;
672
673 tmp = ioread32be(&fpm_rg->fm_rcr);
674 if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
675 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
676 else
677 iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
678 &fpm_rg->fm_rcr);
679}
680
681static void fman_defconfig(struct fman_cfg *cfg)
682{
683 memset(cfg, 0, sizeof(struct fman_cfg));
684
685 cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
686 cfg->dma_err = DEFAULT_DMA_ERR;
687 cfg->dma_aid_mode = DEFAULT_AID_MODE;
688 cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
689 cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
690 cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
691 cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
692 cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
693 cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
694 cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
695 cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
696 cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
697 cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
698 cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
699 cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
700 cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
701 cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
702 cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
703 cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
704}
705
706static int dma_init(struct fman *fman)
707{
708 struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
709 struct fman_cfg *cfg = fman->cfg;
710 u32 tmp_reg;
711
712
713
714
715 tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
716 DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
717 iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
718
719
720 tmp_reg = 0;
721 tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
722 if (cfg->exceptions & EX_DMA_BUS_ERROR)
723 tmp_reg |= DMA_MODE_BER;
724 if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) |
725 (cfg->exceptions & EX_DMA_READ_ECC) |
726 (cfg->exceptions & EX_DMA_FM_WRITE_ECC))
727 tmp_reg |= DMA_MODE_ECC;
728 if (cfg->dma_axi_dbg_num_of_beats)
729 tmp_reg |= (DMA_MODE_AXI_DBG_MASK &
730 ((cfg->dma_axi_dbg_num_of_beats - 1)
731 << DMA_MODE_AXI_DBG_SHIFT));
732
733 tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) &
734 DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT;
735 tmp_reg |= DMA_MODE_SECURE_PROT;
736 tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
737 tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
738
739 iowrite32be(tmp_reg, &dma_rg->fmdmmr);
740
741
742 tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer <<
743 DMA_THRESH_COMMQ_SHIFT);
744 tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer &
745 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
746 tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer &
747 DMA_THRESH_WRITE_INT_BUF_MASK;
748
749 iowrite32be(tmp_reg, &dma_rg->fmdmtr);
750
751
752 tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer <<
753 DMA_THRESH_COMMQ_SHIFT);
754 tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer &
755 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
756 tmp_reg |= cfg->dma_write_buf_tsh_clr_emer &
757 DMA_THRESH_WRITE_INT_BUF_MASK;
758
759 iowrite32be(tmp_reg, &dma_rg->fmdmhy);
760
761
762 iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
763
764
765 iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
766
767 iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
768
769
770 fman->cam_size =
771 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY);
772 fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size);
773 if (IS_ERR_VALUE(fman->cam_offset)) {
774 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
775 __func__);
776 return -ENOMEM;
777 }
778
779 if (fman->state->rev_info.major == 2) {
780 u32 __iomem *cam_base_addr;
781
782 fman_muram_free_mem(fman->muram, fman->cam_offset,
783 fman->cam_size);
784
785 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128;
786 fman->cam_offset = fman_muram_alloc(fman->muram,
787 fman->cam_size);
788 if (IS_ERR_VALUE(fman->cam_offset)) {
789 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
790 __func__);
791 return -ENOMEM;
792 }
793
794 if (fman->cfg->dma_cam_num_of_entries % 8 ||
795 fman->cfg->dma_cam_num_of_entries > 32) {
796 dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n",
797 __func__);
798 return -EINVAL;
799 }
800
801 cam_base_addr = (u32 __iomem *)
802 fman_muram_offset_to_vbase(fman->muram,
803 fman->cam_offset);
804 iowrite32be(~((1 <<
805 (32 - fman->cfg->dma_cam_num_of_entries)) - 1),
806 cam_base_addr);
807 }
808
809 fman->cfg->cam_base_addr = fman->cam_offset;
810
811 return 0;
812}
813
814static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
815{
816 u32 tmp_reg;
817 int i;
818
819
820
821 tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
822 iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
823
824 tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
825 ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
826 ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
827 ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
828 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
829
830 tmp_reg =
831 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
832 ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) |
833 ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
834 ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
835 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
836
837
838 tmp_reg = 0;
839
840 tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
841 FPM_EV_MASK_SINGLE_ECC);
842
843 if (cfg->exceptions & EX_FPM_STALL_ON_TASKS)
844 tmp_reg |= FPM_EV_MASK_STALL_EN;
845 if (cfg->exceptions & EX_FPM_SINGLE_ECC)
846 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
847 if (cfg->exceptions & EX_FPM_DOUBLE_ECC)
848 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
849 tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
850 tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
851
852 tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
853
854 tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
855 iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
856
857
858 for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++)
859 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
860
861
862
863
864
865
866 tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
867
868 iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
869
870 tmp_reg = 0;
871 if (cfg->exceptions & EX_IRAM_ECC) {
872 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
873 enable_rams_ecc(fpm_rg);
874 }
875 if (cfg->exceptions & EX_MURAM_ECC) {
876 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
877 enable_rams_ecc(fpm_rg);
878 }
879 iowrite32be(tmp_reg, &fpm_rg->fm_rie);
880}
881
882static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg,
883 struct fman_cfg *cfg)
884{
885 u32 tmp_reg;
886
887
888
889
890 tmp_reg = cfg->fifo_base_addr;
891 tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
892
893 tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
894 BMI_CFG1_FIFO_SIZE_SHIFT);
895 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
896
897 tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) <<
898 BMI_CFG2_TASKS_SHIFT;
899
900 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
901
902
903 tmp_reg = 0;
904 iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
905 BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
906 BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
907 BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
908
909 if (cfg->exceptions & EX_BMI_LIST_RAM_ECC)
910 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
911 if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC)
912 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
913 if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC)
914 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
915 if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC)
916 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
917 iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
918}
919
920static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg,
921 struct fman_cfg *cfg)
922{
923 u32 tmp_reg;
924
925
926
927
928
929 iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
930 &qmi_rg->fmqm_eie);
931 tmp_reg = 0;
932 if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
933 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
934 if (cfg->exceptions & EX_QMI_DOUBLE_ECC)
935 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
936
937 iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
938
939 tmp_reg = 0;
940
941 iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
942 if (cfg->exceptions & EX_QMI_SINGLE_ECC)
943 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
944
945 iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
946}
947
948static void hwp_init(struct fman_hwp_regs __iomem *hwp_rg)
949{
950
951 iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac);
952}
953
954static int enable(struct fman *fman, struct fman_cfg *cfg)
955{
956 u32 cfg_reg = 0;
957
958
959
960
961
962
963 cfg_reg = QMI_CFG_EN_COUNTERS;
964
965
966 cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh;
967
968 iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init);
969 iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
970 &fman->qmi_regs->fmqm_gc);
971
972 return 0;
973}
974
975static int set_exception(struct fman *fman,
976 enum fman_exceptions exception, bool enable)
977{
978 u32 tmp;
979
980 switch (exception) {
981 case FMAN_EX_DMA_BUS_ERROR:
982 tmp = ioread32be(&fman->dma_regs->fmdmmr);
983 if (enable)
984 tmp |= DMA_MODE_BER;
985 else
986 tmp &= ~DMA_MODE_BER;
987
988 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
989 break;
990 case FMAN_EX_DMA_READ_ECC:
991 case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
992 case FMAN_EX_DMA_FM_WRITE_ECC:
993 tmp = ioread32be(&fman->dma_regs->fmdmmr);
994 if (enable)
995 tmp |= DMA_MODE_ECC;
996 else
997 tmp &= ~DMA_MODE_ECC;
998 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
999 break;
1000 case FMAN_EX_FPM_STALL_ON_TASKS:
1001 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1002 if (enable)
1003 tmp |= FPM_EV_MASK_STALL_EN;
1004 else
1005 tmp &= ~FPM_EV_MASK_STALL_EN;
1006 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1007 break;
1008 case FMAN_EX_FPM_SINGLE_ECC:
1009 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1010 if (enable)
1011 tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
1012 else
1013 tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
1014 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1015 break;
1016 case FMAN_EX_FPM_DOUBLE_ECC:
1017 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1018 if (enable)
1019 tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
1020 else
1021 tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
1022 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1023 break;
1024 case FMAN_EX_QMI_SINGLE_ECC:
1025 tmp = ioread32be(&fman->qmi_regs->fmqm_ien);
1026 if (enable)
1027 tmp |= QMI_INTR_EN_SINGLE_ECC;
1028 else
1029 tmp &= ~QMI_INTR_EN_SINGLE_ECC;
1030 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien);
1031 break;
1032 case FMAN_EX_QMI_DOUBLE_ECC:
1033 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1034 if (enable)
1035 tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
1036 else
1037 tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
1038 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1039 break;
1040 case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1041 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1042 if (enable)
1043 tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1044 else
1045 tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1046 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1047 break;
1048 case FMAN_EX_BMI_LIST_RAM_ECC:
1049 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1050 if (enable)
1051 tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
1052 else
1053 tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
1054 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1055 break;
1056 case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1057 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1058 if (enable)
1059 tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1060 else
1061 tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1062 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1063 break;
1064 case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1065 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1066 if (enable)
1067 tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1068 else
1069 tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1070 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1071 break;
1072 case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1073 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1074 if (enable)
1075 tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1076 else
1077 tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1078 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1079 break;
1080 case FMAN_EX_IRAM_ECC:
1081 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1082 if (enable) {
1083
1084 enable_rams_ecc(fman->fpm_regs);
1085
1086 tmp |= FPM_IRAM_ECC_ERR_EX_EN;
1087 } else {
1088
1089
1090
1091 disable_rams_ecc(fman->fpm_regs);
1092 tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
1093 }
1094 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1095 break;
1096 case FMAN_EX_MURAM_ECC:
1097 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1098 if (enable) {
1099
1100 enable_rams_ecc(fman->fpm_regs);
1101
1102 tmp |= FPM_MURAM_ECC_ERR_EX_EN;
1103 } else {
1104
1105
1106
1107 disable_rams_ecc(fman->fpm_regs);
1108 tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
1109 }
1110 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115 return 0;
1116}
1117
1118static void resume(struct fman_fpm_regs __iomem *fpm_rg)
1119{
1120 u32 tmp;
1121
1122 tmp = ioread32be(&fpm_rg->fmfp_ee);
1123
1124 tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
1125 FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
1126 tmp |= FPM_EV_MASK_RELEASE_FM;
1127
1128 iowrite32be(tmp, &fpm_rg->fmfp_ee);
1129}
1130
1131static int fill_soc_specific_params(struct fman_state_struct *state)
1132{
1133 u8 minor = state->rev_info.minor;
1134
1135
1136
1137
1138 switch (state->rev_info.major) {
1139 case 3:
1140 state->bmi_max_fifo_size = 160 * 1024;
1141 state->fm_iram_size = 64 * 1024;
1142 state->dma_thresh_max_commq = 31;
1143 state->dma_thresh_max_buf = 127;
1144 state->qmi_max_num_of_tnums = 64;
1145 state->qmi_def_tnums_thresh = 48;
1146 state->bmi_max_num_of_tasks = 128;
1147 state->max_num_of_open_dmas = 32;
1148 state->fm_port_num_of_cg = 256;
1149 state->num_of_rx_ports = 6;
1150 state->total_fifo_size = 136 * 1024;
1151 break;
1152
1153 case 2:
1154 state->bmi_max_fifo_size = 160 * 1024;
1155 state->fm_iram_size = 64 * 1024;
1156 state->dma_thresh_max_commq = 31;
1157 state->dma_thresh_max_buf = 127;
1158 state->qmi_max_num_of_tnums = 64;
1159 state->qmi_def_tnums_thresh = 48;
1160 state->bmi_max_num_of_tasks = 128;
1161 state->max_num_of_open_dmas = 32;
1162 state->fm_port_num_of_cg = 256;
1163 state->num_of_rx_ports = 5;
1164 state->total_fifo_size = 100 * 1024;
1165 break;
1166
1167 case 6:
1168 state->dma_thresh_max_commq = 83;
1169 state->dma_thresh_max_buf = 127;
1170 state->qmi_max_num_of_tnums = 64;
1171 state->qmi_def_tnums_thresh = 32;
1172 state->fm_port_num_of_cg = 256;
1173
1174
1175 if (minor == 1 || minor == 4) {
1176 state->bmi_max_fifo_size = 192 * 1024;
1177 state->bmi_max_num_of_tasks = 64;
1178 state->max_num_of_open_dmas = 32;
1179 state->num_of_rx_ports = 5;
1180 if (minor == 1)
1181 state->fm_iram_size = 32 * 1024;
1182 else
1183 state->fm_iram_size = 64 * 1024;
1184 state->total_fifo_size = 156 * 1024;
1185 }
1186
1187 else if (minor == 0 || minor == 2 || minor == 3) {
1188 state->bmi_max_fifo_size = 384 * 1024;
1189 state->fm_iram_size = 64 * 1024;
1190 state->bmi_max_num_of_tasks = 128;
1191 state->max_num_of_open_dmas = 84;
1192 state->num_of_rx_ports = 8;
1193 state->total_fifo_size = 295 * 1024;
1194 } else {
1195 pr_err("Unsupported FManv3 version\n");
1196 return -EINVAL;
1197 }
1198
1199 break;
1200 default:
1201 pr_err("Unsupported FMan version\n");
1202 return -EINVAL;
1203 }
1204
1205 return 0;
1206}
1207
1208static bool is_init_done(struct fman_cfg *cfg)
1209{
1210
1211 if (!cfg)
1212 return true;
1213
1214 return false;
1215}
1216
1217static void free_init_resources(struct fman *fman)
1218{
1219 if (fman->cam_offset)
1220 fman_muram_free_mem(fman->muram, fman->cam_offset,
1221 fman->cam_size);
1222 if (fman->fifo_offset)
1223 fman_muram_free_mem(fman->muram, fman->fifo_offset,
1224 fman->fifo_size);
1225}
1226
1227static irqreturn_t bmi_err_event(struct fman *fman)
1228{
1229 u32 event, mask, force;
1230 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1231 irqreturn_t ret = IRQ_NONE;
1232
1233 event = ioread32be(&bmi_rg->fmbm_ievr);
1234 mask = ioread32be(&bmi_rg->fmbm_ier);
1235 event &= mask;
1236
1237 force = ioread32be(&bmi_rg->fmbm_ifr);
1238 if (force & event)
1239 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
1240
1241 iowrite32be(event, &bmi_rg->fmbm_ievr);
1242
1243 if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC)
1244 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC);
1245 if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC)
1246 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC);
1247 if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC)
1248 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC);
1249 if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC)
1250 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC);
1251
1252 return ret;
1253}
1254
1255static irqreturn_t qmi_err_event(struct fman *fman)
1256{
1257 u32 event, mask, force;
1258 struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1259 irqreturn_t ret = IRQ_NONE;
1260
1261 event = ioread32be(&qmi_rg->fmqm_eie);
1262 mask = ioread32be(&qmi_rg->fmqm_eien);
1263 event &= mask;
1264
1265
1266 force = ioread32be(&qmi_rg->fmqm_eif);
1267 if (force & event)
1268 iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
1269
1270 iowrite32be(event, &qmi_rg->fmqm_eie);
1271
1272 if (event & QMI_ERR_INTR_EN_DOUBLE_ECC)
1273 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC);
1274 if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF)
1275 ret = fman->exception_cb(fman,
1276 FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID);
1277
1278 return ret;
1279}
1280
1281static irqreturn_t dma_err_event(struct fman *fman)
1282{
1283 u32 status, mask, com_id;
1284 u8 tnum, port_id, relative_port_id;
1285 u16 liodn;
1286 struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
1287 irqreturn_t ret = IRQ_NONE;
1288
1289 status = ioread32be(&dma_rg->fmdmsr);
1290 mask = ioread32be(&dma_rg->fmdmmr);
1291
1292
1293 if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
1294 status &= ~DMA_STATUS_BUS_ERR;
1295
1296
1297 if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
1298 status &= ~(DMA_STATUS_FM_SPDAT_ECC |
1299 DMA_STATUS_READ_ECC |
1300 DMA_STATUS_SYSTEM_WRITE_ECC |
1301 DMA_STATUS_FM_WRITE_ECC);
1302
1303
1304 iowrite32be(status, &dma_rg->fmdmsr);
1305
1306 if (status & DMA_STATUS_BUS_ERR) {
1307 u64 addr;
1308
1309 addr = (u64)ioread32be(&dma_rg->fmdmtal);
1310 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32);
1311
1312 com_id = ioread32be(&dma_rg->fmdmtcid);
1313 port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >>
1314 DMA_TRANSFER_PORTID_SHIFT));
1315 relative_port_id =
1316 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
1317 tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >>
1318 DMA_TRANSFER_TNUM_SHIFT);
1319 liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK);
1320 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum,
1321 liodn);
1322 }
1323 if (status & DMA_STATUS_FM_SPDAT_ECC)
1324 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC);
1325 if (status & DMA_STATUS_READ_ECC)
1326 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC);
1327 if (status & DMA_STATUS_SYSTEM_WRITE_ECC)
1328 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC);
1329 if (status & DMA_STATUS_FM_WRITE_ECC)
1330 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC);
1331
1332 return ret;
1333}
1334
1335static irqreturn_t fpm_err_event(struct fman *fman)
1336{
1337 u32 event;
1338 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1339 irqreturn_t ret = IRQ_NONE;
1340
1341 event = ioread32be(&fpm_rg->fmfp_ee);
1342
1343 iowrite32be(event, &fpm_rg->fmfp_ee);
1344
1345 if ((event & FPM_EV_MASK_DOUBLE_ECC) &&
1346 (event & FPM_EV_MASK_DOUBLE_ECC_EN))
1347 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC);
1348 if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN))
1349 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS);
1350 if ((event & FPM_EV_MASK_SINGLE_ECC) &&
1351 (event & FPM_EV_MASK_SINGLE_ECC_EN))
1352 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC);
1353
1354 return ret;
1355}
1356
1357static irqreturn_t muram_err_intr(struct fman *fman)
1358{
1359 u32 event, mask;
1360 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1361 irqreturn_t ret = IRQ_NONE;
1362
1363 event = ioread32be(&fpm_rg->fm_rcr);
1364 mask = ioread32be(&fpm_rg->fm_rie);
1365
1366
1367 iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
1368
1369 if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC))
1370 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC);
1371
1372 return ret;
1373}
1374
1375static irqreturn_t qmi_event(struct fman *fman)
1376{
1377 u32 event, mask, force;
1378 struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1379 irqreturn_t ret = IRQ_NONE;
1380
1381 event = ioread32be(&qmi_rg->fmqm_ie);
1382 mask = ioread32be(&qmi_rg->fmqm_ien);
1383 event &= mask;
1384
1385 force = ioread32be(&qmi_rg->fmqm_if);
1386 if (force & event)
1387 iowrite32be(force & ~event, &qmi_rg->fmqm_if);
1388
1389 iowrite32be(event, &qmi_rg->fmqm_ie);
1390
1391 if (event & QMI_INTR_EN_SINGLE_ECC)
1392 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC);
1393
1394 return ret;
1395}
1396
1397static void enable_time_stamp(struct fman *fman)
1398{
1399 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1400 u16 fm_clk_freq = fman->state->fm_clk_freq;
1401 u32 tmp, intgr, ts_freq;
1402 u64 frac;
1403
1404 ts_freq = (u32)(1 << fman->state->count1_micro_bit);
1405
1406
1407
1408
1409
1410
1411
1412
1413 intgr = ts_freq / fm_clk_freq;
1414
1415
1416
1417
1418
1419 frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
1420
1421 if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
1422 frac++;
1423
1424 tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac;
1425 iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
1426
1427
1428 iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
1429 fman->state->enabled_time_stamp = true;
1430}
1431
1432static int clear_iram(struct fman *fman)
1433{
1434 struct fman_iram_regs __iomem *iram;
1435 int i, count;
1436
1437 iram = fman->base_addr + IMEM_OFFSET;
1438
1439
1440 iowrite32be(IRAM_IADD_AIE, &iram->iadd);
1441 count = 100;
1442 do {
1443 udelay(1);
1444 } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count);
1445 if (count == 0)
1446 return -EBUSY;
1447
1448 for (i = 0; i < (fman->state->fm_iram_size / 4); i++)
1449 iowrite32be(0xffffffff, &iram->idata);
1450
1451 iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd);
1452 count = 100;
1453 do {
1454 udelay(1);
1455 } while ((ioread32be(&iram->idata) != 0xffffffff) && --count);
1456 if (count == 0)
1457 return -EBUSY;
1458
1459 return 0;
1460}
1461
1462static u32 get_exception_flag(enum fman_exceptions exception)
1463{
1464 u32 bit_mask;
1465
1466 switch (exception) {
1467 case FMAN_EX_DMA_BUS_ERROR:
1468 bit_mask = EX_DMA_BUS_ERROR;
1469 break;
1470 case FMAN_EX_DMA_SINGLE_PORT_ECC:
1471 bit_mask = EX_DMA_SINGLE_PORT_ECC;
1472 break;
1473 case FMAN_EX_DMA_READ_ECC:
1474 bit_mask = EX_DMA_READ_ECC;
1475 break;
1476 case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1477 bit_mask = EX_DMA_SYSTEM_WRITE_ECC;
1478 break;
1479 case FMAN_EX_DMA_FM_WRITE_ECC:
1480 bit_mask = EX_DMA_FM_WRITE_ECC;
1481 break;
1482 case FMAN_EX_FPM_STALL_ON_TASKS:
1483 bit_mask = EX_FPM_STALL_ON_TASKS;
1484 break;
1485 case FMAN_EX_FPM_SINGLE_ECC:
1486 bit_mask = EX_FPM_SINGLE_ECC;
1487 break;
1488 case FMAN_EX_FPM_DOUBLE_ECC:
1489 bit_mask = EX_FPM_DOUBLE_ECC;
1490 break;
1491 case FMAN_EX_QMI_SINGLE_ECC:
1492 bit_mask = EX_QMI_SINGLE_ECC;
1493 break;
1494 case FMAN_EX_QMI_DOUBLE_ECC:
1495 bit_mask = EX_QMI_DOUBLE_ECC;
1496 break;
1497 case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1498 bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID;
1499 break;
1500 case FMAN_EX_BMI_LIST_RAM_ECC:
1501 bit_mask = EX_BMI_LIST_RAM_ECC;
1502 break;
1503 case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1504 bit_mask = EX_BMI_STORAGE_PROFILE_ECC;
1505 break;
1506 case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1507 bit_mask = EX_BMI_STATISTICS_RAM_ECC;
1508 break;
1509 case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1510 bit_mask = EX_BMI_DISPATCH_RAM_ECC;
1511 break;
1512 case FMAN_EX_MURAM_ECC:
1513 bit_mask = EX_MURAM_ECC;
1514 break;
1515 default:
1516 bit_mask = 0;
1517 break;
1518 }
1519
1520 return bit_mask;
1521}
1522
1523static int get_module_event(enum fman_event_modules module, u8 mod_id,
1524 enum fman_intr_type intr_type)
1525{
1526 int event;
1527
1528 switch (module) {
1529 case FMAN_MOD_MAC:
1530 if (intr_type == FMAN_INTR_TYPE_ERR)
1531 event = FMAN_EV_ERR_MAC0 + mod_id;
1532 else
1533 event = FMAN_EV_MAC0 + mod_id;
1534 break;
1535 case FMAN_MOD_FMAN_CTRL:
1536 if (intr_type == FMAN_INTR_TYPE_ERR)
1537 event = FMAN_EV_CNT;
1538 else
1539 event = (FMAN_EV_FMAN_CTRL_0 + mod_id);
1540 break;
1541 case FMAN_MOD_DUMMY_LAST:
1542 event = FMAN_EV_CNT;
1543 break;
1544 default:
1545 event = FMAN_EV_CNT;
1546 break;
1547 }
1548
1549 return event;
1550}
1551
1552static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo,
1553 u32 *extra_size_of_fifo)
1554{
1555 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1556 u32 fifo = *size_of_fifo;
1557 u32 extra_fifo = *extra_size_of_fifo;
1558 u32 tmp;
1559
1560
1561
1562
1563
1564 if (extra_fifo && !fman->state->extra_fifo_pool_size)
1565 fman->state->extra_fifo_pool_size =
1566 fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS;
1567
1568 fman->state->extra_fifo_pool_size =
1569 max(fman->state->extra_fifo_pool_size, extra_fifo);
1570
1571
1572 if ((fman->state->accumulated_fifo_size + fifo) >
1573 (fman->state->total_fifo_size -
1574 fman->state->extra_fifo_pool_size)) {
1575 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n",
1576 __func__);
1577 return -EAGAIN;
1578 }
1579
1580
1581 tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) |
1582 ((extra_fifo / FMAN_BMI_FIFO_UNITS) <<
1583 BMI_EXTRA_FIFO_SIZE_SHIFT);
1584 iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
1585
1586
1587 fman->state->accumulated_fifo_size += fifo;
1588
1589 return 0;
1590}
1591
1592static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks,
1593 u8 *num_of_extra_tasks)
1594{
1595 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1596 u8 tasks = *num_of_tasks;
1597 u8 extra_tasks = *num_of_extra_tasks;
1598 u32 tmp;
1599
1600 if (extra_tasks)
1601 fman->state->extra_tasks_pool_size =
1602 max(fman->state->extra_tasks_pool_size, extra_tasks);
1603
1604
1605 if ((fman->state->accumulated_num_of_tasks + tasks) >
1606 (fman->state->total_num_of_tasks -
1607 fman->state->extra_tasks_pool_size)) {
1608 dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n",
1609 __func__, fman->state->fm_id);
1610 return -EAGAIN;
1611 }
1612
1613 fman->state->accumulated_num_of_tasks += tasks;
1614
1615
1616 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1617 ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
1618 tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
1619 (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
1620 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1621
1622 return 0;
1623}
1624
1625static int set_num_of_open_dmas(struct fman *fman, u8 port_id,
1626 u8 *num_of_open_dmas,
1627 u8 *num_of_extra_open_dmas)
1628{
1629 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1630 u8 open_dmas = *num_of_open_dmas;
1631 u8 extra_open_dmas = *num_of_extra_open_dmas;
1632 u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0;
1633 u32 tmp;
1634
1635 if (!open_dmas) {
1636
1637
1638
1639 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1640 current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
1641 BMI_EXTRA_NUM_OF_DMAS_SHIFT);
1642
1643 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1644 current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
1645 BMI_NUM_OF_DMAS_SHIFT) + 1);
1646
1647
1648
1649
1650
1651 fman->state->extra_open_dmas_pool_size =
1652 (u8)max(fman->state->extra_open_dmas_pool_size,
1653 current_extra_val);
1654 fman->state->accumulated_num_of_open_dmas += current_val;
1655 *num_of_open_dmas = current_val;
1656 *num_of_extra_open_dmas = current_extra_val;
1657 return 0;
1658 }
1659
1660 if (extra_open_dmas > current_extra_val)
1661 fman->state->extra_open_dmas_pool_size =
1662 (u8)max(fman->state->extra_open_dmas_pool_size,
1663 extra_open_dmas);
1664
1665 if ((fman->state->rev_info.major < 6) &&
1666 (fman->state->accumulated_num_of_open_dmas - current_val +
1667 open_dmas > fman->state->max_num_of_open_dmas)) {
1668 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n",
1669 __func__, fman->state->fm_id);
1670 return -EAGAIN;
1671 } else if ((fman->state->rev_info.major >= 6) &&
1672 !((fman->state->rev_info.major == 6) &&
1673 (fman->state->rev_info.minor == 0)) &&
1674 (fman->state->accumulated_num_of_open_dmas -
1675 current_val + open_dmas >
1676 fman->state->dma_thresh_max_commq + 1)) {
1677 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n",
1678 __func__, fman->state->fm_id,
1679 fman->state->dma_thresh_max_commq + 1);
1680 return -EAGAIN;
1681 }
1682
1683 WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val);
1684
1685 fman->state->accumulated_num_of_open_dmas -= current_val;
1686 fman->state->accumulated_num_of_open_dmas += open_dmas;
1687
1688 if (fman->state->rev_info.major < 6)
1689 total_num_dmas =
1690 (u8)(fman->state->accumulated_num_of_open_dmas +
1691 fman->state->extra_open_dmas_pool_size);
1692
1693
1694 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1695 ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
1696 tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
1697 (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT));
1698 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1699
1700
1701
1702
1703 if (total_num_dmas) {
1704 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1705 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
1706 iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
1707 }
1708
1709 return 0;
1710}
1711
1712static int fman_config(struct fman *fman)
1713{
1714 void __iomem *base_addr;
1715 int err;
1716
1717 base_addr = fman->dts_params.base_addr;
1718
1719 fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL);
1720 if (!fman->state)
1721 goto err_fm_state;
1722
1723
1724 fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL);
1725 if (!fman->cfg)
1726 goto err_fm_drv;
1727
1728
1729 fman->muram =
1730 fman_muram_init(fman->dts_params.muram_res.start,
1731 resource_size(&fman->dts_params.muram_res));
1732 if (!fman->muram)
1733 goto err_fm_soc_specific;
1734
1735
1736 fman->state->fm_id = fman->dts_params.id;
1737 fman->state->fm_clk_freq = fman->dts_params.clk_freq;
1738 fman->state->qman_channel_base = fman->dts_params.qman_channel_base;
1739 fman->state->num_of_qman_channels =
1740 fman->dts_params.num_of_qman_channels;
1741 fman->state->res = fman->dts_params.res;
1742 fman->exception_cb = fman_exceptions;
1743 fman->bus_error_cb = fman_bus_error;
1744 fman->fpm_regs = base_addr + FPM_OFFSET;
1745 fman->bmi_regs = base_addr + BMI_OFFSET;
1746 fman->qmi_regs = base_addr + QMI_OFFSET;
1747 fman->dma_regs = base_addr + DMA_OFFSET;
1748 fman->hwp_regs = base_addr + HWP_OFFSET;
1749 fman->kg_regs = base_addr + KG_OFFSET;
1750 fman->base_addr = base_addr;
1751
1752 spin_lock_init(&fman->spinlock);
1753 fman_defconfig(fman->cfg);
1754
1755 fman->state->extra_fifo_pool_size = 0;
1756 fman->state->exceptions = (EX_DMA_BUS_ERROR |
1757 EX_DMA_READ_ECC |
1758 EX_DMA_SYSTEM_WRITE_ECC |
1759 EX_DMA_FM_WRITE_ECC |
1760 EX_FPM_STALL_ON_TASKS |
1761 EX_FPM_SINGLE_ECC |
1762 EX_FPM_DOUBLE_ECC |
1763 EX_QMI_DEQ_FROM_UNKNOWN_PORTID |
1764 EX_BMI_LIST_RAM_ECC |
1765 EX_BMI_STORAGE_PROFILE_ECC |
1766 EX_BMI_STATISTICS_RAM_ECC |
1767 EX_MURAM_ECC |
1768 EX_BMI_DISPATCH_RAM_ECC |
1769 EX_QMI_DOUBLE_ECC |
1770 EX_QMI_SINGLE_ECC);
1771
1772
1773 fman_get_revision(fman, &fman->state->rev_info);
1774
1775 err = fill_soc_specific_params(fman->state);
1776 if (err)
1777 goto err_fm_soc_specific;
1778
1779
1780 if (fman->state->rev_info.major >= 6)
1781 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID;
1782
1783 fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh;
1784
1785 fman->state->total_num_of_tasks =
1786 (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major,
1787 fman->state->rev_info.minor,
1788 fman->state->bmi_max_num_of_tasks);
1789
1790 if (fman->state->rev_info.major < 6) {
1791 fman->cfg->dma_comm_qtsh_clr_emer =
1792 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major,
1793 fman->state->dma_thresh_max_commq);
1794
1795 fman->cfg->dma_comm_qtsh_asrt_emer =
1796 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major,
1797 fman->state->dma_thresh_max_commq);
1798
1799 fman->cfg->dma_cam_num_of_entries =
1800 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major);
1801
1802 fman->cfg->dma_read_buf_tsh_clr_emer =
1803 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1804
1805 fman->cfg->dma_read_buf_tsh_asrt_emer =
1806 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1807
1808 fman->cfg->dma_write_buf_tsh_clr_emer =
1809 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1810
1811 fman->cfg->dma_write_buf_tsh_asrt_emer =
1812 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1813
1814 fman->cfg->dma_axi_dbg_num_of_beats =
1815 DFLT_AXI_DBG_NUM_OF_BEATS;
1816 }
1817
1818 return 0;
1819
1820err_fm_soc_specific:
1821 kfree(fman->cfg);
1822err_fm_drv:
1823 kfree(fman->state);
1824err_fm_state:
1825 kfree(fman);
1826 return -EINVAL;
1827}
1828
1829static int fman_reset(struct fman *fman)
1830{
1831 u32 count;
1832 int err = 0;
1833
1834 if (fman->state->rev_info.major < 6) {
1835 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1836
1837 count = 100;
1838 do {
1839 udelay(1);
1840 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1841 FPM_RSTC_FM_RESET) && --count);
1842 if (count == 0)
1843 err = -EBUSY;
1844
1845 goto _return;
1846 } else {
1847#ifdef CONFIG_PPC
1848 struct device_node *guts_node;
1849 struct ccsr_guts __iomem *guts_regs;
1850 u32 devdisr2, reg;
1851
1852
1853 guts_node =
1854 of_find_compatible_node(NULL, NULL,
1855 "fsl,qoriq-device-config-2.0");
1856 if (!guts_node) {
1857 dev_err(fman->dev, "%s: Couldn't find guts node\n",
1858 __func__);
1859 goto guts_node;
1860 }
1861
1862 guts_regs = of_iomap(guts_node, 0);
1863 if (!guts_regs) {
1864 dev_err(fman->dev, "%s: Couldn't map %pOF regs\n",
1865 __func__, guts_node);
1866 goto guts_regs;
1867 }
1868#define FMAN1_ALL_MACS_MASK 0xFCC00000
1869#define FMAN2_ALL_MACS_MASK 0x000FCC00
1870
1871 devdisr2 = ioread32be(&guts_regs->devdisr2);
1872 if (fman->dts_params.id == 0)
1873 reg = devdisr2 & ~FMAN1_ALL_MACS_MASK;
1874 else
1875 reg = devdisr2 & ~FMAN2_ALL_MACS_MASK;
1876
1877
1878 iowrite32be(reg, &guts_regs->devdisr2);
1879#endif
1880
1881
1882 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1883
1884
1885 count = 100;
1886 do {
1887 udelay(1);
1888 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1889 FPM_RSTC_FM_RESET) && --count);
1890 if (count == 0) {
1891#ifdef CONFIG_PPC
1892 iounmap(guts_regs);
1893 of_node_put(guts_node);
1894#endif
1895 err = -EBUSY;
1896 goto _return;
1897 }
1898#ifdef CONFIG_PPC
1899
1900
1901 iowrite32be(devdisr2, &guts_regs->devdisr2);
1902
1903 iounmap(guts_regs);
1904 of_node_put(guts_node);
1905#endif
1906
1907 goto _return;
1908
1909#ifdef CONFIG_PPC
1910guts_regs:
1911 of_node_put(guts_node);
1912guts_node:
1913 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n",
1914 __func__);
1915#endif
1916 }
1917_return:
1918 return err;
1919}
1920
1921static int fman_init(struct fman *fman)
1922{
1923 struct fman_cfg *cfg = NULL;
1924 int err = 0, i, count;
1925
1926 if (is_init_done(fman->cfg))
1927 return -EINVAL;
1928
1929 fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT;
1930
1931 cfg = fman->cfg;
1932
1933
1934 if (fman->state->rev_info.major < 6)
1935 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC;
1936
1937 if (fman->state->rev_info.major >= 6)
1938 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC;
1939
1940
1941 memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0,
1942 fman->state->fm_port_num_of_cg);
1943
1944
1945
1946
1947 for (i = 1; i < FMAN_LIODN_TBL; i++) {
1948 u32 liodn_base;
1949
1950 fman->liodn_offset[i] =
1951 ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
1952 if (!IS_ENABLED(CONFIG_FSL_PAMU))
1953 continue;
1954 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
1955 if (i % 2) {
1956
1957 liodn_base &= DMA_LIODN_BASE_MASK;
1958 } else {
1959
1960 liodn_base >>= DMA_LIODN_SHIFT;
1961 liodn_base &= DMA_LIODN_BASE_MASK;
1962 }
1963 fman->liodn_base[i] = liodn_base;
1964 }
1965
1966 err = fman_reset(fman);
1967 if (err)
1968 return err;
1969
1970 if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) {
1971 resume(fman->fpm_regs);
1972
1973 count = 100;
1974 do {
1975 udelay(1);
1976 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) &
1977 QMI_GS_HALT_NOT_BUSY) && --count);
1978 if (count == 0)
1979 dev_warn(fman->dev, "%s: QMI is in halt not busy state\n",
1980 __func__);
1981 }
1982
1983 if (clear_iram(fman) != 0)
1984 return -EINVAL;
1985
1986 cfg->exceptions = fman->state->exceptions;
1987
1988
1989
1990 err = dma_init(fman);
1991 if (err != 0) {
1992 free_init_resources(fman);
1993 return err;
1994 }
1995
1996
1997 fpm_init(fman->fpm_regs, fman->cfg);
1998
1999
2000
2001 fman->fifo_offset = fman_muram_alloc(fman->muram,
2002 fman->state->total_fifo_size);
2003 if (IS_ERR_VALUE(fman->fifo_offset)) {
2004 free_init_resources(fman);
2005 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n",
2006 __func__);
2007 return -ENOMEM;
2008 }
2009
2010 cfg->fifo_base_addr = fman->fifo_offset;
2011 cfg->total_fifo_size = fman->state->total_fifo_size;
2012 cfg->total_num_of_tasks = fman->state->total_num_of_tasks;
2013 cfg->clk_freq = fman->state->fm_clk_freq;
2014
2015
2016 bmi_init(fman->bmi_regs, fman->cfg);
2017
2018
2019 qmi_init(fman->qmi_regs, fman->cfg);
2020
2021
2022 hwp_init(fman->hwp_regs);
2023
2024
2025 fman->keygen = keygen_init(fman->kg_regs);
2026 if (!fman->keygen)
2027 return -EINVAL;
2028
2029 err = enable(fman, cfg);
2030 if (err != 0)
2031 return err;
2032
2033 enable_time_stamp(fman);
2034
2035 kfree(fman->cfg);
2036 fman->cfg = NULL;
2037
2038 return 0;
2039}
2040
2041static int fman_set_exception(struct fman *fman,
2042 enum fman_exceptions exception, bool enable)
2043{
2044 u32 bit_mask = 0;
2045
2046 if (!is_init_done(fman->cfg))
2047 return -EINVAL;
2048
2049 bit_mask = get_exception_flag(exception);
2050 if (bit_mask) {
2051 if (enable)
2052 fman->state->exceptions |= bit_mask;
2053 else
2054 fman->state->exceptions &= ~bit_mask;
2055 } else {
2056 dev_err(fman->dev, "%s: Undefined exception (%d)\n",
2057 __func__, exception);
2058 return -EINVAL;
2059 }
2060
2061 return set_exception(fman, exception, enable);
2062}
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077void fman_register_intr(struct fman *fman, enum fman_event_modules module,
2078 u8 mod_id, enum fman_intr_type intr_type,
2079 void (*isr_cb)(void *src_arg), void *src_arg)
2080{
2081 int event = 0;
2082
2083 event = get_module_event(module, mod_id, intr_type);
2084 WARN_ON(event >= FMAN_EV_CNT);
2085
2086
2087 fman->intr_mng[event].isr_cb = isr_cb;
2088 fman->intr_mng[event].src_handle = src_arg;
2089}
2090EXPORT_SYMBOL(fman_register_intr);
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103void fman_unregister_intr(struct fman *fman, enum fman_event_modules module,
2104 u8 mod_id, enum fman_intr_type intr_type)
2105{
2106 int event = 0;
2107
2108 event = get_module_event(module, mod_id, intr_type);
2109 WARN_ON(event >= FMAN_EV_CNT);
2110
2111 fman->intr_mng[event].isr_cb = NULL;
2112 fman->intr_mng[event].src_handle = NULL;
2113}
2114EXPORT_SYMBOL(fman_unregister_intr);
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125int fman_set_port_params(struct fman *fman,
2126 struct fman_port_init_params *port_params)
2127{
2128 int err;
2129 unsigned long flags;
2130 u8 port_id = port_params->port_id, mac_id;
2131
2132 spin_lock_irqsave(&fman->spinlock, flags);
2133
2134 err = set_num_of_tasks(fman, port_params->port_id,
2135 &port_params->num_of_tasks,
2136 &port_params->num_of_extra_tasks);
2137 if (err)
2138 goto return_err;
2139
2140
2141 if (port_params->port_type != FMAN_PORT_TYPE_RX) {
2142 u32 enq_th, deq_th, reg;
2143
2144
2145 fman->state->accumulated_num_of_deq_tnums +=
2146 port_params->deq_pipeline_depth;
2147 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) &
2148 QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT;
2149
2150
2151
2152 if (enq_th >= (fman->state->qmi_max_num_of_tnums -
2153 fman->state->accumulated_num_of_deq_tnums)) {
2154 enq_th =
2155 fman->state->qmi_max_num_of_tnums -
2156 fman->state->accumulated_num_of_deq_tnums - 1;
2157
2158 reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2159 reg &= ~QMI_CFG_ENQ_MASK;
2160 reg |= (enq_th << QMI_CFG_ENQ_SHIFT);
2161 iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2162 }
2163
2164 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) &
2165 QMI_CFG_DEQ_MASK;
2166
2167
2168
2169
2170
2171 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) &&
2172 (deq_th < fman->state->qmi_max_num_of_tnums - 1)) {
2173 deq_th = fman->state->accumulated_num_of_deq_tnums + 1;
2174 reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2175 reg &= ~QMI_CFG_DEQ_MASK;
2176 reg |= deq_th;
2177 iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2178 }
2179 }
2180
2181 err = set_size_of_fifo(fman, port_params->port_id,
2182 &port_params->size_of_fifo,
2183 &port_params->extra_size_of_fifo);
2184 if (err)
2185 goto return_err;
2186
2187 err = set_num_of_open_dmas(fman, port_params->port_id,
2188 &port_params->num_of_open_dmas,
2189 &port_params->num_of_extra_open_dmas);
2190 if (err)
2191 goto return_err;
2192
2193 set_port_liodn(fman, port_id, fman->liodn_base[port_id],
2194 fman->liodn_offset[port_id]);
2195
2196 if (fman->state->rev_info.major < 6)
2197 set_port_order_restoration(fman->fpm_regs, port_id);
2198
2199 mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
2200
2201 if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) {
2202 fman->state->port_mfl[mac_id] = port_params->max_frame_length;
2203 } else {
2204 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n",
2205 __func__, port_id, mac_id);
2206 err = -EINVAL;
2207 goto return_err;
2208 }
2209
2210 spin_unlock_irqrestore(&fman->spinlock, flags);
2211
2212 return 0;
2213
2214return_err:
2215 spin_unlock_irqrestore(&fman->spinlock, flags);
2216 return err;
2217}
2218EXPORT_SYMBOL(fman_set_port_params);
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229int fman_reset_mac(struct fman *fman, u8 mac_id)
2230{
2231 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
2232 u32 msk, timeout = 100;
2233
2234 if (fman->state->rev_info.major >= 6) {
2235 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n",
2236 __func__);
2237 return -EINVAL;
2238 }
2239
2240
2241 switch (mac_id) {
2242 case 0:
2243 msk = FPM_RSTC_MAC0_RESET;
2244 break;
2245 case 1:
2246 msk = FPM_RSTC_MAC1_RESET;
2247 break;
2248 case 2:
2249 msk = FPM_RSTC_MAC2_RESET;
2250 break;
2251 case 3:
2252 msk = FPM_RSTC_MAC3_RESET;
2253 break;
2254 case 4:
2255 msk = FPM_RSTC_MAC4_RESET;
2256 break;
2257 case 5:
2258 msk = FPM_RSTC_MAC5_RESET;
2259 break;
2260 case 6:
2261 msk = FPM_RSTC_MAC6_RESET;
2262 break;
2263 case 7:
2264 msk = FPM_RSTC_MAC7_RESET;
2265 break;
2266 case 8:
2267 msk = FPM_RSTC_MAC8_RESET;
2268 break;
2269 case 9:
2270 msk = FPM_RSTC_MAC9_RESET;
2271 break;
2272 default:
2273 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n",
2274 __func__, mac_id);
2275 return -EINVAL;
2276 }
2277
2278
2279 iowrite32be(msk, &fpm_rg->fm_rstc);
2280 while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
2281 udelay(10);
2282
2283 if (!timeout)
2284 return -EIO;
2285
2286 return 0;
2287}
2288EXPORT_SYMBOL(fman_reset_mac);
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl)
2301{
2302
2303
2304
2305 if ((!fman->state->port_mfl[mac_id]) ||
2306 (mfl <= fman->state->port_mfl[mac_id])) {
2307 fman->state->mac_mfl[mac_id] = mfl;
2308 } else {
2309 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n",
2310 __func__);
2311 return -EINVAL;
2312 }
2313 return 0;
2314}
2315EXPORT_SYMBOL(fman_set_mac_max_frame);
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325u16 fman_get_clock_freq(struct fman *fman)
2326{
2327 return fman->state->fm_clk_freq;
2328}
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338u32 fman_get_bmi_max_fifo_size(struct fman *fman)
2339{
2340 return fman->state->bmi_max_fifo_size;
2341}
2342EXPORT_SYMBOL(fman_get_bmi_max_fifo_size);
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info)
2356{
2357 u32 tmp;
2358
2359 tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1);
2360 rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >>
2361 FPM_REV1_MAJOR_SHIFT);
2362 rev_info->minor = tmp & FPM_REV1_MINOR_MASK;
2363}
2364EXPORT_SYMBOL(fman_get_revision);
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id)
2376{
2377 int i;
2378
2379 if (fman->state->rev_info.major >= 6) {
2380 static const u32 port_ids[] = {
2381 0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b,
2382 0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2383 };
2384
2385 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2386 if (port_ids[i] == port_id)
2387 break;
2388 }
2389 } else {
2390 static const u32 port_ids[] = {
2391 0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1,
2392 0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2393 };
2394
2395 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2396 if (port_ids[i] == port_id)
2397 break;
2398 }
2399 }
2400
2401 if (i == fman->state->num_of_qman_channels)
2402 return 0;
2403
2404 return fman->state->qman_channel_base + i;
2405}
2406EXPORT_SYMBOL(fman_get_qman_channel_id);
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416struct resource *fman_get_mem_region(struct fman *fman)
2417{
2418 return fman->state->res;
2419}
2420EXPORT_SYMBOL(fman_get_mem_region);
2421
2422
2423
2424#define FSL_FM_RX_EXTRA_HEADROOM 64
2425#define FSL_FM_RX_EXTRA_HEADROOM_MIN 16
2426#define FSL_FM_RX_EXTRA_HEADROOM_MAX 384
2427
2428
2429#define FSL_FM_MAX_FRAME_SIZE 1522
2430#define FSL_FM_MAX_POSSIBLE_FRAME_SIZE 9600
2431#define FSL_FM_MIN_POSSIBLE_FRAME_SIZE 64
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2443module_param(fsl_fm_rx_extra_headroom, int, 0);
2444MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers");
2445
2446
2447
2448
2449
2450
2451
2452static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2453module_param(fsl_fm_max_frm, int, 0);
2454MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces");
2455
2456
2457
2458
2459
2460
2461u16 fman_get_max_frm(void)
2462{
2463 static bool fm_check_mfl;
2464
2465 if (!fm_check_mfl) {
2466 if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE ||
2467 fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) {
2468 pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2469 fsl_fm_max_frm,
2470 FSL_FM_MIN_POSSIBLE_FRAME_SIZE,
2471 FSL_FM_MAX_POSSIBLE_FRAME_SIZE,
2472 FSL_FM_MAX_FRAME_SIZE);
2473 fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2474 }
2475 fm_check_mfl = true;
2476 }
2477
2478 return fsl_fm_max_frm;
2479}
2480EXPORT_SYMBOL(fman_get_max_frm);
2481
2482
2483
2484
2485
2486
2487int fman_get_rx_extra_headroom(void)
2488{
2489 static bool fm_check_rx_extra_headroom;
2490
2491 if (!fm_check_rx_extra_headroom) {
2492 if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
2493 fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) {
2494 pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2495 fsl_fm_rx_extra_headroom,
2496 FSL_FM_RX_EXTRA_HEADROOM_MIN,
2497 FSL_FM_RX_EXTRA_HEADROOM_MAX,
2498 FSL_FM_RX_EXTRA_HEADROOM);
2499 fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2500 }
2501
2502 fm_check_rx_extra_headroom = true;
2503 fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16);
2504 }
2505
2506 return fsl_fm_rx_extra_headroom;
2507}
2508EXPORT_SYMBOL(fman_get_rx_extra_headroom);
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520struct fman *fman_bind(struct device *fm_dev)
2521{
2522 return (struct fman *)(dev_get_drvdata(get_device(fm_dev)));
2523}
2524EXPORT_SYMBOL(fman_bind);
2525
2526#ifdef CONFIG_DPAA_ERRATUM_A050385
2527bool fman_has_errata_a050385(void)
2528{
2529 return fman_has_err_a050385;
2530}
2531EXPORT_SYMBOL(fman_has_errata_a050385);
2532#endif
2533
2534static irqreturn_t fman_err_irq(int irq, void *handle)
2535{
2536 struct fman *fman = (struct fman *)handle;
2537 u32 pending;
2538 struct fman_fpm_regs __iomem *fpm_rg;
2539 irqreturn_t single_ret, ret = IRQ_NONE;
2540
2541 if (!is_init_done(fman->cfg))
2542 return IRQ_NONE;
2543
2544 fpm_rg = fman->fpm_regs;
2545
2546
2547 pending = ioread32be(&fpm_rg->fm_epi);
2548 if (!pending)
2549 return IRQ_NONE;
2550
2551 if (pending & ERR_INTR_EN_BMI) {
2552 single_ret = bmi_err_event(fman);
2553 if (single_ret == IRQ_HANDLED)
2554 ret = IRQ_HANDLED;
2555 }
2556 if (pending & ERR_INTR_EN_QMI) {
2557 single_ret = qmi_err_event(fman);
2558 if (single_ret == IRQ_HANDLED)
2559 ret = IRQ_HANDLED;
2560 }
2561 if (pending & ERR_INTR_EN_FPM) {
2562 single_ret = fpm_err_event(fman);
2563 if (single_ret == IRQ_HANDLED)
2564 ret = IRQ_HANDLED;
2565 }
2566 if (pending & ERR_INTR_EN_DMA) {
2567 single_ret = dma_err_event(fman);
2568 if (single_ret == IRQ_HANDLED)
2569 ret = IRQ_HANDLED;
2570 }
2571 if (pending & ERR_INTR_EN_MURAM) {
2572 single_ret = muram_err_intr(fman);
2573 if (single_ret == IRQ_HANDLED)
2574 ret = IRQ_HANDLED;
2575 }
2576
2577
2578 if (pending & ERR_INTR_EN_MAC0) {
2579 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0);
2580 if (single_ret == IRQ_HANDLED)
2581 ret = IRQ_HANDLED;
2582 }
2583 if (pending & ERR_INTR_EN_MAC1) {
2584 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1);
2585 if (single_ret == IRQ_HANDLED)
2586 ret = IRQ_HANDLED;
2587 }
2588 if (pending & ERR_INTR_EN_MAC2) {
2589 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2);
2590 if (single_ret == IRQ_HANDLED)
2591 ret = IRQ_HANDLED;
2592 }
2593 if (pending & ERR_INTR_EN_MAC3) {
2594 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3);
2595 if (single_ret == IRQ_HANDLED)
2596 ret = IRQ_HANDLED;
2597 }
2598 if (pending & ERR_INTR_EN_MAC4) {
2599 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4);
2600 if (single_ret == IRQ_HANDLED)
2601 ret = IRQ_HANDLED;
2602 }
2603 if (pending & ERR_INTR_EN_MAC5) {
2604 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5);
2605 if (single_ret == IRQ_HANDLED)
2606 ret = IRQ_HANDLED;
2607 }
2608 if (pending & ERR_INTR_EN_MAC6) {
2609 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6);
2610 if (single_ret == IRQ_HANDLED)
2611 ret = IRQ_HANDLED;
2612 }
2613 if (pending & ERR_INTR_EN_MAC7) {
2614 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7);
2615 if (single_ret == IRQ_HANDLED)
2616 ret = IRQ_HANDLED;
2617 }
2618 if (pending & ERR_INTR_EN_MAC8) {
2619 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8);
2620 if (single_ret == IRQ_HANDLED)
2621 ret = IRQ_HANDLED;
2622 }
2623 if (pending & ERR_INTR_EN_MAC9) {
2624 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9);
2625 if (single_ret == IRQ_HANDLED)
2626 ret = IRQ_HANDLED;
2627 }
2628
2629 return ret;
2630}
2631
2632static irqreturn_t fman_irq(int irq, void *handle)
2633{
2634 struct fman *fman = (struct fman *)handle;
2635 u32 pending;
2636 struct fman_fpm_regs __iomem *fpm_rg;
2637 irqreturn_t single_ret, ret = IRQ_NONE;
2638
2639 if (!is_init_done(fman->cfg))
2640 return IRQ_NONE;
2641
2642 fpm_rg = fman->fpm_regs;
2643
2644
2645 pending = ioread32be(&fpm_rg->fm_npi);
2646 if (!pending)
2647 return IRQ_NONE;
2648
2649 if (pending & INTR_EN_QMI) {
2650 single_ret = qmi_event(fman);
2651 if (single_ret == IRQ_HANDLED)
2652 ret = IRQ_HANDLED;
2653 }
2654
2655
2656 if (pending & INTR_EN_MAC0) {
2657 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0);
2658 if (single_ret == IRQ_HANDLED)
2659 ret = IRQ_HANDLED;
2660 }
2661 if (pending & INTR_EN_MAC1) {
2662 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1);
2663 if (single_ret == IRQ_HANDLED)
2664 ret = IRQ_HANDLED;
2665 }
2666 if (pending & INTR_EN_MAC2) {
2667 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2);
2668 if (single_ret == IRQ_HANDLED)
2669 ret = IRQ_HANDLED;
2670 }
2671 if (pending & INTR_EN_MAC3) {
2672 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3);
2673 if (single_ret == IRQ_HANDLED)
2674 ret = IRQ_HANDLED;
2675 }
2676 if (pending & INTR_EN_MAC4) {
2677 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4);
2678 if (single_ret == IRQ_HANDLED)
2679 ret = IRQ_HANDLED;
2680 }
2681 if (pending & INTR_EN_MAC5) {
2682 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5);
2683 if (single_ret == IRQ_HANDLED)
2684 ret = IRQ_HANDLED;
2685 }
2686 if (pending & INTR_EN_MAC6) {
2687 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6);
2688 if (single_ret == IRQ_HANDLED)
2689 ret = IRQ_HANDLED;
2690 }
2691 if (pending & INTR_EN_MAC7) {
2692 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7);
2693 if (single_ret == IRQ_HANDLED)
2694 ret = IRQ_HANDLED;
2695 }
2696 if (pending & INTR_EN_MAC8) {
2697 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8);
2698 if (single_ret == IRQ_HANDLED)
2699 ret = IRQ_HANDLED;
2700 }
2701 if (pending & INTR_EN_MAC9) {
2702 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9);
2703 if (single_ret == IRQ_HANDLED)
2704 ret = IRQ_HANDLED;
2705 }
2706
2707 return ret;
2708}
2709
2710static const struct of_device_id fman_muram_match[] = {
2711 {
2712 .compatible = "fsl,fman-muram"},
2713 {}
2714};
2715MODULE_DEVICE_TABLE(of, fman_muram_match);
2716
2717static struct fman *read_dts_node(struct platform_device *of_dev)
2718{
2719 struct fman *fman;
2720 struct device_node *fm_node, *muram_node;
2721 struct resource *res;
2722 u32 val, range[2];
2723 int err, irq;
2724 struct clk *clk;
2725 u32 clk_rate;
2726 phys_addr_t phys_base_addr;
2727 resource_size_t mem_size;
2728
2729 fman = kzalloc(sizeof(*fman), GFP_KERNEL);
2730 if (!fman)
2731 return NULL;
2732
2733 fm_node = of_node_get(of_dev->dev.of_node);
2734
2735 err = of_property_read_u32(fm_node, "cell-index", &val);
2736 if (err) {
2737 dev_err(&of_dev->dev, "%s: failed to read cell-index for %pOF\n",
2738 __func__, fm_node);
2739 goto fman_node_put;
2740 }
2741 fman->dts_params.id = (u8)val;
2742
2743
2744 res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0);
2745 if (!res) {
2746 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n",
2747 __func__);
2748 goto fman_node_put;
2749 }
2750 irq = res->start;
2751
2752
2753 res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1);
2754 if (!res) {
2755 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n",
2756 __func__);
2757 goto fman_node_put;
2758 }
2759 fman->dts_params.err_irq = res->start;
2760
2761
2762 res = platform_get_resource(of_dev, IORESOURCE_MEM, 0);
2763 if (!res) {
2764 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n",
2765 __func__);
2766 goto fman_node_put;
2767 }
2768
2769 phys_base_addr = res->start;
2770 mem_size = resource_size(res);
2771
2772 clk = of_clk_get(fm_node, 0);
2773 if (IS_ERR(clk)) {
2774 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n",
2775 __func__, fman->dts_params.id);
2776 goto fman_node_put;
2777 }
2778
2779 clk_rate = clk_get_rate(clk);
2780 if (!clk_rate) {
2781 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n",
2782 __func__, fman->dts_params.id);
2783 goto fman_node_put;
2784 }
2785
2786 fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000);
2787
2788 err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range",
2789 &range[0], 2);
2790 if (err) {
2791 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %pOF\n",
2792 __func__, fm_node);
2793 goto fman_node_put;
2794 }
2795 fman->dts_params.qman_channel_base = range[0];
2796 fman->dts_params.num_of_qman_channels = range[1];
2797
2798
2799 muram_node = of_find_matching_node(fm_node, fman_muram_match);
2800 if (!muram_node) {
2801 dev_err(&of_dev->dev, "%s: could not find MURAM node\n",
2802 __func__);
2803 goto fman_free;
2804 }
2805
2806 err = of_address_to_resource(muram_node, 0,
2807 &fman->dts_params.muram_res);
2808 if (err) {
2809 of_node_put(muram_node);
2810 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n",
2811 __func__, err);
2812 goto fman_free;
2813 }
2814
2815 of_node_put(muram_node);
2816
2817 err = devm_request_irq(&of_dev->dev, irq, fman_irq, IRQF_SHARED,
2818 "fman", fman);
2819 if (err < 0) {
2820 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2821 __func__, irq, err);
2822 goto fman_free;
2823 }
2824
2825 if (fman->dts_params.err_irq != 0) {
2826 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq,
2827 fman_err_irq, IRQF_SHARED,
2828 "fman-err", fman);
2829 if (err < 0) {
2830 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2831 __func__, fman->dts_params.err_irq, err);
2832 goto fman_free;
2833 }
2834 }
2835
2836 fman->dts_params.res =
2837 devm_request_mem_region(&of_dev->dev, phys_base_addr,
2838 mem_size, "fman");
2839 if (!fman->dts_params.res) {
2840 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n",
2841 __func__);
2842 goto fman_free;
2843 }
2844
2845 fman->dts_params.base_addr =
2846 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size);
2847 if (!fman->dts_params.base_addr) {
2848 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__);
2849 goto fman_free;
2850 }
2851
2852 fman->dev = &of_dev->dev;
2853
2854 err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev);
2855 if (err) {
2856 dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n",
2857 __func__);
2858 goto fman_free;
2859 }
2860
2861#ifdef CONFIG_DPAA_ERRATUM_A050385
2862 fman_has_err_a050385 =
2863 of_property_read_bool(fm_node, "fsl,erratum-a050385");
2864#endif
2865
2866 return fman;
2867
2868fman_node_put:
2869 of_node_put(fm_node);
2870fman_free:
2871 kfree(fman);
2872 return NULL;
2873}
2874
2875static int fman_probe(struct platform_device *of_dev)
2876{
2877 struct fman *fman;
2878 struct device *dev;
2879 int err;
2880
2881 dev = &of_dev->dev;
2882
2883 fman = read_dts_node(of_dev);
2884 if (!fman)
2885 return -EIO;
2886
2887 err = fman_config(fman);
2888 if (err) {
2889 dev_err(dev, "%s: FMan config failed\n", __func__);
2890 return -EINVAL;
2891 }
2892
2893 if (fman_init(fman) != 0) {
2894 dev_err(dev, "%s: FMan init failed\n", __func__);
2895 return -EINVAL;
2896 }
2897
2898 if (fman->dts_params.err_irq == 0) {
2899 fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false);
2900 fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false);
2901 fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false);
2902 fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false);
2903 fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false);
2904 fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false);
2905 fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false);
2906 fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false);
2907 fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false);
2908 fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false);
2909 fman_set_exception(fman,
2910 FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false);
2911 fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false);
2912 fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC,
2913 false);
2914 fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false);
2915 fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false);
2916 }
2917
2918 dev_set_drvdata(dev, fman);
2919
2920 dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id);
2921
2922 return 0;
2923}
2924
2925static const struct of_device_id fman_match[] = {
2926 {
2927 .compatible = "fsl,fman"},
2928 {}
2929};
2930
2931MODULE_DEVICE_TABLE(of, fman_match);
2932
2933static struct platform_driver fman_driver = {
2934 .driver = {
2935 .name = "fsl-fman",
2936 .of_match_table = fman_match,
2937 },
2938 .probe = fman_probe,
2939};
2940
2941static int __init fman_load(void)
2942{
2943 int err;
2944
2945 pr_debug("FSL DPAA FMan driver\n");
2946
2947 err = platform_driver_register(&fman_driver);
2948 if (err < 0)
2949 pr_err("Error, platform_driver_register() = %d\n", err);
2950
2951 return err;
2952}
2953module_init(fman_load);
2954
2955static void __exit fman_unload(void)
2956{
2957 platform_driver_unregister(&fman_driver);
2958}
2959module_exit(fman_unload);
2960
2961MODULE_LICENSE("Dual BSD/GPL");
2962MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver");
2963