linux/drivers/net/ethernet/freescale/fman/fman_memac.c
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   1/*
   2 * Copyright 2008-2015 Freescale Semiconductor Inc.
   3 *
   4 * Redistribution and use in source and binary forms, with or without
   5 * modification, are permitted provided that the following conditions are met:
   6 *     * Redistributions of source code must retain the above copyright
   7 *       notice, this list of conditions and the following disclaimer.
   8 *     * Redistributions in binary form must reproduce the above copyright
   9 *       notice, this list of conditions and the following disclaimer in the
  10 *       documentation and/or other materials provided with the distribution.
  11 *     * Neither the name of Freescale Semiconductor nor the
  12 *       names of its contributors may be used to endorse or promote products
  13 *       derived from this software without specific prior written permission.
  14 *
  15 *
  16 * ALTERNATIVELY, this software may be distributed under the terms of the
  17 * GNU General Public License ("GPL") as published by the Free Software
  18 * Foundation, either version 2 of that License or (at your option) any
  19 * later version.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 */
  32
  33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35#include "fman_memac.h"
  36#include "fman.h"
  37
  38#include <linux/slab.h>
  39#include <linux/io.h>
  40#include <linux/phy.h>
  41#include <linux/phy_fixed.h>
  42#include <linux/of_mdio.h>
  43
  44/* PCS registers */
  45#define MDIO_SGMII_CR                   0x00
  46#define MDIO_SGMII_DEV_ABIL_SGMII       0x04
  47#define MDIO_SGMII_LINK_TMR_L           0x12
  48#define MDIO_SGMII_LINK_TMR_H           0x13
  49#define MDIO_SGMII_IF_MODE              0x14
  50
  51/* SGMII Control defines */
  52#define SGMII_CR_AN_EN                  0x1000
  53#define SGMII_CR_RESTART_AN             0x0200
  54#define SGMII_CR_FD                     0x0100
  55#define SGMII_CR_SPEED_SEL1_1G          0x0040
  56#define SGMII_CR_DEF_VAL                (SGMII_CR_AN_EN | SGMII_CR_FD | \
  57                                         SGMII_CR_SPEED_SEL1_1G)
  58
  59/* SGMII Device Ability for SGMII defines */
  60#define MDIO_SGMII_DEV_ABIL_SGMII_MODE  0x4001
  61#define MDIO_SGMII_DEV_ABIL_BASEX_MODE  0x01A0
  62
  63/* Link timer define */
  64#define LINK_TMR_L                      0xa120
  65#define LINK_TMR_H                      0x0007
  66#define LINK_TMR_L_BASEX                0xaf08
  67#define LINK_TMR_H_BASEX                0x002f
  68
  69/* SGMII IF Mode defines */
  70#define IF_MODE_USE_SGMII_AN            0x0002
  71#define IF_MODE_SGMII_EN                0x0001
  72#define IF_MODE_SGMII_SPEED_100M        0x0004
  73#define IF_MODE_SGMII_SPEED_1G          0x0008
  74#define IF_MODE_SGMII_DUPLEX_HALF       0x0010
  75
  76/* Num of additional exact match MAC adr regs */
  77#define MEMAC_NUM_OF_PADDRS 7
  78
  79/* Control and Configuration Register (COMMAND_CONFIG) */
  80#define CMD_CFG_REG_LOWP_RXETY  0x01000000 /* 07 Rx low power indication */
  81#define CMD_CFG_TX_LOWP_ENA     0x00800000 /* 08 Tx Low Power Idle Enable */
  82#define CMD_CFG_PFC_MODE        0x00080000 /* 12 Enable PFC */
  83#define CMD_CFG_NO_LEN_CHK      0x00020000 /* 14 Payload length check disable */
  84#define CMD_CFG_SW_RESET        0x00001000 /* 19 S/W Reset, self clearing bit */
  85#define CMD_CFG_TX_PAD_EN       0x00000800 /* 20 Enable Tx padding of frames */
  86#define CMD_CFG_PAUSE_IGNORE    0x00000100 /* 23 Ignore Pause frame quanta */
  87#define CMD_CFG_CRC_FWD         0x00000040 /* 25 Terminate/frwd CRC of frames */
  88#define CMD_CFG_PAD_EN          0x00000020 /* 26 Frame padding removal */
  89#define CMD_CFG_PROMIS_EN       0x00000010 /* 27 Promiscuous operation enable */
  90#define CMD_CFG_RX_EN           0x00000002 /* 30 MAC receive path enable */
  91#define CMD_CFG_TX_EN           0x00000001 /* 31 MAC transmit path enable */
  92
  93/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
  94#define TX_FIFO_SECTIONS_TX_EMPTY_MASK                  0xFFFF0000
  95#define TX_FIFO_SECTIONS_TX_AVAIL_MASK                  0x0000FFFF
  96#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G           0x00400000
  97#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G            0x00100000
  98#define TX_FIFO_SECTIONS_TX_AVAIL_10G                   0x00000019
  99#define TX_FIFO_SECTIONS_TX_AVAIL_1G                    0x00000020
 100#define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G              0x00000060
 101
 102#define GET_TX_EMPTY_DEFAULT_VALUE(_val)                                \
 103do {                                                                    \
 104        _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK;                        \
 105        ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ?                      \
 106                        (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
 107                        (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
 108} while (0)
 109
 110/* Interface Mode Register (IF_MODE) */
 111
 112#define IF_MODE_MASK            0x00000003 /* 30-31 Mask on i/f mode bits */
 113#define IF_MODE_10G             0x00000000 /* 30-31 10G interface */
 114#define IF_MODE_GMII            0x00000002 /* 30-31 GMII (1G) interface */
 115#define IF_MODE_RGMII           0x00000004
 116#define IF_MODE_RGMII_AUTO      0x00008000
 117#define IF_MODE_RGMII_1000      0x00004000 /* 10 - 1000Mbps RGMII */
 118#define IF_MODE_RGMII_100       0x00000000 /* 00 - 100Mbps RGMII */
 119#define IF_MODE_RGMII_10        0x00002000 /* 01 - 10Mbps RGMII */
 120#define IF_MODE_RGMII_SP_MASK   0x00006000 /* Setsp mask bits */
 121#define IF_MODE_RGMII_FD        0x00001000 /* Full duplex RGMII */
 122#define IF_MODE_HD              0x00000040 /* Half duplex operation */
 123
 124/* Hash table Control Register (HASHTABLE_CTRL) */
 125#define HASH_CTRL_MCAST_EN      0x00000100
 126/* 26-31 Hash table address code */
 127#define HASH_CTRL_ADDR_MASK     0x0000003F
 128/* MAC mcast indication */
 129#define GROUP_ADDRESS           0x0000010000000000LL
 130#define HASH_TABLE_SIZE         64      /* Hash tbl size */
 131
 132/* Interrupt Mask Register (IMASK) */
 133#define MEMAC_IMASK_MGI         0x40000000 /* 1 Magic pkt detect indication */
 134#define MEMAC_IMASK_TSECC_ER    0x20000000 /* 2 Timestamp FIFO ECC error evnt */
 135#define MEMAC_IMASK_TECC_ER     0x02000000 /* 6 Transmit frame ECC error evnt */
 136#define MEMAC_IMASK_RECC_ER     0x01000000 /* 7 Receive frame ECC error evnt */
 137
 138#define MEMAC_ALL_ERRS_IMASK                                    \
 139                ((u32)(MEMAC_IMASK_TSECC_ER     |       \
 140                       MEMAC_IMASK_TECC_ER              |       \
 141                       MEMAC_IMASK_RECC_ER              |       \
 142                       MEMAC_IMASK_MGI))
 143
 144#define MEMAC_IEVNT_PCS                 0x80000000 /* PCS (XG). Link sync (G) */
 145#define MEMAC_IEVNT_AN                  0x40000000 /* Auto-negotiation */
 146#define MEMAC_IEVNT_LT                  0x20000000 /* Link Training/New page */
 147#define MEMAC_IEVNT_MGI                 0x00004000 /* Magic pkt detection */
 148#define MEMAC_IEVNT_TS_ECC_ER           0x00002000 /* Timestamp FIFO ECC error*/
 149#define MEMAC_IEVNT_RX_FIFO_OVFL        0x00001000 /* Rx FIFO overflow */
 150#define MEMAC_IEVNT_TX_FIFO_UNFL        0x00000800 /* Tx FIFO underflow */
 151#define MEMAC_IEVNT_TX_FIFO_OVFL        0x00000400 /* Tx FIFO overflow */
 152#define MEMAC_IEVNT_TX_ECC_ER           0x00000200 /* Tx frame ECC error */
 153#define MEMAC_IEVNT_RX_ECC_ER           0x00000100 /* Rx frame ECC error */
 154#define MEMAC_IEVNT_LI_FAULT            0x00000080 /* Link Interruption flt */
 155#define MEMAC_IEVNT_RX_EMPTY            0x00000040 /* Rx FIFO empty */
 156#define MEMAC_IEVNT_TX_EMPTY            0x00000020 /* Tx FIFO empty */
 157#define MEMAC_IEVNT_RX_LOWP             0x00000010 /* Low Power Idle */
 158#define MEMAC_IEVNT_PHY_LOS             0x00000004 /* Phy loss of signal */
 159#define MEMAC_IEVNT_REM_FAULT           0x00000002 /* Remote fault (XGMII) */
 160#define MEMAC_IEVNT_LOC_FAULT           0x00000001 /* Local fault (XGMII) */
 161
 162#define DEFAULT_PAUSE_QUANTA    0xf000
 163#define DEFAULT_FRAME_LENGTH    0x600
 164#define DEFAULT_TX_IPG_LENGTH   12
 165
 166#define CLXY_PAUSE_QUANTA_CLX_PQNT      0x0000FFFF
 167#define CLXY_PAUSE_QUANTA_CLY_PQNT      0xFFFF0000
 168#define CLXY_PAUSE_THRESH_CLX_QTH       0x0000FFFF
 169#define CLXY_PAUSE_THRESH_CLY_QTH       0xFFFF0000
 170
 171struct mac_addr {
 172        /* Lower 32 bits of 48-bit MAC address */
 173        u32 mac_addr_l;
 174        /* Upper 16 bits of 48-bit MAC address */
 175        u32 mac_addr_u;
 176};
 177
 178/* memory map */
 179struct memac_regs {
 180        u32 res0000[2];                 /* General Control and Status */
 181        u32 command_config;             /* 0x008 Ctrl and cfg */
 182        struct mac_addr mac_addr0;      /* 0x00C-0x010 MAC_ADDR_0...1 */
 183        u32 maxfrm;                     /* 0x014 Max frame length */
 184        u32 res0018[1];
 185        u32 rx_fifo_sections;           /* Receive FIFO configuration reg */
 186        u32 tx_fifo_sections;           /* Transmit FIFO configuration reg */
 187        u32 res0024[2];
 188        u32 hashtable_ctrl;             /* 0x02C Hash table control */
 189        u32 res0030[4];
 190        u32 ievent;                     /* 0x040 Interrupt event */
 191        u32 tx_ipg_length;              /* 0x044 Transmitter inter-packet-gap */
 192        u32 res0048;
 193        u32 imask;                      /* 0x04C Interrupt mask */
 194        u32 res0050;
 195        u32 pause_quanta[4];            /* 0x054 Pause quanta */
 196        u32 pause_thresh[4];            /* 0x064 Pause quanta threshold */
 197        u32 rx_pause_status;            /* 0x074 Receive pause status */
 198        u32 res0078[2];
 199        struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
 200        u32 lpwake_timer;               /* 0x0B8 Low Power Wakeup Timer */
 201        u32 sleep_timer;                /* 0x0BC Transmit EEE Low Power Timer */
 202        u32 res00c0[8];
 203        u32 statn_config;               /* 0x0E0 Statistics configuration */
 204        u32 res00e4[7];
 205        /* Rx Statistics Counter */
 206        u32 reoct_l;
 207        u32 reoct_u;
 208        u32 roct_l;
 209        u32 roct_u;
 210        u32 raln_l;
 211        u32 raln_u;
 212        u32 rxpf_l;
 213        u32 rxpf_u;
 214        u32 rfrm_l;
 215        u32 rfrm_u;
 216        u32 rfcs_l;
 217        u32 rfcs_u;
 218        u32 rvlan_l;
 219        u32 rvlan_u;
 220        u32 rerr_l;
 221        u32 rerr_u;
 222        u32 ruca_l;
 223        u32 ruca_u;
 224        u32 rmca_l;
 225        u32 rmca_u;
 226        u32 rbca_l;
 227        u32 rbca_u;
 228        u32 rdrp_l;
 229        u32 rdrp_u;
 230        u32 rpkt_l;
 231        u32 rpkt_u;
 232        u32 rund_l;
 233        u32 rund_u;
 234        u32 r64_l;
 235        u32 r64_u;
 236        u32 r127_l;
 237        u32 r127_u;
 238        u32 r255_l;
 239        u32 r255_u;
 240        u32 r511_l;
 241        u32 r511_u;
 242        u32 r1023_l;
 243        u32 r1023_u;
 244        u32 r1518_l;
 245        u32 r1518_u;
 246        u32 r1519x_l;
 247        u32 r1519x_u;
 248        u32 rovr_l;
 249        u32 rovr_u;
 250        u32 rjbr_l;
 251        u32 rjbr_u;
 252        u32 rfrg_l;
 253        u32 rfrg_u;
 254        u32 rcnp_l;
 255        u32 rcnp_u;
 256        u32 rdrntp_l;
 257        u32 rdrntp_u;
 258        u32 res01d0[12];
 259        /* Tx Statistics Counter */
 260        u32 teoct_l;
 261        u32 teoct_u;
 262        u32 toct_l;
 263        u32 toct_u;
 264        u32 res0210[2];
 265        u32 txpf_l;
 266        u32 txpf_u;
 267        u32 tfrm_l;
 268        u32 tfrm_u;
 269        u32 tfcs_l;
 270        u32 tfcs_u;
 271        u32 tvlan_l;
 272        u32 tvlan_u;
 273        u32 terr_l;
 274        u32 terr_u;
 275        u32 tuca_l;
 276        u32 tuca_u;
 277        u32 tmca_l;
 278        u32 tmca_u;
 279        u32 tbca_l;
 280        u32 tbca_u;
 281        u32 res0258[2];
 282        u32 tpkt_l;
 283        u32 tpkt_u;
 284        u32 tund_l;
 285        u32 tund_u;
 286        u32 t64_l;
 287        u32 t64_u;
 288        u32 t127_l;
 289        u32 t127_u;
 290        u32 t255_l;
 291        u32 t255_u;
 292        u32 t511_l;
 293        u32 t511_u;
 294        u32 t1023_l;
 295        u32 t1023_u;
 296        u32 t1518_l;
 297        u32 t1518_u;
 298        u32 t1519x_l;
 299        u32 t1519x_u;
 300        u32 res02a8[6];
 301        u32 tcnp_l;
 302        u32 tcnp_u;
 303        u32 res02c8[14];
 304        /* Line Interface Control */
 305        u32 if_mode;            /* 0x300 Interface Mode Control */
 306        u32 if_status;          /* 0x304 Interface Status */
 307        u32 res0308[14];
 308        /* HiGig/2 */
 309        u32 hg_config;          /* 0x340 Control and cfg */
 310        u32 res0344[3];
 311        u32 hg_pause_quanta;    /* 0x350 Pause quanta */
 312        u32 res0354[3];
 313        u32 hg_pause_thresh;    /* 0x360 Pause quanta threshold */
 314        u32 res0364[3];
 315        u32 hgrx_pause_status;  /* 0x370 Receive pause status */
 316        u32 hg_fifos_status;    /* 0x374 fifos status */
 317        u32 rhm;                /* 0x378 rx messages counter */
 318        u32 thm;                /* 0x37C tx messages counter */
 319};
 320
 321struct memac_cfg {
 322        bool reset_on_init;
 323        bool pause_ignore;
 324        bool promiscuous_mode_enable;
 325        struct fixed_phy_status *fixed_link;
 326        u16 max_frame_length;
 327        u16 pause_quanta;
 328        u32 tx_ipg_length;
 329};
 330
 331struct fman_mac {
 332        /* Pointer to MAC memory mapped registers */
 333        struct memac_regs __iomem *regs;
 334        /* MAC address of device */
 335        u64 addr;
 336        /* Ethernet physical interface */
 337        phy_interface_t phy_if;
 338        u16 max_speed;
 339        void *dev_id; /* device cookie used by the exception cbs */
 340        fman_mac_exception_cb *exception_cb;
 341        fman_mac_exception_cb *event_cb;
 342        /* Pointer to driver's global address hash table  */
 343        struct eth_hash_t *multicast_addr_hash;
 344        /* Pointer to driver's individual address hash table  */
 345        struct eth_hash_t *unicast_addr_hash;
 346        u8 mac_id;
 347        u32 exceptions;
 348        struct memac_cfg *memac_drv_param;
 349        void *fm;
 350        struct fman_rev_info fm_rev_info;
 351        bool basex_if;
 352        struct phy_device *pcsphy;
 353        bool allmulti_enabled;
 354};
 355
 356static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr,
 357                              u8 paddr_num)
 358{
 359        u32 tmp0, tmp1;
 360
 361        tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
 362        tmp1 = (u32)(adr[4] | adr[5] << 8);
 363
 364        if (paddr_num == 0) {
 365                iowrite32be(tmp0, &regs->mac_addr0.mac_addr_l);
 366                iowrite32be(tmp1, &regs->mac_addr0.mac_addr_u);
 367        } else {
 368                iowrite32be(tmp0, &regs->mac_addr[paddr_num - 1].mac_addr_l);
 369                iowrite32be(tmp1, &regs->mac_addr[paddr_num - 1].mac_addr_u);
 370        }
 371}
 372
 373static int reset(struct memac_regs __iomem *regs)
 374{
 375        u32 tmp;
 376        int count;
 377
 378        tmp = ioread32be(&regs->command_config);
 379
 380        tmp |= CMD_CFG_SW_RESET;
 381
 382        iowrite32be(tmp, &regs->command_config);
 383
 384        count = 100;
 385        do {
 386                udelay(1);
 387        } while ((ioread32be(&regs->command_config) & CMD_CFG_SW_RESET) &&
 388                 --count);
 389
 390        if (count == 0)
 391                return -EBUSY;
 392
 393        return 0;
 394}
 395
 396static void set_exception(struct memac_regs __iomem *regs, u32 val,
 397                          bool enable)
 398{
 399        u32 tmp;
 400
 401        tmp = ioread32be(&regs->imask);
 402        if (enable)
 403                tmp |= val;
 404        else
 405                tmp &= ~val;
 406
 407        iowrite32be(tmp, &regs->imask);
 408}
 409
 410static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
 411                phy_interface_t phy_if, u16 speed, bool slow_10g_if,
 412                u32 exceptions)
 413{
 414        u32 tmp;
 415
 416        /* Config */
 417        tmp = 0;
 418        if (cfg->promiscuous_mode_enable)
 419                tmp |= CMD_CFG_PROMIS_EN;
 420        if (cfg->pause_ignore)
 421                tmp |= CMD_CFG_PAUSE_IGNORE;
 422
 423        /* Payload length check disable */
 424        tmp |= CMD_CFG_NO_LEN_CHK;
 425        /* Enable padding of frames in transmit direction */
 426        tmp |= CMD_CFG_TX_PAD_EN;
 427
 428        tmp |= CMD_CFG_CRC_FWD;
 429
 430        iowrite32be(tmp, &regs->command_config);
 431
 432        /* Max Frame Length */
 433        iowrite32be((u32)cfg->max_frame_length, &regs->maxfrm);
 434
 435        /* Pause Time */
 436        iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
 437        iowrite32be((u32)0, &regs->pause_thresh[0]);
 438
 439        /* IF_MODE */
 440        tmp = 0;
 441        switch (phy_if) {
 442        case PHY_INTERFACE_MODE_XGMII:
 443                tmp |= IF_MODE_10G;
 444                break;
 445        default:
 446                tmp |= IF_MODE_GMII;
 447                if (phy_if == PHY_INTERFACE_MODE_RGMII ||
 448                    phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
 449                    phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
 450                    phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
 451                        tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
 452        }
 453        iowrite32be(tmp, &regs->if_mode);
 454
 455        /* TX_FIFO_SECTIONS */
 456        tmp = 0;
 457        if (phy_if == PHY_INTERFACE_MODE_XGMII) {
 458                if (slow_10g_if) {
 459                        tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
 460                                TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
 461                } else {
 462                        tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
 463                                TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
 464                }
 465        } else {
 466                tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
 467                        TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
 468        }
 469        iowrite32be(tmp, &regs->tx_fifo_sections);
 470
 471        /* clear all pending events and set-up interrupts */
 472        iowrite32be(0xffffffff, &regs->ievent);
 473        set_exception(regs, exceptions, true);
 474
 475        return 0;
 476}
 477
 478static void set_dflts(struct memac_cfg *cfg)
 479{
 480        cfg->reset_on_init = false;
 481        cfg->promiscuous_mode_enable = false;
 482        cfg->pause_ignore = false;
 483        cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
 484        cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
 485        cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
 486}
 487
 488static u32 get_mac_addr_hash_code(u64 eth_addr)
 489{
 490        u64 mask1, mask2;
 491        u32 xor_val = 0;
 492        u8 i, j;
 493
 494        for (i = 0; i < 6; i++) {
 495                mask1 = eth_addr & (u64)0x01;
 496                eth_addr >>= 1;
 497
 498                for (j = 0; j < 7; j++) {
 499                        mask2 = eth_addr & (u64)0x01;
 500                        mask1 ^= mask2;
 501                        eth_addr >>= 1;
 502                }
 503
 504                xor_val |= (mask1 << (5 - i));
 505        }
 506
 507        return xor_val;
 508}
 509
 510static void setup_sgmii_internal_phy(struct fman_mac *memac,
 511                                     struct fixed_phy_status *fixed_link)
 512{
 513        u16 tmp_reg16;
 514
 515        if (WARN_ON(!memac->pcsphy))
 516                return;
 517
 518        /* SGMII mode */
 519        tmp_reg16 = IF_MODE_SGMII_EN;
 520        if (!fixed_link)
 521                /* AN enable */
 522                tmp_reg16 |= IF_MODE_USE_SGMII_AN;
 523        else {
 524                switch (fixed_link->speed) {
 525                case 10:
 526                        /* For 10M: IF_MODE[SPEED_10M] = 0 */
 527                break;
 528                case 100:
 529                        tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
 530                break;
 531                case 1000: /* fallthrough */
 532                default:
 533                        tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
 534                break;
 535                }
 536                if (!fixed_link->duplex)
 537                        tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
 538        }
 539        phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
 540
 541        /* Device ability according to SGMII specification */
 542        tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
 543        phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
 544
 545        /* Adjust link timer for SGMII  -
 546         * According to Cisco SGMII specification the timer should be 1.6 ms.
 547         * The link_timer register is configured in units of the clock.
 548         * - When running as 1G SGMII, Serdes clock is 125 MHz, so
 549         * unit = 1 / (125*10^6 Hz) = 8 ns.
 550         * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
 551         * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
 552         * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
 553         * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
 554         * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
 555         * we always set up here a value of 2.5 SGMII.
 556         */
 557        phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
 558        phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
 559
 560        if (!fixed_link)
 561                /* Restart AN */
 562                tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
 563        else
 564                /* AN disabled */
 565                tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
 566        phy_write(memac->pcsphy, 0x0, tmp_reg16);
 567}
 568
 569static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
 570{
 571        u16 tmp_reg16;
 572
 573        /* AN Device capability  */
 574        tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
 575        phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
 576
 577        /* Adjust link timer for SGMII  -
 578         * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
 579         * The link_timer register is configured in units of the clock.
 580         * - When running as 1G SGMII, Serdes clock is 125 MHz, so
 581         * unit = 1 / (125*10^6 Hz) = 8 ns.
 582         * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
 583         * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
 584         * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
 585         * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
 586         * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
 587         * we always set up here a value of 2.5 SGMII.
 588         */
 589        phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
 590        phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
 591
 592        /* Restart AN */
 593        tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
 594        phy_write(memac->pcsphy, 0x0, tmp_reg16);
 595}
 596
 597static int check_init_parameters(struct fman_mac *memac)
 598{
 599        if (memac->addr == 0) {
 600                pr_err("Ethernet MAC must have a valid MAC address\n");
 601                return -EINVAL;
 602        }
 603        if (!memac->exception_cb) {
 604                pr_err("Uninitialized exception handler\n");
 605                return -EINVAL;
 606        }
 607        if (!memac->event_cb) {
 608                pr_warn("Uninitialize event handler\n");
 609                return -EINVAL;
 610        }
 611
 612        return 0;
 613}
 614
 615static int get_exception_flag(enum fman_mac_exceptions exception)
 616{
 617        u32 bit_mask;
 618
 619        switch (exception) {
 620        case FM_MAC_EX_10G_TX_ECC_ER:
 621                bit_mask = MEMAC_IMASK_TECC_ER;
 622                break;
 623        case FM_MAC_EX_10G_RX_ECC_ER:
 624                bit_mask = MEMAC_IMASK_RECC_ER;
 625                break;
 626        case FM_MAC_EX_TS_FIFO_ECC_ERR:
 627                bit_mask = MEMAC_IMASK_TSECC_ER;
 628                break;
 629        case FM_MAC_EX_MAGIC_PACKET_INDICATION:
 630                bit_mask = MEMAC_IMASK_MGI;
 631                break;
 632        default:
 633                bit_mask = 0;
 634                break;
 635        }
 636
 637        return bit_mask;
 638}
 639
 640static void memac_err_exception(void *handle)
 641{
 642        struct fman_mac *memac = (struct fman_mac *)handle;
 643        struct memac_regs __iomem *regs = memac->regs;
 644        u32 event, imask;
 645
 646        event = ioread32be(&regs->ievent);
 647        imask = ioread32be(&regs->imask);
 648
 649        /* Imask include both error and notification/event bits.
 650         * Leaving only error bits enabled by imask.
 651         * The imask error bits are shifted by 16 bits offset from
 652         * their corresponding location in the ievent - hence the >> 16
 653         */
 654        event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
 655
 656        iowrite32be(event, &regs->ievent);
 657
 658        if (event & MEMAC_IEVNT_TS_ECC_ER)
 659                memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
 660        if (event & MEMAC_IEVNT_TX_ECC_ER)
 661                memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
 662        if (event & MEMAC_IEVNT_RX_ECC_ER)
 663                memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
 664}
 665
 666static void memac_exception(void *handle)
 667{
 668        struct fman_mac *memac = (struct fman_mac *)handle;
 669        struct memac_regs __iomem *regs = memac->regs;
 670        u32 event, imask;
 671
 672        event = ioread32be(&regs->ievent);
 673        imask = ioread32be(&regs->imask);
 674
 675        /* Imask include both error and notification/event bits.
 676         * Leaving only error bits enabled by imask.
 677         * The imask error bits are shifted by 16 bits offset from
 678         * their corresponding location in the ievent - hence the >> 16
 679         */
 680        event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
 681
 682        iowrite32be(event, &regs->ievent);
 683
 684        if (event & MEMAC_IEVNT_MGI)
 685                memac->exception_cb(memac->dev_id,
 686                                    FM_MAC_EX_MAGIC_PACKET_INDICATION);
 687}
 688
 689static void free_init_resources(struct fman_mac *memac)
 690{
 691        fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
 692                             FMAN_INTR_TYPE_ERR);
 693
 694        fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
 695                             FMAN_INTR_TYPE_NORMAL);
 696
 697        /* release the driver's group hash table */
 698        free_hash_table(memac->multicast_addr_hash);
 699        memac->multicast_addr_hash = NULL;
 700
 701        /* release the driver's individual hash table */
 702        free_hash_table(memac->unicast_addr_hash);
 703        memac->unicast_addr_hash = NULL;
 704}
 705
 706static bool is_init_done(struct memac_cfg *memac_drv_params)
 707{
 708        /* Checks if mEMAC driver parameters were initialized */
 709        if (!memac_drv_params)
 710                return true;
 711
 712        return false;
 713}
 714
 715int memac_enable(struct fman_mac *memac, enum comm_mode mode)
 716{
 717        struct memac_regs __iomem *regs = memac->regs;
 718        u32 tmp;
 719
 720        if (!is_init_done(memac->memac_drv_param))
 721                return -EINVAL;
 722
 723        tmp = ioread32be(&regs->command_config);
 724        if (mode & COMM_MODE_RX)
 725                tmp |= CMD_CFG_RX_EN;
 726        if (mode & COMM_MODE_TX)
 727                tmp |= CMD_CFG_TX_EN;
 728
 729        iowrite32be(tmp, &regs->command_config);
 730
 731        return 0;
 732}
 733
 734int memac_disable(struct fman_mac *memac, enum comm_mode mode)
 735{
 736        struct memac_regs __iomem *regs = memac->regs;
 737        u32 tmp;
 738
 739        if (!is_init_done(memac->memac_drv_param))
 740                return -EINVAL;
 741
 742        tmp = ioread32be(&regs->command_config);
 743        if (mode & COMM_MODE_RX)
 744                tmp &= ~CMD_CFG_RX_EN;
 745        if (mode & COMM_MODE_TX)
 746                tmp &= ~CMD_CFG_TX_EN;
 747
 748        iowrite32be(tmp, &regs->command_config);
 749
 750        return 0;
 751}
 752
 753int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
 754{
 755        struct memac_regs __iomem *regs = memac->regs;
 756        u32 tmp;
 757
 758        if (!is_init_done(memac->memac_drv_param))
 759                return -EINVAL;
 760
 761        tmp = ioread32be(&regs->command_config);
 762        if (new_val)
 763                tmp |= CMD_CFG_PROMIS_EN;
 764        else
 765                tmp &= ~CMD_CFG_PROMIS_EN;
 766
 767        iowrite32be(tmp, &regs->command_config);
 768
 769        return 0;
 770}
 771
 772int memac_adjust_link(struct fman_mac *memac, u16 speed)
 773{
 774        struct memac_regs __iomem *regs = memac->regs;
 775        u32 tmp;
 776
 777        if (!is_init_done(memac->memac_drv_param))
 778                return -EINVAL;
 779
 780        tmp = ioread32be(&regs->if_mode);
 781
 782        /* Set full duplex */
 783        tmp &= ~IF_MODE_HD;
 784
 785        if (phy_interface_mode_is_rgmii(memac->phy_if)) {
 786                /* Configure RGMII in manual mode */
 787                tmp &= ~IF_MODE_RGMII_AUTO;
 788                tmp &= ~IF_MODE_RGMII_SP_MASK;
 789                /* Full duplex */
 790                tmp |= IF_MODE_RGMII_FD;
 791
 792                switch (speed) {
 793                case SPEED_1000:
 794                        tmp |= IF_MODE_RGMII_1000;
 795                        break;
 796                case SPEED_100:
 797                        tmp |= IF_MODE_RGMII_100;
 798                        break;
 799                case SPEED_10:
 800                        tmp |= IF_MODE_RGMII_10;
 801                        break;
 802                default:
 803                        break;
 804                }
 805        }
 806
 807        iowrite32be(tmp, &regs->if_mode);
 808
 809        return 0;
 810}
 811
 812int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val)
 813{
 814        if (is_init_done(memac->memac_drv_param))
 815                return -EINVAL;
 816
 817        memac->memac_drv_param->max_frame_length = new_val;
 818
 819        return 0;
 820}
 821
 822int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable)
 823{
 824        if (is_init_done(memac->memac_drv_param))
 825                return -EINVAL;
 826
 827        memac->memac_drv_param->reset_on_init = enable;
 828
 829        return 0;
 830}
 831
 832int memac_cfg_fixed_link(struct fman_mac *memac,
 833                         struct fixed_phy_status *fixed_link)
 834{
 835        if (is_init_done(memac->memac_drv_param))
 836                return -EINVAL;
 837
 838        memac->memac_drv_param->fixed_link = fixed_link;
 839
 840        return 0;
 841}
 842
 843int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
 844                              u16 pause_time, u16 thresh_time)
 845{
 846        struct memac_regs __iomem *regs = memac->regs;
 847        u32 tmp;
 848
 849        if (!is_init_done(memac->memac_drv_param))
 850                return -EINVAL;
 851
 852        tmp = ioread32be(&regs->tx_fifo_sections);
 853
 854        GET_TX_EMPTY_DEFAULT_VALUE(tmp);
 855        iowrite32be(tmp, &regs->tx_fifo_sections);
 856
 857        tmp = ioread32be(&regs->command_config);
 858        tmp &= ~CMD_CFG_PFC_MODE;
 859        priority = 0;
 860
 861        iowrite32be(tmp, &regs->command_config);
 862
 863        tmp = ioread32be(&regs->pause_quanta[priority / 2]);
 864        if (priority % 2)
 865                tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
 866        else
 867                tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
 868        tmp |= ((u32)pause_time << (16 * (priority % 2)));
 869        iowrite32be(tmp, &regs->pause_quanta[priority / 2]);
 870
 871        tmp = ioread32be(&regs->pause_thresh[priority / 2]);
 872        if (priority % 2)
 873                tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
 874        else
 875                tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
 876        tmp |= ((u32)thresh_time << (16 * (priority % 2)));
 877        iowrite32be(tmp, &regs->pause_thresh[priority / 2]);
 878
 879        return 0;
 880}
 881
 882int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
 883{
 884        struct memac_regs __iomem *regs = memac->regs;
 885        u32 tmp;
 886
 887        if (!is_init_done(memac->memac_drv_param))
 888                return -EINVAL;
 889
 890        tmp = ioread32be(&regs->command_config);
 891        if (en)
 892                tmp &= ~CMD_CFG_PAUSE_IGNORE;
 893        else
 894                tmp |= CMD_CFG_PAUSE_IGNORE;
 895
 896        iowrite32be(tmp, &regs->command_config);
 897
 898        return 0;
 899}
 900
 901int memac_modify_mac_address(struct fman_mac *memac, enet_addr_t *enet_addr)
 902{
 903        if (!is_init_done(memac->memac_drv_param))
 904                return -EINVAL;
 905
 906        add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0);
 907
 908        return 0;
 909}
 910
 911int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
 912{
 913        struct memac_regs __iomem *regs = memac->regs;
 914        struct eth_hash_entry *hash_entry;
 915        u32 hash;
 916        u64 addr;
 917
 918        if (!is_init_done(memac->memac_drv_param))
 919                return -EINVAL;
 920
 921        addr = ENET_ADDR_TO_UINT64(*eth_addr);
 922
 923        if (!(addr & GROUP_ADDRESS)) {
 924                /* Unicast addresses not supported in hash */
 925                pr_err("Unicast Address\n");
 926                return -EINVAL;
 927        }
 928        hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
 929
 930        /* Create element to be added to the driver hash table */
 931        hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
 932        if (!hash_entry)
 933                return -ENOMEM;
 934        hash_entry->addr = addr;
 935        INIT_LIST_HEAD(&hash_entry->node);
 936
 937        list_add_tail(&hash_entry->node,
 938                      &memac->multicast_addr_hash->lsts[hash]);
 939        iowrite32be(hash | HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
 940
 941        return 0;
 942}
 943
 944int memac_set_allmulti(struct fman_mac *memac, bool enable)
 945{
 946        u32 entry;
 947        struct memac_regs __iomem *regs = memac->regs;
 948
 949        if (!is_init_done(memac->memac_drv_param))
 950                return -EINVAL;
 951
 952        if (enable) {
 953                for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
 954                        iowrite32be(entry | HASH_CTRL_MCAST_EN,
 955                                    &regs->hashtable_ctrl);
 956        } else {
 957                for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
 958                        iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
 959                                    &regs->hashtable_ctrl);
 960        }
 961
 962        memac->allmulti_enabled = enable;
 963
 964        return 0;
 965}
 966
 967int memac_set_tstamp(struct fman_mac *memac, bool enable)
 968{
 969        return 0; /* Always enabled. */
 970}
 971
 972int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
 973{
 974        struct memac_regs __iomem *regs = memac->regs;
 975        struct eth_hash_entry *hash_entry = NULL;
 976        struct list_head *pos;
 977        u32 hash;
 978        u64 addr;
 979
 980        if (!is_init_done(memac->memac_drv_param))
 981                return -EINVAL;
 982
 983        addr = ENET_ADDR_TO_UINT64(*eth_addr);
 984
 985        hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
 986
 987        list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
 988                hash_entry = ETH_HASH_ENTRY_OBJ(pos);
 989                if (hash_entry->addr == addr) {
 990                        list_del_init(&hash_entry->node);
 991                        kfree(hash_entry);
 992                        break;
 993                }
 994        }
 995
 996        if (!memac->allmulti_enabled) {
 997                if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
 998                        iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
 999                                    &regs->hashtable_ctrl);
1000        }
1001
1002        return 0;
1003}
1004
1005int memac_set_exception(struct fman_mac *memac,
1006                        enum fman_mac_exceptions exception, bool enable)
1007{
1008        u32 bit_mask = 0;
1009
1010        if (!is_init_done(memac->memac_drv_param))
1011                return -EINVAL;
1012
1013        bit_mask = get_exception_flag(exception);
1014        if (bit_mask) {
1015                if (enable)
1016                        memac->exceptions |= bit_mask;
1017                else
1018                        memac->exceptions &= ~bit_mask;
1019        } else {
1020                pr_err("Undefined exception\n");
1021                return -EINVAL;
1022        }
1023        set_exception(memac->regs, bit_mask, enable);
1024
1025        return 0;
1026}
1027
1028int memac_init(struct fman_mac *memac)
1029{
1030        struct memac_cfg *memac_drv_param;
1031        u8 i;
1032        enet_addr_t eth_addr;
1033        bool slow_10g_if = false;
1034        struct fixed_phy_status *fixed_link;
1035        int err;
1036        u32 reg32 = 0;
1037
1038        if (is_init_done(memac->memac_drv_param))
1039                return -EINVAL;
1040
1041        err = check_init_parameters(memac);
1042        if (err)
1043                return err;
1044
1045        memac_drv_param = memac->memac_drv_param;
1046
1047        if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
1048                slow_10g_if = true;
1049
1050        /* First, reset the MAC if desired. */
1051        if (memac_drv_param->reset_on_init) {
1052                err = reset(memac->regs);
1053                if (err) {
1054                        pr_err("mEMAC reset failed\n");
1055                        return err;
1056                }
1057        }
1058
1059        /* MAC Address */
1060        MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
1061        add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0);
1062
1063        fixed_link = memac_drv_param->fixed_link;
1064
1065        init(memac->regs, memac->memac_drv_param, memac->phy_if,
1066             memac->max_speed, slow_10g_if, memac->exceptions);
1067
1068        /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
1069         * Exists only in FMan 6.0 and 6.3.
1070         */
1071        if ((memac->fm_rev_info.major == 6) &&
1072            ((memac->fm_rev_info.minor == 0) ||
1073            (memac->fm_rev_info.minor == 3))) {
1074                /* MAC strips CRC from received frames - this workaround
1075                 * should decrease the likelihood of bug appearance
1076                 */
1077                reg32 = ioread32be(&memac->regs->command_config);
1078                reg32 &= ~CMD_CFG_CRC_FWD;
1079                iowrite32be(reg32, &memac->regs->command_config);
1080        }
1081
1082        if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
1083                /* Configure internal SGMII PHY */
1084                if (memac->basex_if)
1085                        setup_sgmii_internal_phy_base_x(memac);
1086                else
1087                        setup_sgmii_internal_phy(memac, fixed_link);
1088        } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1089                /* Configure 4 internal SGMII PHYs */
1090                for (i = 0; i < 4; i++) {
1091                        u8 qsmgii_phy_addr, phy_addr;
1092                        /* QSGMII PHY address occupies 3 upper bits of 5-bit
1093                         * phy_address; the lower 2 bits are used to extend
1094                         * register address space and access each one of 4
1095                         * ports inside QSGMII.
1096                         */
1097                        phy_addr = memac->pcsphy->mdio.addr;
1098                        qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
1099                        memac->pcsphy->mdio.addr = qsmgii_phy_addr;
1100                        if (memac->basex_if)
1101                                setup_sgmii_internal_phy_base_x(memac);
1102                        else
1103                                setup_sgmii_internal_phy(memac, fixed_link);
1104
1105                        memac->pcsphy->mdio.addr = phy_addr;
1106                }
1107        }
1108
1109        /* Max Frame Length */
1110        err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
1111                                     memac_drv_param->max_frame_length);
1112        if (err) {
1113                pr_err("settings Mac max frame length is FAILED\n");
1114                return err;
1115        }
1116
1117        memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1118        if (!memac->multicast_addr_hash) {
1119                free_init_resources(memac);
1120                pr_err("allocation hash table is FAILED\n");
1121                return -ENOMEM;
1122        }
1123
1124        memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1125        if (!memac->unicast_addr_hash) {
1126                free_init_resources(memac);
1127                pr_err("allocation hash table is FAILED\n");
1128                return -ENOMEM;
1129        }
1130
1131        fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1132                           FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
1133
1134        fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1135                           FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
1136
1137        kfree(memac_drv_param);
1138        memac->memac_drv_param = NULL;
1139
1140        return 0;
1141}
1142
1143int memac_free(struct fman_mac *memac)
1144{
1145        free_init_resources(memac);
1146
1147        if (memac->pcsphy)
1148                put_device(&memac->pcsphy->mdio.dev);
1149
1150        kfree(memac->memac_drv_param);
1151        kfree(memac);
1152
1153        return 0;
1154}
1155
1156struct fman_mac *memac_config(struct fman_mac_params *params)
1157{
1158        struct fman_mac *memac;
1159        struct memac_cfg *memac_drv_param;
1160        void __iomem *base_addr;
1161
1162        base_addr = params->base_addr;
1163        /* allocate memory for the m_emac data structure */
1164        memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1165        if (!memac)
1166                return NULL;
1167
1168        /* allocate memory for the m_emac driver parameters data structure */
1169        memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1170        if (!memac_drv_param) {
1171                memac_free(memac);
1172                return NULL;
1173        }
1174
1175        /* Plant parameter structure pointer */
1176        memac->memac_drv_param = memac_drv_param;
1177
1178        set_dflts(memac_drv_param);
1179
1180        memac->addr = ENET_ADDR_TO_UINT64(params->addr);
1181
1182        memac->regs = base_addr;
1183        memac->max_speed = params->max_speed;
1184        memac->phy_if = params->phy_if;
1185        memac->mac_id = params->mac_id;
1186        memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1187                             MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1188        memac->exception_cb = params->exception_cb;
1189        memac->event_cb = params->event_cb;
1190        memac->dev_id = params->dev_id;
1191        memac->fm = params->fm;
1192        memac->basex_if = params->basex_if;
1193
1194        /* Save FMan revision */
1195        fman_get_revision(memac->fm, &memac->fm_rev_info);
1196
1197        if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
1198            memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1199                if (!params->internal_phy_node) {
1200                        pr_err("PCS PHY node is not available\n");
1201                        memac_free(memac);
1202                        return NULL;
1203                }
1204
1205                memac->pcsphy = of_phy_find_device(params->internal_phy_node);
1206                if (!memac->pcsphy) {
1207                        pr_err("of_phy_find_device (PCS PHY) failed\n");
1208                        memac_free(memac);
1209                        return NULL;
1210                }
1211        }
1212
1213        return memac;
1214}
1215