LXR linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/* Copyright (c) 2016-2017 Hisilicon Limited. */
   3
   4#ifndef __HCLGEVF_MAIN_H
   5#define __HCLGEVF_MAIN_H
   6#include <linux/fs.h>
   7#include <linux/if_vlan.h>
   8#include <linux/types.h>
   9#include "hclge_mbx.h"
  10#include "hclgevf_cmd.h"
  11#include "hnae3.h"
  12
  13#define HCLGEVF_MOD_VERSION "1.0"
  14#define HCLGEVF_DRIVER_NAME "hclgevf"
  15
  16#define HCLGEVF_MAX_VLAN_ID     4095
  17#define HCLGEVF_MISC_VECTOR_NUM         0
  18
  19#define HCLGEVF_INVALID_VPORT           0xffff
  20#define HCLGEVF_GENERAL_TASK_INTERVAL     5
  21#define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2
  22
  23/* This number in actual depends upon the total number of VFs
  24 * created by physical function. But the maximum number of
  25 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
  26 */
  27#define HCLGEVF_MAX_VF_VECTOR_NUM       (32 + 1)
  28
  29#define HCLGEVF_VECTOR_REG_BASE         0x20000
  30#define HCLGEVF_MISC_VECTOR_REG_BASE    0x20400
  31#define HCLGEVF_VECTOR_REG_OFFSET       0x4
  32#define HCLGEVF_VECTOR_VF_OFFSET                0x100000
  33
  34/* bar registers for cmdq */
  35#define HCLGEVF_CMDQ_TX_ADDR_L_REG              0x27000
  36#define HCLGEVF_CMDQ_TX_ADDR_H_REG              0x27004
  37#define HCLGEVF_CMDQ_TX_DEPTH_REG               0x27008
  38#define HCLGEVF_CMDQ_TX_TAIL_REG                0x27010
  39#define HCLGEVF_CMDQ_TX_HEAD_REG                0x27014
  40#define HCLGEVF_CMDQ_RX_ADDR_L_REG              0x27018
  41#define HCLGEVF_CMDQ_RX_ADDR_H_REG              0x2701C
  42#define HCLGEVF_CMDQ_RX_DEPTH_REG               0x27020
  43#define HCLGEVF_CMDQ_RX_TAIL_REG                0x27024
  44#define HCLGEVF_CMDQ_RX_HEAD_REG                0x27028
  45#define HCLGEVF_CMDQ_INTR_SRC_REG               0x27100
  46#define HCLGEVF_CMDQ_INTR_STS_REG               0x27104
  47#define HCLGEVF_CMDQ_INTR_EN_REG                0x27108
  48#define HCLGEVF_CMDQ_INTR_GEN_REG               0x2710C
  49
  50/* bar registers for common func */
  51#define HCLGEVF_GRO_EN_REG                      0x28000
  52
  53/* bar registers for rcb */
  54#define HCLGEVF_RING_RX_ADDR_L_REG              0x80000
  55#define HCLGEVF_RING_RX_ADDR_H_REG              0x80004
  56#define HCLGEVF_RING_RX_BD_NUM_REG              0x80008
  57#define HCLGEVF_RING_RX_BD_LENGTH_REG           0x8000C
  58#define HCLGEVF_RING_RX_MERGE_EN_REG            0x80014
  59#define HCLGEVF_RING_RX_TAIL_REG                0x80018
  60#define HCLGEVF_RING_RX_HEAD_REG                0x8001C
  61#define HCLGEVF_RING_RX_FBD_NUM_REG             0x80020
  62#define HCLGEVF_RING_RX_OFFSET_REG              0x80024
  63#define HCLGEVF_RING_RX_FBD_OFFSET_REG          0x80028
  64#define HCLGEVF_RING_RX_STASH_REG               0x80030
  65#define HCLGEVF_RING_RX_BD_ERR_REG              0x80034
  66#define HCLGEVF_RING_TX_ADDR_L_REG              0x80040
  67#define HCLGEVF_RING_TX_ADDR_H_REG              0x80044
  68#define HCLGEVF_RING_TX_BD_NUM_REG              0x80048
  69#define HCLGEVF_RING_TX_PRIORITY_REG            0x8004C
  70#define HCLGEVF_RING_TX_TC_REG                  0x80050
  71#define HCLGEVF_RING_TX_MERGE_EN_REG            0x80054
  72#define HCLGEVF_RING_TX_TAIL_REG                0x80058
  73#define HCLGEVF_RING_TX_HEAD_REG                0x8005C
  74#define HCLGEVF_RING_TX_FBD_NUM_REG             0x80060
  75#define HCLGEVF_RING_TX_OFFSET_REG              0x80064
  76#define HCLGEVF_RING_TX_EBD_NUM_REG             0x80068
  77#define HCLGEVF_RING_TX_EBD_OFFSET_REG          0x80070
  78#define HCLGEVF_RING_TX_BD_ERR_REG              0x80074
  79#define HCLGEVF_RING_EN_REG                     0x80090
  80
  81/* bar registers for tqp interrupt */
  82#define HCLGEVF_TQP_INTR_CTRL_REG               0x20000
  83#define HCLGEVF_TQP_INTR_GL0_REG                0x20100
  84#define HCLGEVF_TQP_INTR_GL1_REG                0x20200
  85#define HCLGEVF_TQP_INTR_GL2_REG                0x20300
  86#define HCLGEVF_TQP_INTR_RL_REG                 0x20900
  87
  88/* Vector0 interrupt CMDQ event source register(RW) */
  89#define HCLGEVF_VECTOR0_CMDQ_SRC_REG    0x27100
  90/* Vector0 interrupt CMDQ event status register(RO) */
  91#define HCLGEVF_VECTOR0_CMDQ_STAT_REG   0x27104
  92/* CMDQ register bits for RX event(=MBX event) */
  93#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B   1
  94/* RST register bits for RESET event */
  95#define HCLGEVF_VECTOR0_RST_INT_B       2
  96
  97#define HCLGEVF_TQP_RESET_TRY_TIMES     10
  98/* Reset related Registers */
  99#define HCLGEVF_RST_ING                 0x20C00
 100#define HCLGEVF_FUN_RST_ING_BIT         BIT(0)
 101#define HCLGEVF_GLOBAL_RST_ING_BIT      BIT(5)
 102#define HCLGEVF_CORE_RST_ING_BIT        BIT(6)
 103#define HCLGEVF_IMP_RST_ING_BIT         BIT(7)
 104#define HCLGEVF_RST_ING_BITS \
 105        (HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
 106         HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)
 107
 108#define HCLGEVF_VF_RST_ING              0x07008
 109#define HCLGEVF_VF_RST_ING_BIT          BIT(16)
 110
 111#define HCLGEVF_RSS_IND_TBL_SIZE                512
 112#define HCLGEVF_RSS_SET_BITMAP_MSK      0xffff
 113#define HCLGEVF_RSS_KEY_SIZE            40
 114#define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ  0
 115#define HCLGEVF_RSS_HASH_ALGO_SIMPLE    1
 116#define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
 117#define HCLGEVF_RSS_HASH_ALGO_MASK      0xf
 118#define HCLGEVF_RSS_CFG_TBL_NUM \
 119        (HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
 120#define HCLGEVF_RSS_INPUT_TUPLE_OTHER   GENMASK(3, 0)
 121#define HCLGEVF_RSS_INPUT_TUPLE_SCTP    GENMASK(4, 0)
 122#define HCLGEVF_D_PORT_BIT              BIT(0)
 123#define HCLGEVF_S_PORT_BIT              BIT(1)
 124#define HCLGEVF_D_IP_BIT                BIT(2)
 125#define HCLGEVF_S_IP_BIT                BIT(3)
 126#define HCLGEVF_V_TAG_BIT               BIT(4)
 127
 128#define HCLGEVF_STATS_TIMER_INTERVAL    36U
 129
 130enum hclgevf_evt_cause {
 131        HCLGEVF_VECTOR0_EVENT_RST,
 132        HCLGEVF_VECTOR0_EVENT_MBX,
 133        HCLGEVF_VECTOR0_EVENT_OTHER,
 134};
 135
 136/* states of hclgevf device & tasks */
 137enum hclgevf_states {
 138        /* device states */
 139        HCLGEVF_STATE_DOWN,
 140        HCLGEVF_STATE_DISABLED,
 141        HCLGEVF_STATE_IRQ_INITED,
 142        HCLGEVF_STATE_REMOVING,
 143        HCLGEVF_STATE_NIC_REGISTERED,
 144        /* task states */
 145        HCLGEVF_STATE_RST_SERVICE_SCHED,
 146        HCLGEVF_STATE_RST_HANDLING,
 147        HCLGEVF_STATE_MBX_SERVICE_SCHED,
 148        HCLGEVF_STATE_MBX_HANDLING,
 149        HCLGEVF_STATE_CMD_DISABLE,
 150        HCLGEVF_STATE_LINK_UPDATING,
 151        HCLGEVF_STATE_RST_FAIL,
 152};
 153
 154struct hclgevf_mac {
 155        u8 media_type;
 156        u8 module_type;
 157        u8 mac_addr[ETH_ALEN];
 158        int link;
 159        u8 duplex;
 160        u32 speed;
 161        u64 supported;
 162        u64 advertising;
 163};
 164
 165struct hclgevf_hw {
 166        void __iomem *io_base;
 167        int num_vec;
 168        struct hclgevf_cmq cmq;
 169        struct hclgevf_mac mac;
 170        void *hdev; /* hchgevf device it is part of */
 171};
 172
 173/* TQP stats */
 174struct hlcgevf_tqp_stats {
 175        /* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
 176        u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
 177        /* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
 178        u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
 179};
 180
 181struct hclgevf_tqp {
 182        struct device *dev;     /* device for DMA mapping */
 183        struct hnae3_queue q;
 184        struct hlcgevf_tqp_stats tqp_stats;
 185        u16 index;              /* global index in a NIC controller */
 186
 187        bool alloced;
 188};
 189
 190struct hclgevf_cfg {
 191        u8 vmdq_vport_num;
 192        u8 tc_num;
 193        u16 tqp_desc_num;
 194        u16 rx_buf_len;
 195        u8 phy_addr;
 196        u8 media_type;
 197        u8 mac_addr[ETH_ALEN];
 198        u32 numa_node_map;
 199};
 200
 201struct hclgevf_rss_tuple_cfg {
 202        u8 ipv4_tcp_en;
 203        u8 ipv4_udp_en;
 204        u8 ipv4_sctp_en;
 205        u8 ipv4_fragment_en;
 206        u8 ipv6_tcp_en;
 207        u8 ipv6_udp_en;
 208        u8 ipv6_sctp_en;
 209        u8 ipv6_fragment_en;
 210};
 211
 212struct hclgevf_rss_cfg {
 213        u8  rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
 214        u32 hash_algo;
 215        u32 rss_size;
 216        u8 hw_tc_map;
 217        u8  rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
 218        struct hclgevf_rss_tuple_cfg rss_tuple_sets;
 219};
 220
 221struct hclgevf_misc_vector {
 222        u8 __iomem *addr;
 223        int vector_irq;
 224        char name[HNAE3_INT_NAME_LEN];
 225};
 226
 227struct hclgevf_rst_stats {
 228        u32 rst_cnt;                    /* the number of reset */
 229        u32 vf_func_rst_cnt;            /* the number of VF function reset */
 230        u32 flr_rst_cnt;                /* the number of FLR */
 231        u32 vf_rst_cnt;                 /* the number of VF reset */
 232        u32 rst_done_cnt;               /* the number of reset completed */
 233        u32 hw_rst_done_cnt;            /* the number of HW reset completed */
 234        u32 rst_fail_cnt;               /* the number of VF reset fail */
 235};
 236
 237struct hclgevf_dev {
 238        struct pci_dev *pdev;
 239        struct hnae3_ae_dev *ae_dev;
 240        struct hclgevf_hw hw;
 241        struct hclgevf_misc_vector misc_vector;
 242        struct hclgevf_rss_cfg rss_cfg;
 243        unsigned long state;
 244        unsigned long flr_state;
 245        unsigned long default_reset_request;
 246        unsigned long last_reset_time;
 247        enum hnae3_reset_type reset_level;
 248        unsigned long reset_pending;
 249        enum hnae3_reset_type reset_type;
 250
 251#define HCLGEVF_RESET_REQUESTED         0
 252#define HCLGEVF_RESET_PENDING           1
 253        unsigned long reset_state;      /* requested, pending */
 254        struct hclgevf_rst_stats rst_stats;
 255        u32 reset_attempts;
 256        struct semaphore reset_sem;     /* protect reset process */
 257
 258        u32 fw_version;
 259        u16 num_tqps;           /* num task queue pairs of this PF */
 260
 261        u16 alloc_rss_size;     /* allocated RSS task queue */
 262        u16 rss_size_max;       /* HW defined max RSS task queue */
 263
 264        u16 num_alloc_vport;    /* num vports this driver supports */
 265        u32 numa_node_mask;
 266        u16 rx_buf_len;
 267        u16 num_tx_desc;        /* desc num of per tx queue */
 268        u16 num_rx_desc;        /* desc num of per rx queue */
 269        u8 hw_tc_map;
 270        u8 has_pf_mac;
 271
 272        u16 num_msi;
 273        u16 num_msi_left;
 274        u16 num_msi_used;
 275        u16 num_nic_msix;       /* Num of nic vectors for this VF */
 276        u16 num_roce_msix;      /* Num of roce vectors for this VF */
 277        u16 roce_base_msix_offset;
 278        int roce_base_vector;
 279        u32 base_msi_vector;
 280        u16 *vector_status;
 281        int *vector_irq;
 282
 283        unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
 284
 285        bool mbx_event_pending;
 286        struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
 287        struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
 288
 289        struct delayed_work service_task;
 290
 291        struct hclgevf_tqp *htqp;
 292
 293        struct hnae3_handle nic;
 294        struct hnae3_handle roce;
 295
 296        struct hnae3_client *nic_client;
 297        struct hnae3_client *roce_client;
 298        u32 flag;
 299        unsigned long serv_processed_cnt;
 300        unsigned long last_serv_processed;
 301};
 302
 303static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
 304{
 305        return !!hdev->reset_pending;
 306}
 307
 308int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
 309                         const u8 *msg_data, u8 msg_len, bool need_resp,
 310                         u8 *resp_data, u16 resp_len);
 311void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
 312void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
 313
 314void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
 315void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
 316                                 u8 duplex);
 317void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
 318void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
 319void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
 320                                        u8 *port_base_vlan_info, u8 data_size);
 321#endif
 322