1
2
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/aer.h>
27#include <linux/prefetch.h>
28
29#include "e1000.h"
30
31#define DRV_EXTRAVERSION "-k"
32
33#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
34char e1000e_driver_name[] = "e1000e";
35const char e1000e_driver_version[] = DRV_VERSION;
36
37#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
38static int debug = -1;
39module_param(debug, int, 0);
40MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
41
42static const struct e1000_info *e1000_info_tbl[] = {
43 [board_82571] = &e1000_82571_info,
44 [board_82572] = &e1000_82572_info,
45 [board_82573] = &e1000_82573_info,
46 [board_82574] = &e1000_82574_info,
47 [board_82583] = &e1000_82583_info,
48 [board_80003es2lan] = &e1000_es2_info,
49 [board_ich8lan] = &e1000_ich8_info,
50 [board_ich9lan] = &e1000_ich9_info,
51 [board_ich10lan] = &e1000_ich10_info,
52 [board_pchlan] = &e1000_pch_info,
53 [board_pch2lan] = &e1000_pch2_info,
54 [board_pch_lpt] = &e1000_pch_lpt_info,
55 [board_pch_spt] = &e1000_pch_spt_info,
56 [board_pch_cnp] = &e1000_pch_cnp_info,
57};
58
59struct e1000_reg_info {
60 u32 ofs;
61 char *name;
62};
63
64static const struct e1000_reg_info e1000_reg_info_tbl[] = {
65
66 {E1000_CTRL, "CTRL"},
67 {E1000_STATUS, "STATUS"},
68 {E1000_CTRL_EXT, "CTRL_EXT"},
69
70
71 {E1000_ICR, "ICR"},
72
73
74 {E1000_RCTL, "RCTL"},
75 {E1000_RDLEN(0), "RDLEN"},
76 {E1000_RDH(0), "RDH"},
77 {E1000_RDT(0), "RDT"},
78 {E1000_RDTR, "RDTR"},
79 {E1000_RXDCTL(0), "RXDCTL"},
80 {E1000_ERT, "ERT"},
81 {E1000_RDBAL(0), "RDBAL"},
82 {E1000_RDBAH(0), "RDBAH"},
83 {E1000_RDFH, "RDFH"},
84 {E1000_RDFT, "RDFT"},
85 {E1000_RDFHS, "RDFHS"},
86 {E1000_RDFTS, "RDFTS"},
87 {E1000_RDFPC, "RDFPC"},
88
89
90 {E1000_TCTL, "TCTL"},
91 {E1000_TDBAL(0), "TDBAL"},
92 {E1000_TDBAH(0), "TDBAH"},
93 {E1000_TDLEN(0), "TDLEN"},
94 {E1000_TDH(0), "TDH"},
95 {E1000_TDT(0), "TDT"},
96 {E1000_TIDV, "TIDV"},
97 {E1000_TXDCTL(0), "TXDCTL"},
98 {E1000_TADV, "TADV"},
99 {E1000_TARC(0), "TARC"},
100 {E1000_TDFH, "TDFH"},
101 {E1000_TDFT, "TDFT"},
102 {E1000_TDFHS, "TDFHS"},
103 {E1000_TDFTS, "TDFTS"},
104 {E1000_TDFPC, "TDFPC"},
105
106
107 {0, NULL}
108};
109
110
111
112
113
114
115
116
117
118
119
120
121
122s32 __ew32_prepare(struct e1000_hw *hw)
123{
124 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
125
126 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
127 udelay(50);
128
129 return i;
130}
131
132void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
133{
134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
135 __ew32_prepare(hw);
136
137 writel(val, hw->hw_addr + reg);
138}
139
140
141
142
143
144
145static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
146{
147 int n = 0;
148 char rname[16];
149 u32 regs[8];
150
151 switch (reginfo->ofs) {
152 case E1000_RXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_RXDCTL(n));
155 break;
156 case E1000_TXDCTL(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TXDCTL(n));
159 break;
160 case E1000_TARC(0):
161 for (n = 0; n < 2; n++)
162 regs[n] = __er32(hw, E1000_TARC(n));
163 break;
164 default:
165 pr_info("%-15s %08x\n",
166 reginfo->name, __er32(hw, reginfo->ofs));
167 return;
168 }
169
170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
172}
173
174static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
175 struct e1000_buffer *bi)
176{
177 int i;
178 struct e1000_ps_page *ps_page;
179
180 for (i = 0; i < adapter->rx_ps_pages; i++) {
181 ps_page = &bi->ps_pages[i];
182
183 if (ps_page->page) {
184 pr_info("packet dump for ps_page %d:\n", i);
185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
186 16, 1, page_address(ps_page->page),
187 PAGE_SIZE, true);
188 }
189 }
190}
191
192
193
194
195
196static void e1000e_dump(struct e1000_adapter *adapter)
197{
198 struct net_device *netdev = adapter->netdev;
199 struct e1000_hw *hw = &adapter->hw;
200 struct e1000_reg_info *reginfo;
201 struct e1000_ring *tx_ring = adapter->tx_ring;
202 struct e1000_tx_desc *tx_desc;
203 struct my_u0 {
204 __le64 a;
205 __le64 b;
206 } *u0;
207 struct e1000_buffer *buffer_info;
208 struct e1000_ring *rx_ring = adapter->rx_ring;
209 union e1000_rx_desc_packet_split *rx_desc_ps;
210 union e1000_rx_desc_extended *rx_desc;
211 struct my_u1 {
212 __le64 a;
213 __le64 b;
214 __le64 c;
215 __le64 d;
216 } *u1;
217 u32 staterr;
218 int i = 0;
219
220 if (!netif_msg_hw(adapter))
221 return;
222
223
224 if (netdev) {
225 dev_info(&adapter->pdev->dev, "Net device Info\n");
226 pr_info("Device Name state trans_start\n");
227 pr_info("%-15s %016lX %016lX\n", netdev->name,
228 netdev->state, dev_trans_start(netdev));
229 }
230
231
232 dev_info(&adapter->pdev->dev, "Register Dump\n");
233 pr_info(" Register Name Value\n");
234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
235 reginfo->name; reginfo++) {
236 e1000_regdump(hw, reginfo);
237 }
238
239
240 if (!netdev || !netif_running(netdev))
241 return;
242
243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
247 0, tx_ring->next_to_use, tx_ring->next_to_clean,
248 (unsigned long long)buffer_info->dma,
249 buffer_info->length,
250 buffer_info->next_to_watch,
251 (unsigned long long)buffer_info->time_stamp);
252
253
254 if (!netif_msg_tx_done(adapter))
255 goto rx_ring_summary;
256
257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
258
259
260
261
262
263
264
265
266
267
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270
271
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273
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280
281
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283
284
285
286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
290 const char *next_desc;
291 tx_desc = E1000_TX_DESC(*tx_ring, i);
292 buffer_info = &tx_ring->buffer_info[i];
293 u0 = (struct my_u0 *)tx_desc;
294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
295 next_desc = " NTC/U";
296 else if (i == tx_ring->next_to_use)
297 next_desc = " NTU";
298 else if (i == tx_ring->next_to_clean)
299 next_desc = " NTC";
300 else
301 next_desc = "";
302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
305 i,
306 (unsigned long long)le64_to_cpu(u0->a),
307 (unsigned long long)le64_to_cpu(u0->b),
308 (unsigned long long)buffer_info->dma,
309 buffer_info->length, buffer_info->next_to_watch,
310 (unsigned long long)buffer_info->time_stamp,
311 buffer_info->skb, next_desc);
312
313 if (netif_msg_pktdata(adapter) && buffer_info->skb)
314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
315 16, 1, buffer_info->skb->data,
316 buffer_info->skb->len, true);
317 }
318
319
320rx_ring_summary:
321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
322 pr_info("Queue [NTU] [NTC]\n");
323 pr_info(" %5d %5X %5X\n",
324 0, rx_ring->next_to_use, rx_ring->next_to_clean);
325
326
327 if (!netif_msg_rx_status(adapter))
328 return;
329
330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
331 switch (adapter->rx_ps_pages) {
332 case 1:
333 case 2:
334 case 3:
335
336
337
338
339
340
341
342
343
344
345
346
347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
348
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357
358
359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 for (i = 0; i < rx_ring->count; i++) {
361 const char *next_desc;
362 buffer_info = &rx_ring->buffer_info[i];
363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
364 u1 = (struct my_u1 *)rx_desc_ps;
365 staterr =
366 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
367
368 if (i == rx_ring->next_to_use)
369 next_desc = " NTU";
370 else if (i == rx_ring->next_to_clean)
371 next_desc = " NTC";
372 else
373 next_desc = "";
374
375 if (staterr & E1000_RXD_STAT_DD) {
376
377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
378 "RWB", i,
379 (unsigned long long)le64_to_cpu(u1->a),
380 (unsigned long long)le64_to_cpu(u1->b),
381 (unsigned long long)le64_to_cpu(u1->c),
382 (unsigned long long)le64_to_cpu(u1->d),
383 buffer_info->skb, next_desc);
384 } else {
385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
386 "R ", i,
387 (unsigned long long)le64_to_cpu(u1->a),
388 (unsigned long long)le64_to_cpu(u1->b),
389 (unsigned long long)le64_to_cpu(u1->c),
390 (unsigned long long)le64_to_cpu(u1->d),
391 (unsigned long long)buffer_info->dma,
392 buffer_info->skb, next_desc);
393
394 if (netif_msg_pktdata(adapter))
395 e1000e_dump_ps_pages(adapter,
396 buffer_info);
397 }
398 }
399 break;
400 default:
401 case 0:
402
403
404
405
406
407
408
409
410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
411
412
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417
418
419
420
421
422
423
424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
425
426 for (i = 0; i < rx_ring->count; i++) {
427 const char *next_desc;
428
429 buffer_info = &rx_ring->buffer_info[i];
430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
431 u1 = (struct my_u1 *)rx_desc;
432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
433
434 if (i == rx_ring->next_to_use)
435 next_desc = " NTU";
436 else if (i == rx_ring->next_to_clean)
437 next_desc = " NTC";
438 else
439 next_desc = "";
440
441 if (staterr & E1000_RXD_STAT_DD) {
442
443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
444 "RWB", i,
445 (unsigned long long)le64_to_cpu(u1->a),
446 (unsigned long long)le64_to_cpu(u1->b),
447 buffer_info->skb, next_desc);
448 } else {
449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
450 "R ", i,
451 (unsigned long long)le64_to_cpu(u1->a),
452 (unsigned long long)le64_to_cpu(u1->b),
453 (unsigned long long)buffer_info->dma,
454 buffer_info->skb, next_desc);
455
456 if (netif_msg_pktdata(adapter) &&
457 buffer_info->skb)
458 print_hex_dump(KERN_INFO, "",
459 DUMP_PREFIX_ADDRESS, 16,
460 1,
461 buffer_info->skb->data,
462 adapter->rx_buffer_len,
463 true);
464 }
465 }
466 }
467}
468
469
470
471
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509
510
511
512
513
514
515
516
517
518
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530
531
532
533
534
535
536
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544
545
546
547
548
549
550
551static void e1000_receive_skb(struct e1000_adapter *adapter,
552 struct net_device *netdev, struct sk_buff *skb,
553 u32 staterr, __le16 vlan)
554{
555 u16 tag = le16_to_cpu(vlan);
556
557 e1000e_rx_hwtstamp(adapter, staterr, skb);
558
559 skb->protocol = eth_type_trans(skb, netdev);
560
561 if (staterr & E1000_RXD_STAT_VP)
562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
563
564 napi_gro_receive(&adapter->napi, skb);
565}
566
567
568
569
570
571
572
573
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592
593 adapter->hw_csum_err++;
594 return;
595 }
596
597
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610 s32 ret_val = __ew32_prepare(hw);
611
612 writel(i, rx_ring->tail);
613
614 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, tx_ring->tail);
630
631 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640
641
642
643
644static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
645 int cleaned_count, gfp_t gfp)
646{
647 struct e1000_adapter *adapter = rx_ring->adapter;
648 struct net_device *netdev = adapter->netdev;
649 struct pci_dev *pdev = adapter->pdev;
650 union e1000_rx_desc_extended *rx_desc;
651 struct e1000_buffer *buffer_info;
652 struct sk_buff *skb;
653 unsigned int i;
654 unsigned int bufsz = adapter->rx_buffer_len;
655
656 i = rx_ring->next_to_use;
657 buffer_info = &rx_ring->buffer_info[i];
658
659 while (cleaned_count--) {
660 skb = buffer_info->skb;
661 if (skb) {
662 skb_trim(skb, 0);
663 goto map_skb;
664 }
665
666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
667 if (!skb) {
668
669 adapter->alloc_rx_buff_failed++;
670 break;
671 }
672
673 buffer_info->skb = skb;
674map_skb:
675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
676 adapter->rx_buffer_len,
677 DMA_FROM_DEVICE);
678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
679 dev_err(&pdev->dev, "Rx DMA map failed\n");
680 adapter->rx_dma_failed++;
681 break;
682 }
683
684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
686
687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
688
689
690
691
692
693 wmb();
694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
695 e1000e_update_rdt_wa(rx_ring, i);
696 else
697 writel(i, rx_ring->tail);
698 }
699 i++;
700 if (i == rx_ring->count)
701 i = 0;
702 buffer_info = &rx_ring->buffer_info[i];
703 }
704
705 rx_ring->next_to_use = i;
706}
707
708
709
710
711
712static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
713 int cleaned_count, gfp_t gfp)
714{
715 struct e1000_adapter *adapter = rx_ring->adapter;
716 struct net_device *netdev = adapter->netdev;
717 struct pci_dev *pdev = adapter->pdev;
718 union e1000_rx_desc_packet_split *rx_desc;
719 struct e1000_buffer *buffer_info;
720 struct e1000_ps_page *ps_page;
721 struct sk_buff *skb;
722 unsigned int i, j;
723
724 i = rx_ring->next_to_use;
725 buffer_info = &rx_ring->buffer_info[i];
726
727 while (cleaned_count--) {
728 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
729
730 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
731 ps_page = &buffer_info->ps_pages[j];
732 if (j >= adapter->rx_ps_pages) {
733
734 rx_desc->read.buffer_addr[j + 1] =
735 ~cpu_to_le64(0);
736 continue;
737 }
738 if (!ps_page->page) {
739 ps_page->page = alloc_page(gfp);
740 if (!ps_page->page) {
741 adapter->alloc_rx_buff_failed++;
742 goto no_buffers;
743 }
744 ps_page->dma = dma_map_page(&pdev->dev,
745 ps_page->page,
746 0, PAGE_SIZE,
747 DMA_FROM_DEVICE);
748 if (dma_mapping_error(&pdev->dev,
749 ps_page->dma)) {
750 dev_err(&adapter->pdev->dev,
751 "Rx DMA page map failed\n");
752 adapter->rx_dma_failed++;
753 goto no_buffers;
754 }
755 }
756
757
758
759
760 rx_desc->read.buffer_addr[j + 1] =
761 cpu_to_le64(ps_page->dma);
762 }
763
764 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
765 gfp);
766
767 if (!skb) {
768 adapter->alloc_rx_buff_failed++;
769 break;
770 }
771
772 buffer_info->skb = skb;
773 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
774 adapter->rx_ps_bsize0,
775 DMA_FROM_DEVICE);
776 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
777 dev_err(&pdev->dev, "Rx DMA map failed\n");
778 adapter->rx_dma_failed++;
779
780 dev_kfree_skb_any(skb);
781 buffer_info->skb = NULL;
782 break;
783 }
784
785 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
786
787 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
788
789
790
791
792
793 wmb();
794 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
795 e1000e_update_rdt_wa(rx_ring, i << 1);
796 else
797 writel(i << 1, rx_ring->tail);
798 }
799
800 i++;
801 if (i == rx_ring->count)
802 i = 0;
803 buffer_info = &rx_ring->buffer_info[i];
804 }
805
806no_buffers:
807 rx_ring->next_to_use = i;
808}
809
810
811
812
813
814
815
816static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
817 int cleaned_count, gfp_t gfp)
818{
819 struct e1000_adapter *adapter = rx_ring->adapter;
820 struct net_device *netdev = adapter->netdev;
821 struct pci_dev *pdev = adapter->pdev;
822 union e1000_rx_desc_extended *rx_desc;
823 struct e1000_buffer *buffer_info;
824 struct sk_buff *skb;
825 unsigned int i;
826 unsigned int bufsz = 256 - 16;
827
828 i = rx_ring->next_to_use;
829 buffer_info = &rx_ring->buffer_info[i];
830
831 while (cleaned_count--) {
832 skb = buffer_info->skb;
833 if (skb) {
834 skb_trim(skb, 0);
835 goto check_page;
836 }
837
838 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
839 if (unlikely(!skb)) {
840
841 adapter->alloc_rx_buff_failed++;
842 break;
843 }
844
845 buffer_info->skb = skb;
846check_page:
847
848 if (!buffer_info->page) {
849 buffer_info->page = alloc_page(gfp);
850 if (unlikely(!buffer_info->page)) {
851 adapter->alloc_rx_buff_failed++;
852 break;
853 }
854 }
855
856 if (!buffer_info->dma) {
857 buffer_info->dma = dma_map_page(&pdev->dev,
858 buffer_info->page, 0,
859 PAGE_SIZE,
860 DMA_FROM_DEVICE);
861 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
862 adapter->alloc_rx_buff_failed++;
863 break;
864 }
865 }
866
867 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
868 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
869
870 if (unlikely(++i == rx_ring->count))
871 i = 0;
872 buffer_info = &rx_ring->buffer_info[i];
873 }
874
875 if (likely(rx_ring->next_to_use != i)) {
876 rx_ring->next_to_use = i;
877 if (unlikely(i-- == 0))
878 i = (rx_ring->count - 1);
879
880
881
882
883
884
885 wmb();
886 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
887 e1000e_update_rdt_wa(rx_ring, i);
888 else
889 writel(i, rx_ring->tail);
890 }
891}
892
893static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
894 struct sk_buff *skb)
895{
896 if (netdev->features & NETIF_F_RXHASH)
897 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
898}
899
900
901
902
903
904
905
906
907static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
908 int work_to_do)
909{
910 struct e1000_adapter *adapter = rx_ring->adapter;
911 struct net_device *netdev = adapter->netdev;
912 struct pci_dev *pdev = adapter->pdev;
913 struct e1000_hw *hw = &adapter->hw;
914 union e1000_rx_desc_extended *rx_desc, *next_rxd;
915 struct e1000_buffer *buffer_info, *next_buffer;
916 u32 length, staterr;
917 unsigned int i;
918 int cleaned_count = 0;
919 bool cleaned = false;
920 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
921
922 i = rx_ring->next_to_clean;
923 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
925 buffer_info = &rx_ring->buffer_info[i];
926
927 while (staterr & E1000_RXD_STAT_DD) {
928 struct sk_buff *skb;
929
930 if (*work_done >= work_to_do)
931 break;
932 (*work_done)++;
933 dma_rmb();
934
935 skb = buffer_info->skb;
936 buffer_info->skb = NULL;
937
938 prefetch(skb->data - NET_IP_ALIGN);
939
940 i++;
941 if (i == rx_ring->count)
942 i = 0;
943 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
944 prefetch(next_rxd);
945
946 next_buffer = &rx_ring->buffer_info[i];
947
948 cleaned = true;
949 cleaned_count++;
950 dma_unmap_single(&pdev->dev, buffer_info->dma,
951 adapter->rx_buffer_len, DMA_FROM_DEVICE);
952 buffer_info->dma = 0;
953
954 length = le16_to_cpu(rx_desc->wb.upper.length);
955
956
957
958
959
960
961
962 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
963 adapter->flags2 |= FLAG2_IS_DISCARDING;
964
965 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
966
967 e_dbg("Receive packet consumed multiple buffers\n");
968
969 buffer_info->skb = skb;
970 if (staterr & E1000_RXD_STAT_EOP)
971 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
972 goto next_desc;
973 }
974
975 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
976 !(netdev->features & NETIF_F_RXALL))) {
977
978 buffer_info->skb = skb;
979 goto next_desc;
980 }
981
982
983 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
984
985
986
987
988 if (netdev->features & NETIF_F_RXFCS)
989 total_rx_bytes -= 4;
990 else
991 length -= 4;
992 }
993
994 total_rx_bytes += length;
995 total_rx_packets++;
996
997
998
999
1000
1001 if (length < copybreak) {
1002 struct sk_buff *new_skb =
1003 napi_alloc_skb(&adapter->napi, length);
1004 if (new_skb) {
1005 skb_copy_to_linear_data_offset(new_skb,
1006 -NET_IP_ALIGN,
1007 (skb->data -
1008 NET_IP_ALIGN),
1009 (length +
1010 NET_IP_ALIGN));
1011
1012 buffer_info->skb = skb;
1013 skb = new_skb;
1014 }
1015
1016 }
1017
1018 skb_put(skb, length);
1019
1020
1021 e1000_rx_checksum(adapter, staterr, skb);
1022
1023 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1024
1025 e1000_receive_skb(adapter, netdev, skb, staterr,
1026 rx_desc->wb.upper.vlan);
1027
1028next_desc:
1029 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1030
1031
1032 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1033 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1034 GFP_ATOMIC);
1035 cleaned_count = 0;
1036 }
1037
1038
1039 rx_desc = next_rxd;
1040 buffer_info = next_buffer;
1041
1042 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1043 }
1044 rx_ring->next_to_clean = i;
1045
1046 cleaned_count = e1000_desc_unused(rx_ring);
1047 if (cleaned_count)
1048 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1049
1050 adapter->total_rx_bytes += total_rx_bytes;
1051 adapter->total_rx_packets += total_rx_packets;
1052 return cleaned;
1053}
1054
1055static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1056 struct e1000_buffer *buffer_info,
1057 bool drop)
1058{
1059 struct e1000_adapter *adapter = tx_ring->adapter;
1060
1061 if (buffer_info->dma) {
1062 if (buffer_info->mapped_as_page)
1063 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1064 buffer_info->length, DMA_TO_DEVICE);
1065 else
1066 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1067 buffer_info->length, DMA_TO_DEVICE);
1068 buffer_info->dma = 0;
1069 }
1070 if (buffer_info->skb) {
1071 if (drop)
1072 dev_kfree_skb_any(buffer_info->skb);
1073 else
1074 dev_consume_skb_any(buffer_info->skb);
1075 buffer_info->skb = NULL;
1076 }
1077 buffer_info->time_stamp = 0;
1078}
1079
1080static void e1000_print_hw_hang(struct work_struct *work)
1081{
1082 struct e1000_adapter *adapter = container_of(work,
1083 struct e1000_adapter,
1084 print_hang_task);
1085 struct net_device *netdev = adapter->netdev;
1086 struct e1000_ring *tx_ring = adapter->tx_ring;
1087 unsigned int i = tx_ring->next_to_clean;
1088 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1089 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1090 struct e1000_hw *hw = &adapter->hw;
1091 u16 phy_status, phy_1000t_status, phy_ext_status;
1092 u16 pci_status;
1093
1094 if (test_bit(__E1000_DOWN, &adapter->state))
1095 return;
1096
1097 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1098
1099
1100
1101 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1102
1103 e1e_flush();
1104
1105
1106
1107 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1108
1109 e1e_flush();
1110 adapter->tx_hang_recheck = true;
1111 return;
1112 }
1113 adapter->tx_hang_recheck = false;
1114
1115 if (er32(TDH(0)) == er32(TDT(0))) {
1116 e_dbg("false hang detected, ignoring\n");
1117 return;
1118 }
1119
1120
1121 netif_stop_queue(netdev);
1122
1123 e1e_rphy(hw, MII_BMSR, &phy_status);
1124 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1125 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1126
1127 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1128
1129
1130 e_err("Detected Hardware Unit Hang:\n"
1131 " TDH <%x>\n"
1132 " TDT <%x>\n"
1133 " next_to_use <%x>\n"
1134 " next_to_clean <%x>\n"
1135 "buffer_info[next_to_clean]:\n"
1136 " time_stamp <%lx>\n"
1137 " next_to_watch <%x>\n"
1138 " jiffies <%lx>\n"
1139 " next_to_watch.status <%x>\n"
1140 "MAC Status <%x>\n"
1141 "PHY Status <%x>\n"
1142 "PHY 1000BASE-T Status <%x>\n"
1143 "PHY Extended Status <%x>\n"
1144 "PCI Status <%x>\n",
1145 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1146 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1147 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1148 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1149
1150 e1000e_dump(adapter);
1151
1152
1153 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1154 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1155}
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1166{
1167 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1168 tx_hwtstamp_work);
1169 struct e1000_hw *hw = &adapter->hw;
1170
1171 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1172 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1173 struct skb_shared_hwtstamps shhwtstamps;
1174 u64 txstmp;
1175
1176 txstmp = er32(TXSTMPL);
1177 txstmp |= (u64)er32(TXSTMPH) << 32;
1178
1179 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1180
1181
1182
1183
1184 adapter->tx_hwtstamp_skb = NULL;
1185 wmb();
1186
1187 skb_tstamp_tx(skb, &shhwtstamps);
1188 dev_consume_skb_any(skb);
1189 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1190 + adapter->tx_timeout_factor * HZ)) {
1191 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1192 adapter->tx_hwtstamp_skb = NULL;
1193 adapter->tx_hwtstamp_timeouts++;
1194 e_warn("clearing Tx timestamp hang\n");
1195 } else {
1196
1197 schedule_work(&adapter->tx_hwtstamp_work);
1198 }
1199}
1200
1201
1202
1203
1204
1205
1206
1207
1208static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1209{
1210 struct e1000_adapter *adapter = tx_ring->adapter;
1211 struct net_device *netdev = adapter->netdev;
1212 struct e1000_hw *hw = &adapter->hw;
1213 struct e1000_tx_desc *tx_desc, *eop_desc;
1214 struct e1000_buffer *buffer_info;
1215 unsigned int i, eop;
1216 unsigned int count = 0;
1217 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1218 unsigned int bytes_compl = 0, pkts_compl = 0;
1219
1220 i = tx_ring->next_to_clean;
1221 eop = tx_ring->buffer_info[i].next_to_watch;
1222 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1223
1224 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1225 (count < tx_ring->count)) {
1226 bool cleaned = false;
1227
1228 dma_rmb();
1229 for (; !cleaned; count++) {
1230 tx_desc = E1000_TX_DESC(*tx_ring, i);
1231 buffer_info = &tx_ring->buffer_info[i];
1232 cleaned = (i == eop);
1233
1234 if (cleaned) {
1235 total_tx_packets += buffer_info->segs;
1236 total_tx_bytes += buffer_info->bytecount;
1237 if (buffer_info->skb) {
1238 bytes_compl += buffer_info->skb->len;
1239 pkts_compl++;
1240 }
1241 }
1242
1243 e1000_put_txbuf(tx_ring, buffer_info, false);
1244 tx_desc->upper.data = 0;
1245
1246 i++;
1247 if (i == tx_ring->count)
1248 i = 0;
1249 }
1250
1251 if (i == tx_ring->next_to_use)
1252 break;
1253 eop = tx_ring->buffer_info[i].next_to_watch;
1254 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1255 }
1256
1257 tx_ring->next_to_clean = i;
1258
1259 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1260
1261#define TX_WAKE_THRESHOLD 32
1262 if (count && netif_carrier_ok(netdev) &&
1263 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1264
1265
1266
1267 smp_mb();
1268
1269 if (netif_queue_stopped(netdev) &&
1270 !(test_bit(__E1000_DOWN, &adapter->state))) {
1271 netif_wake_queue(netdev);
1272 ++adapter->restart_queue;
1273 }
1274 }
1275
1276 if (adapter->detect_tx_hung) {
1277
1278
1279
1280 adapter->detect_tx_hung = false;
1281 if (tx_ring->buffer_info[i].time_stamp &&
1282 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1283 + (adapter->tx_timeout_factor * HZ)) &&
1284 !(er32(STATUS) & E1000_STATUS_TXOFF))
1285 schedule_work(&adapter->print_hang_task);
1286 else
1287 adapter->tx_hang_recheck = false;
1288 }
1289 adapter->total_tx_bytes += total_tx_bytes;
1290 adapter->total_tx_packets += total_tx_packets;
1291 return count < tx_ring->count;
1292}
1293
1294
1295
1296
1297
1298
1299
1300
1301static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1302 int work_to_do)
1303{
1304 struct e1000_adapter *adapter = rx_ring->adapter;
1305 struct e1000_hw *hw = &adapter->hw;
1306 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1307 struct net_device *netdev = adapter->netdev;
1308 struct pci_dev *pdev = adapter->pdev;
1309 struct e1000_buffer *buffer_info, *next_buffer;
1310 struct e1000_ps_page *ps_page;
1311 struct sk_buff *skb;
1312 unsigned int i, j;
1313 u32 length, staterr;
1314 int cleaned_count = 0;
1315 bool cleaned = false;
1316 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1317
1318 i = rx_ring->next_to_clean;
1319 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1320 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1321 buffer_info = &rx_ring->buffer_info[i];
1322
1323 while (staterr & E1000_RXD_STAT_DD) {
1324 if (*work_done >= work_to_do)
1325 break;
1326 (*work_done)++;
1327 skb = buffer_info->skb;
1328 dma_rmb();
1329
1330
1331 prefetch(skb->data - NET_IP_ALIGN);
1332
1333 i++;
1334 if (i == rx_ring->count)
1335 i = 0;
1336 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1337 prefetch(next_rxd);
1338
1339 next_buffer = &rx_ring->buffer_info[i];
1340
1341 cleaned = true;
1342 cleaned_count++;
1343 dma_unmap_single(&pdev->dev, buffer_info->dma,
1344 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1345 buffer_info->dma = 0;
1346
1347
1348 if (!(staterr & E1000_RXD_STAT_EOP))
1349 adapter->flags2 |= FLAG2_IS_DISCARDING;
1350
1351 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1352 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1353 dev_kfree_skb_irq(skb);
1354 if (staterr & E1000_RXD_STAT_EOP)
1355 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1356 goto next_desc;
1357 }
1358
1359 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1360 !(netdev->features & NETIF_F_RXALL))) {
1361 dev_kfree_skb_irq(skb);
1362 goto next_desc;
1363 }
1364
1365 length = le16_to_cpu(rx_desc->wb.middle.length0);
1366
1367 if (!length) {
1368 e_dbg("Last part of the packet spanning multiple descriptors\n");
1369 dev_kfree_skb_irq(skb);
1370 goto next_desc;
1371 }
1372
1373
1374 skb_put(skb, length);
1375
1376 {
1377
1378
1379
1380 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1381
1382
1383
1384
1385
1386
1387 if (l1 && (l1 <= copybreak) &&
1388 ((length + l1) <= adapter->rx_ps_bsize0)) {
1389 u8 *vaddr;
1390
1391 ps_page = &buffer_info->ps_pages[0];
1392
1393
1394
1395
1396
1397 dma_sync_single_for_cpu(&pdev->dev,
1398 ps_page->dma,
1399 PAGE_SIZE,
1400 DMA_FROM_DEVICE);
1401 vaddr = kmap_atomic(ps_page->page);
1402 memcpy(skb_tail_pointer(skb), vaddr, l1);
1403 kunmap_atomic(vaddr);
1404 dma_sync_single_for_device(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1408
1409
1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 if (!(netdev->features & NETIF_F_RXFCS))
1412 l1 -= 4;
1413 }
1414
1415 skb_put(skb, l1);
1416 goto copydone;
1417 }
1418 }
1419
1420 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1421 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1422 if (!length)
1423 break;
1424
1425 ps_page = &buffer_info->ps_pages[j];
1426 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1427 DMA_FROM_DEVICE);
1428 ps_page->dma = 0;
1429 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1430 ps_page->page = NULL;
1431 skb->len += length;
1432 skb->data_len += length;
1433 skb->truesize += PAGE_SIZE;
1434 }
1435
1436
1437
1438
1439 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1440 if (!(netdev->features & NETIF_F_RXFCS))
1441 pskb_trim(skb, skb->len - 4);
1442 }
1443
1444copydone:
1445 total_rx_bytes += skb->len;
1446 total_rx_packets++;
1447
1448 e1000_rx_checksum(adapter, staterr, skb);
1449
1450 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1451
1452 if (rx_desc->wb.upper.header_status &
1453 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1454 adapter->rx_hdr_split++;
1455
1456 e1000_receive_skb(adapter, netdev, skb, staterr,
1457 rx_desc->wb.middle.vlan);
1458
1459next_desc:
1460 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1461 buffer_info->skb = NULL;
1462
1463
1464 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1465 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1466 GFP_ATOMIC);
1467 cleaned_count = 0;
1468 }
1469
1470
1471 rx_desc = next_rxd;
1472 buffer_info = next_buffer;
1473
1474 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1475 }
1476 rx_ring->next_to_clean = i;
1477
1478 cleaned_count = e1000_desc_unused(rx_ring);
1479 if (cleaned_count)
1480 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1481
1482 adapter->total_rx_bytes += total_rx_bytes;
1483 adapter->total_rx_packets += total_rx_packets;
1484 return cleaned;
1485}
1486
1487
1488
1489
1490static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1491 u16 length)
1492{
1493 bi->page = NULL;
1494 skb->len += length;
1495 skb->data_len += length;
1496 skb->truesize += PAGE_SIZE;
1497}
1498
1499
1500
1501
1502
1503
1504
1505
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb();
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557
1558 buffer_info->skb = skb;
1559
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567
1568 if (!rxtop) {
1569
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591
1592
1593
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599
1600
1601
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 u8 *vaddr;
1605 vaddr = kmap_atomic(buffer_info->page);
1606 memcpy(skb_tail_pointer(skb), vaddr,
1607 length);
1608 kunmap_atomic(vaddr);
1609
1610
1611
1612 skb_put(skb, length);
1613 } else {
1614 skb_fill_page_desc(skb, 0,
1615 buffer_info->page, 0,
1616 length);
1617 e1000_consume_page(buffer_info, skb,
1618 length);
1619 }
1620 }
1621 }
1622
1623
1624 e1000_rx_checksum(adapter, staterr, skb);
1625
1626 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1627
1628
1629 total_rx_bytes += skb->len;
1630 total_rx_packets++;
1631
1632
1633 if (!pskb_may_pull(skb, ETH_HLEN)) {
1634 e_err("pskb_may_pull failed.\n");
1635 dev_kfree_skb_irq(skb);
1636 goto next_desc;
1637 }
1638
1639 e1000_receive_skb(adapter, netdev, skb, staterr,
1640 rx_desc->wb.upper.vlan);
1641
1642next_desc:
1643 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1644
1645
1646 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1647 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1648 GFP_ATOMIC);
1649 cleaned_count = 0;
1650 }
1651
1652
1653 rx_desc = next_rxd;
1654 buffer_info = next_buffer;
1655
1656 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1657 }
1658 rx_ring->next_to_clean = i;
1659
1660 cleaned_count = e1000_desc_unused(rx_ring);
1661 if (cleaned_count)
1662 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1663
1664 adapter->total_rx_bytes += total_rx_bytes;
1665 adapter->total_rx_packets += total_rx_packets;
1666 return cleaned;
1667}
1668
1669
1670
1671
1672
1673static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1674{
1675 struct e1000_adapter *adapter = rx_ring->adapter;
1676 struct e1000_buffer *buffer_info;
1677 struct e1000_ps_page *ps_page;
1678 struct pci_dev *pdev = adapter->pdev;
1679 unsigned int i, j;
1680
1681
1682 for (i = 0; i < rx_ring->count; i++) {
1683 buffer_info = &rx_ring->buffer_info[i];
1684 if (buffer_info->dma) {
1685 if (adapter->clean_rx == e1000_clean_rx_irq)
1686 dma_unmap_single(&pdev->dev, buffer_info->dma,
1687 adapter->rx_buffer_len,
1688 DMA_FROM_DEVICE);
1689 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1690 dma_unmap_page(&pdev->dev, buffer_info->dma,
1691 PAGE_SIZE, DMA_FROM_DEVICE);
1692 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 adapter->rx_ps_bsize0,
1695 DMA_FROM_DEVICE);
1696 buffer_info->dma = 0;
1697 }
1698
1699 if (buffer_info->page) {
1700 put_page(buffer_info->page);
1701 buffer_info->page = NULL;
1702 }
1703
1704 if (buffer_info->skb) {
1705 dev_kfree_skb(buffer_info->skb);
1706 buffer_info->skb = NULL;
1707 }
1708
1709 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1710 ps_page = &buffer_info->ps_pages[j];
1711 if (!ps_page->page)
1712 break;
1713 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1714 DMA_FROM_DEVICE);
1715 ps_page->dma = 0;
1716 put_page(ps_page->page);
1717 ps_page->page = NULL;
1718 }
1719 }
1720
1721
1722 if (rx_ring->rx_skb_top) {
1723 dev_kfree_skb(rx_ring->rx_skb_top);
1724 rx_ring->rx_skb_top = NULL;
1725 }
1726
1727
1728 memset(rx_ring->desc, 0, rx_ring->size);
1729
1730 rx_ring->next_to_clean = 0;
1731 rx_ring->next_to_use = 0;
1732 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1733}
1734
1735static void e1000e_downshift_workaround(struct work_struct *work)
1736{
1737 struct e1000_adapter *adapter = container_of(work,
1738 struct e1000_adapter,
1739 downshift_task);
1740
1741 if (test_bit(__E1000_DOWN, &adapter->state))
1742 return;
1743
1744 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1745}
1746
1747
1748
1749
1750
1751
1752static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1753{
1754 struct net_device *netdev = data;
1755 struct e1000_adapter *adapter = netdev_priv(netdev);
1756 struct e1000_hw *hw = &adapter->hw;
1757 u32 icr = er32(ICR);
1758
1759
1760 if (icr & E1000_ICR_LSC) {
1761 hw->mac.get_link_status = true;
1762
1763
1764
1765 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1766 (!(er32(STATUS) & E1000_STATUS_LU)))
1767 schedule_work(&adapter->downshift_task);
1768
1769
1770
1771
1772
1773 if (netif_carrier_ok(netdev) &&
1774 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1775
1776 u32 rctl = er32(RCTL);
1777
1778 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1779 adapter->flags |= FLAG_RESTART_NOW;
1780 }
1781
1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1784 }
1785
1786
1787 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1788 u32 pbeccsts = er32(PBECCSTS);
1789
1790 adapter->corr_errors +=
1791 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1792 adapter->uncorr_errors +=
1793 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1794 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1795
1796
1797 schedule_work(&adapter->reset_task);
1798
1799
1800 return IRQ_HANDLED;
1801 }
1802
1803 if (napi_schedule_prep(&adapter->napi)) {
1804 adapter->total_tx_bytes = 0;
1805 adapter->total_tx_packets = 0;
1806 adapter->total_rx_bytes = 0;
1807 adapter->total_rx_packets = 0;
1808 __napi_schedule(&adapter->napi);
1809 }
1810
1811 return IRQ_HANDLED;
1812}
1813
1814
1815
1816
1817
1818
1819static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1820{
1821 struct net_device *netdev = data;
1822 struct e1000_adapter *adapter = netdev_priv(netdev);
1823 struct e1000_hw *hw = &adapter->hw;
1824 u32 rctl, icr = er32(ICR);
1825
1826 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1827 return IRQ_NONE;
1828
1829
1830
1831
1832 if (!(icr & E1000_ICR_INT_ASSERTED))
1833 return IRQ_NONE;
1834
1835
1836
1837
1838
1839
1840 if (icr & E1000_ICR_LSC) {
1841 hw->mac.get_link_status = true;
1842
1843
1844
1845 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1846 (!(er32(STATUS) & E1000_STATUS_LU)))
1847 schedule_work(&adapter->downshift_task);
1848
1849
1850
1851
1852
1853
1854 if (netif_carrier_ok(netdev) &&
1855 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1856
1857 rctl = er32(RCTL);
1858 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1859 adapter->flags |= FLAG_RESTART_NOW;
1860 }
1861
1862 if (!test_bit(__E1000_DOWN, &adapter->state))
1863 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1864 }
1865
1866
1867 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1868 u32 pbeccsts = er32(PBECCSTS);
1869
1870 adapter->corr_errors +=
1871 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1872 adapter->uncorr_errors +=
1873 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1874 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1875
1876
1877 schedule_work(&adapter->reset_task);
1878
1879
1880 return IRQ_HANDLED;
1881 }
1882
1883 if (napi_schedule_prep(&adapter->napi)) {
1884 adapter->total_tx_bytes = 0;
1885 adapter->total_tx_packets = 0;
1886 adapter->total_rx_bytes = 0;
1887 adapter->total_rx_packets = 0;
1888 __napi_schedule(&adapter->napi);
1889 }
1890
1891 return IRQ_HANDLED;
1892}
1893
1894static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1895{
1896 struct net_device *netdev = data;
1897 struct e1000_adapter *adapter = netdev_priv(netdev);
1898 struct e1000_hw *hw = &adapter->hw;
1899 u32 icr = er32(ICR);
1900
1901 if (icr & adapter->eiac_mask)
1902 ew32(ICS, (icr & adapter->eiac_mask));
1903
1904 if (icr & E1000_ICR_LSC) {
1905 hw->mac.get_link_status = true;
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1909 }
1910
1911 if (!test_bit(__E1000_DOWN, &adapter->state))
1912 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1913
1914 return IRQ_HANDLED;
1915}
1916
1917static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1918{
1919 struct net_device *netdev = data;
1920 struct e1000_adapter *adapter = netdev_priv(netdev);
1921 struct e1000_hw *hw = &adapter->hw;
1922 struct e1000_ring *tx_ring = adapter->tx_ring;
1923
1924 adapter->total_tx_bytes = 0;
1925 adapter->total_tx_packets = 0;
1926
1927 if (!e1000_clean_tx_irq(tx_ring))
1928
1929 ew32(ICS, tx_ring->ims_val);
1930
1931 if (!test_bit(__E1000_DOWN, &adapter->state))
1932 ew32(IMS, adapter->tx_ring->ims_val);
1933
1934 return IRQ_HANDLED;
1935}
1936
1937static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1938{
1939 struct net_device *netdev = data;
1940 struct e1000_adapter *adapter = netdev_priv(netdev);
1941 struct e1000_ring *rx_ring = adapter->rx_ring;
1942
1943
1944
1945
1946 if (rx_ring->set_itr) {
1947 u32 itr = rx_ring->itr_val ?
1948 1000000000 / (rx_ring->itr_val * 256) : 0;
1949
1950 writel(itr, rx_ring->itr_register);
1951 rx_ring->set_itr = 0;
1952 }
1953
1954 if (napi_schedule_prep(&adapter->napi)) {
1955 adapter->total_rx_bytes = 0;
1956 adapter->total_rx_packets = 0;
1957 __napi_schedule(&adapter->napi);
1958 }
1959 return IRQ_HANDLED;
1960}
1961
1962
1963
1964
1965
1966
1967
1968static void e1000_configure_msix(struct e1000_adapter *adapter)
1969{
1970 struct e1000_hw *hw = &adapter->hw;
1971 struct e1000_ring *rx_ring = adapter->rx_ring;
1972 struct e1000_ring *tx_ring = adapter->tx_ring;
1973 int vector = 0;
1974 u32 ctrl_ext, ivar = 0;
1975
1976 adapter->eiac_mask = 0;
1977
1978
1979 if (hw->mac.type == e1000_82574) {
1980 u32 rfctl = er32(RFCTL);
1981
1982 rfctl |= E1000_RFCTL_ACK_DIS;
1983 ew32(RFCTL, rfctl);
1984 }
1985
1986
1987 rx_ring->ims_val = E1000_IMS_RXQ0;
1988 adapter->eiac_mask |= rx_ring->ims_val;
1989 if (rx_ring->itr_val)
1990 writel(1000000000 / (rx_ring->itr_val * 256),
1991 rx_ring->itr_register);
1992 else
1993 writel(1, rx_ring->itr_register);
1994 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1995
1996
1997 tx_ring->ims_val = E1000_IMS_TXQ0;
1998 vector++;
1999 if (tx_ring->itr_val)
2000 writel(1000000000 / (tx_ring->itr_val * 256),
2001 tx_ring->itr_register);
2002 else
2003 writel(1, tx_ring->itr_register);
2004 adapter->eiac_mask |= tx_ring->ims_val;
2005 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2006
2007
2008 vector++;
2009 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2010 if (rx_ring->itr_val)
2011 writel(1000000000 / (rx_ring->itr_val * 256),
2012 hw->hw_addr + E1000_EITR_82574(vector));
2013 else
2014 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2015
2016
2017 ivar |= BIT(31);
2018
2019 ew32(IVAR, ivar);
2020
2021
2022 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2023 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2024 ew32(CTRL_EXT, ctrl_ext);
2025 e1e_flush();
2026}
2027
2028void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2029{
2030 if (adapter->msix_entries) {
2031 pci_disable_msix(adapter->pdev);
2032 kfree(adapter->msix_entries);
2033 adapter->msix_entries = NULL;
2034 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2035 pci_disable_msi(adapter->pdev);
2036 adapter->flags &= ~FLAG_MSI_ENABLED;
2037 }
2038}
2039
2040
2041
2042
2043
2044
2045
2046void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2047{
2048 int err;
2049 int i;
2050
2051 switch (adapter->int_mode) {
2052 case E1000E_INT_MODE_MSIX:
2053 if (adapter->flags & FLAG_HAS_MSIX) {
2054 adapter->num_vectors = 3;
2055 adapter->msix_entries = kcalloc(adapter->num_vectors,
2056 sizeof(struct
2057 msix_entry),
2058 GFP_KERNEL);
2059 if (adapter->msix_entries) {
2060 struct e1000_adapter *a = adapter;
2061
2062 for (i = 0; i < adapter->num_vectors; i++)
2063 adapter->msix_entries[i].entry = i;
2064
2065 err = pci_enable_msix_range(a->pdev,
2066 a->msix_entries,
2067 a->num_vectors,
2068 a->num_vectors);
2069 if (err > 0)
2070 return;
2071 }
2072
2073 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2074 e1000e_reset_interrupt_capability(adapter);
2075 }
2076 adapter->int_mode = E1000E_INT_MODE_MSI;
2077
2078 case E1000E_INT_MODE_MSI:
2079 if (!pci_enable_msi(adapter->pdev)) {
2080 adapter->flags |= FLAG_MSI_ENABLED;
2081 } else {
2082 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2083 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2084 }
2085
2086 case E1000E_INT_MODE_LEGACY:
2087
2088 break;
2089 }
2090
2091
2092 adapter->num_vectors = 1;
2093}
2094
2095
2096
2097
2098
2099
2100
2101static int e1000_request_msix(struct e1000_adapter *adapter)
2102{
2103 struct net_device *netdev = adapter->netdev;
2104 int err = 0, vector = 0;
2105
2106 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2107 snprintf(adapter->rx_ring->name,
2108 sizeof(adapter->rx_ring->name) - 1,
2109 "%.14s-rx-0", netdev->name);
2110 else
2111 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2112 err = request_irq(adapter->msix_entries[vector].vector,
2113 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2114 netdev);
2115 if (err)
2116 return err;
2117 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2118 E1000_EITR_82574(vector);
2119 adapter->rx_ring->itr_val = adapter->itr;
2120 vector++;
2121
2122 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2123 snprintf(adapter->tx_ring->name,
2124 sizeof(adapter->tx_ring->name) - 1,
2125 "%.14s-tx-0", netdev->name);
2126 else
2127 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2128 err = request_irq(adapter->msix_entries[vector].vector,
2129 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2130 netdev);
2131 if (err)
2132 return err;
2133 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2134 E1000_EITR_82574(vector);
2135 adapter->tx_ring->itr_val = adapter->itr;
2136 vector++;
2137
2138 err = request_irq(adapter->msix_entries[vector].vector,
2139 e1000_msix_other, 0, netdev->name, netdev);
2140 if (err)
2141 return err;
2142
2143 e1000_configure_msix(adapter);
2144
2145 return 0;
2146}
2147
2148
2149
2150
2151
2152
2153
2154static int e1000_request_irq(struct e1000_adapter *adapter)
2155{
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185}
2186
2187static void e1000_free_irq(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206}
2207
2208
2209
2210
2211static void e1000_irq_disable(struct e1000_adapter *adapter)
2212{
2213 struct e1000_hw *hw = &adapter->hw;
2214
2215 ew32(IMC, ~0);
2216 if (adapter->msix_entries)
2217 ew32(EIAC_82574, 0);
2218 e1e_flush();
2219
2220 if (adapter->msix_entries) {
2221 int i;
2222
2223 for (i = 0; i < adapter->num_vectors; i++)
2224 synchronize_irq(adapter->msix_entries[i].vector);
2225 } else {
2226 synchronize_irq(adapter->pdev->irq);
2227 }
2228}
2229
2230
2231
2232
2233static void e1000_irq_enable(struct e1000_adapter *adapter)
2234{
2235 struct e1000_hw *hw = &adapter->hw;
2236
2237 if (adapter->msix_entries) {
2238 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2239 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2240 IMS_OTHER_MASK);
2241 } else if (hw->mac.type >= e1000_pch_lpt) {
2242 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2243 } else {
2244 ew32(IMS, IMS_ENABLE_MASK);
2245 }
2246 e1e_flush();
2247}
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258void e1000e_get_hw_control(struct e1000_adapter *adapter)
2259{
2260 struct e1000_hw *hw = &adapter->hw;
2261 u32 ctrl_ext;
2262 u32 swsm;
2263
2264
2265 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2266 swsm = er32(SWSM);
2267 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2268 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2269 ctrl_ext = er32(CTRL_EXT);
2270 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2271 }
2272}
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284void e1000e_release_hw_control(struct e1000_adapter *adapter)
2285{
2286 struct e1000_hw *hw = &adapter->hw;
2287 u32 ctrl_ext;
2288 u32 swsm;
2289
2290
2291 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2292 swsm = er32(SWSM);
2293 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2294 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2295 ctrl_ext = er32(CTRL_EXT);
2296 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2297 }
2298}
2299
2300
2301
2302
2303static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2304 struct e1000_ring *ring)
2305{
2306 struct pci_dev *pdev = adapter->pdev;
2307
2308 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2309 GFP_KERNEL);
2310 if (!ring->desc)
2311 return -ENOMEM;
2312
2313 return 0;
2314}
2315
2316
2317
2318
2319
2320
2321
2322int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2323{
2324 struct e1000_adapter *adapter = tx_ring->adapter;
2325 int err = -ENOMEM, size;
2326
2327 size = sizeof(struct e1000_buffer) * tx_ring->count;
2328 tx_ring->buffer_info = vzalloc(size);
2329 if (!tx_ring->buffer_info)
2330 goto err;
2331
2332
2333 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2334 tx_ring->size = ALIGN(tx_ring->size, 4096);
2335
2336 err = e1000_alloc_ring_dma(adapter, tx_ring);
2337 if (err)
2338 goto err;
2339
2340 tx_ring->next_to_use = 0;
2341 tx_ring->next_to_clean = 0;
2342
2343 return 0;
2344err:
2345 vfree(tx_ring->buffer_info);
2346 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2347 return err;
2348}
2349
2350
2351
2352
2353
2354
2355
2356int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2357{
2358 struct e1000_adapter *adapter = rx_ring->adapter;
2359 struct e1000_buffer *buffer_info;
2360 int i, size, desc_len, err = -ENOMEM;
2361
2362 size = sizeof(struct e1000_buffer) * rx_ring->count;
2363 rx_ring->buffer_info = vzalloc(size);
2364 if (!rx_ring->buffer_info)
2365 goto err;
2366
2367 for (i = 0; i < rx_ring->count; i++) {
2368 buffer_info = &rx_ring->buffer_info[i];
2369 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2370 sizeof(struct e1000_ps_page),
2371 GFP_KERNEL);
2372 if (!buffer_info->ps_pages)
2373 goto err_pages;
2374 }
2375
2376 desc_len = sizeof(union e1000_rx_desc_packet_split);
2377
2378
2379 rx_ring->size = rx_ring->count * desc_len;
2380 rx_ring->size = ALIGN(rx_ring->size, 4096);
2381
2382 err = e1000_alloc_ring_dma(adapter, rx_ring);
2383 if (err)
2384 goto err_pages;
2385
2386 rx_ring->next_to_clean = 0;
2387 rx_ring->next_to_use = 0;
2388 rx_ring->rx_skb_top = NULL;
2389
2390 return 0;
2391
2392err_pages:
2393 for (i = 0; i < rx_ring->count; i++) {
2394 buffer_info = &rx_ring->buffer_info[i];
2395 kfree(buffer_info->ps_pages);
2396 }
2397err:
2398 vfree(rx_ring->buffer_info);
2399 e_err("Unable to allocate memory for the receive descriptor ring\n");
2400 return err;
2401}
2402
2403
2404
2405
2406
2407static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2408{
2409 struct e1000_adapter *adapter = tx_ring->adapter;
2410 struct e1000_buffer *buffer_info;
2411 unsigned long size;
2412 unsigned int i;
2413
2414 for (i = 0; i < tx_ring->count; i++) {
2415 buffer_info = &tx_ring->buffer_info[i];
2416 e1000_put_txbuf(tx_ring, buffer_info, false);
2417 }
2418
2419 netdev_reset_queue(adapter->netdev);
2420 size = sizeof(struct e1000_buffer) * tx_ring->count;
2421 memset(tx_ring->buffer_info, 0, size);
2422
2423 memset(tx_ring->desc, 0, tx_ring->size);
2424
2425 tx_ring->next_to_use = 0;
2426 tx_ring->next_to_clean = 0;
2427}
2428
2429
2430
2431
2432
2433
2434
2435void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2436{
2437 struct e1000_adapter *adapter = tx_ring->adapter;
2438 struct pci_dev *pdev = adapter->pdev;
2439
2440 e1000_clean_tx_ring(tx_ring);
2441
2442 vfree(tx_ring->buffer_info);
2443 tx_ring->buffer_info = NULL;
2444
2445 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2446 tx_ring->dma);
2447 tx_ring->desc = NULL;
2448}
2449
2450
2451
2452
2453
2454
2455
2456void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2457{
2458 struct e1000_adapter *adapter = rx_ring->adapter;
2459 struct pci_dev *pdev = adapter->pdev;
2460 int i;
2461
2462 e1000_clean_rx_ring(rx_ring);
2463
2464 for (i = 0; i < rx_ring->count; i++)
2465 kfree(rx_ring->buffer_info[i].ps_pages);
2466
2467 vfree(rx_ring->buffer_info);
2468 rx_ring->buffer_info = NULL;
2469
2470 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2471 rx_ring->dma);
2472 rx_ring->desc = NULL;
2473}
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2492{
2493 unsigned int retval = itr_setting;
2494
2495 if (packets == 0)
2496 return itr_setting;
2497
2498 switch (itr_setting) {
2499 case lowest_latency:
2500
2501 if (bytes / packets > 8000)
2502 retval = bulk_latency;
2503 else if ((packets < 5) && (bytes > 512))
2504 retval = low_latency;
2505 break;
2506 case low_latency:
2507 if (bytes > 10000) {
2508
2509 if (bytes / packets > 8000)
2510 retval = bulk_latency;
2511 else if ((packets < 10) || ((bytes / packets) > 1200))
2512 retval = bulk_latency;
2513 else if ((packets > 35))
2514 retval = lowest_latency;
2515 } else if (bytes / packets > 2000) {
2516 retval = bulk_latency;
2517 } else if (packets <= 2 && bytes < 512) {
2518 retval = lowest_latency;
2519 }
2520 break;
2521 case bulk_latency:
2522 if (bytes > 25000) {
2523 if (packets > 35)
2524 retval = low_latency;
2525 } else if (bytes < 6000) {
2526 retval = low_latency;
2527 }
2528 break;
2529 }
2530
2531 return retval;
2532}
2533
2534static void e1000_set_itr(struct e1000_adapter *adapter)
2535{
2536 u16 current_itr;
2537 u32 new_itr = adapter->itr;
2538
2539
2540 if (adapter->link_speed != SPEED_1000) {
2541 current_itr = 0;
2542 new_itr = 4000;
2543 goto set_itr_now;
2544 }
2545
2546 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2547 new_itr = 0;
2548 goto set_itr_now;
2549 }
2550
2551 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2552 adapter->total_tx_packets,
2553 adapter->total_tx_bytes);
2554
2555 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2556 adapter->tx_itr = low_latency;
2557
2558 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2559 adapter->total_rx_packets,
2560 adapter->total_rx_bytes);
2561
2562 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2563 adapter->rx_itr = low_latency;
2564
2565 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2566
2567
2568 switch (current_itr) {
2569 case lowest_latency:
2570 new_itr = 70000;
2571 break;
2572 case low_latency:
2573 new_itr = 20000;
2574 break;
2575 case bulk_latency:
2576 new_itr = 4000;
2577 break;
2578 default:
2579 break;
2580 }
2581
2582set_itr_now:
2583 if (new_itr != adapter->itr) {
2584
2585
2586
2587
2588 new_itr = new_itr > adapter->itr ?
2589 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2590 adapter->itr = new_itr;
2591 adapter->rx_ring->itr_val = new_itr;
2592 if (adapter->msix_entries)
2593 adapter->rx_ring->set_itr = 1;
2594 else
2595 e1000e_write_itr(adapter, new_itr);
2596 }
2597}
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2609{
2610 struct e1000_hw *hw = &adapter->hw;
2611 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2612
2613 if (adapter->msix_entries) {
2614 int vector;
2615
2616 for (vector = 0; vector < adapter->num_vectors; vector++)
2617 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2618 } else {
2619 ew32(ITR, new_itr);
2620 }
2621}
2622
2623
2624
2625
2626
2627static int e1000_alloc_queues(struct e1000_adapter *adapter)
2628{
2629 int size = sizeof(struct e1000_ring);
2630
2631 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2632 if (!adapter->tx_ring)
2633 goto err;
2634 adapter->tx_ring->count = adapter->tx_ring_count;
2635 adapter->tx_ring->adapter = adapter;
2636
2637 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2638 if (!adapter->rx_ring)
2639 goto err;
2640 adapter->rx_ring->count = adapter->rx_ring_count;
2641 adapter->rx_ring->adapter = adapter;
2642
2643 return 0;
2644err:
2645 e_err("Unable to allocate memory for queues\n");
2646 kfree(adapter->rx_ring);
2647 kfree(adapter->tx_ring);
2648 return -ENOMEM;
2649}
2650
2651
2652
2653
2654
2655
2656static int e1000e_poll(struct napi_struct *napi, int budget)
2657{
2658 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2659 napi);
2660 struct e1000_hw *hw = &adapter->hw;
2661 struct net_device *poll_dev = adapter->netdev;
2662 int tx_cleaned = 1, work_done = 0;
2663
2664 adapter = netdev_priv(poll_dev);
2665
2666 if (!adapter->msix_entries ||
2667 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2668 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2669
2670 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2671
2672 if (!tx_cleaned || work_done == budget)
2673 return budget;
2674
2675
2676
2677
2678 if (likely(napi_complete_done(napi, work_done))) {
2679 if (adapter->itr_setting & 3)
2680 e1000_set_itr(adapter);
2681 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2682 if (adapter->msix_entries)
2683 ew32(IMS, adapter->rx_ring->ims_val);
2684 else
2685 e1000_irq_enable(adapter);
2686 }
2687 }
2688
2689 return work_done;
2690}
2691
2692static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2693 __always_unused __be16 proto, u16 vid)
2694{
2695 struct e1000_adapter *adapter = netdev_priv(netdev);
2696 struct e1000_hw *hw = &adapter->hw;
2697 u32 vfta, index;
2698
2699
2700 if ((adapter->hw.mng_cookie.status &
2701 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2702 (vid == adapter->mng_vlan_id))
2703 return 0;
2704
2705
2706 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2707 index = (vid >> 5) & 0x7F;
2708 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2709 vfta |= BIT((vid & 0x1F));
2710 hw->mac.ops.write_vfta(hw, index, vfta);
2711 }
2712
2713 set_bit(vid, adapter->active_vlans);
2714
2715 return 0;
2716}
2717
2718static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2719 __always_unused __be16 proto, u16 vid)
2720{
2721 struct e1000_adapter *adapter = netdev_priv(netdev);
2722 struct e1000_hw *hw = &adapter->hw;
2723 u32 vfta, index;
2724
2725 if ((adapter->hw.mng_cookie.status &
2726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2727 (vid == adapter->mng_vlan_id)) {
2728
2729 e1000e_release_hw_control(adapter);
2730 return 0;
2731 }
2732
2733
2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2735 index = (vid >> 5) & 0x7F;
2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2737 vfta &= ~BIT((vid & 0x1F));
2738 hw->mac.ops.write_vfta(hw, index, vfta);
2739 }
2740
2741 clear_bit(vid, adapter->active_vlans);
2742
2743 return 0;
2744}
2745
2746
2747
2748
2749
2750static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2751{
2752 struct net_device *netdev = adapter->netdev;
2753 struct e1000_hw *hw = &adapter->hw;
2754 u32 rctl;
2755
2756 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2757
2758 rctl = er32(RCTL);
2759 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2760 ew32(RCTL, rctl);
2761
2762 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2763 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2764 adapter->mng_vlan_id);
2765 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2766 }
2767 }
2768}
2769
2770
2771
2772
2773
2774static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2775{
2776 struct e1000_hw *hw = &adapter->hw;
2777 u32 rctl;
2778
2779 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2780
2781 rctl = er32(RCTL);
2782 rctl |= E1000_RCTL_VFE;
2783 rctl &= ~E1000_RCTL_CFIEN;
2784 ew32(RCTL, rctl);
2785 }
2786}
2787
2788
2789
2790
2791
2792static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2793{
2794 struct e1000_hw *hw = &adapter->hw;
2795 u32 ctrl;
2796
2797
2798 ctrl = er32(CTRL);
2799 ctrl &= ~E1000_CTRL_VME;
2800 ew32(CTRL, ctrl);
2801}
2802
2803
2804
2805
2806
2807static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2808{
2809 struct e1000_hw *hw = &adapter->hw;
2810 u32 ctrl;
2811
2812
2813 ctrl = er32(CTRL);
2814 ctrl |= E1000_CTRL_VME;
2815 ew32(CTRL, ctrl);
2816}
2817
2818static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2819{
2820 struct net_device *netdev = adapter->netdev;
2821 u16 vid = adapter->hw.mng_cookie.vlan_id;
2822 u16 old_vid = adapter->mng_vlan_id;
2823
2824 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2825 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2826 adapter->mng_vlan_id = vid;
2827 }
2828
2829 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2830 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2831}
2832
2833static void e1000_restore_vlan(struct e1000_adapter *adapter)
2834{
2835 u16 vid;
2836
2837 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2838
2839 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2841}
2842
2843static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2844{
2845 struct e1000_hw *hw = &adapter->hw;
2846 u32 manc, manc2h, mdef, i, j;
2847
2848 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2849 return;
2850
2851 manc = er32(MANC);
2852
2853
2854
2855
2856
2857 manc |= E1000_MANC_EN_MNG2HOST;
2858 manc2h = er32(MANC2H);
2859
2860 switch (hw->mac.type) {
2861 default:
2862 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2863 break;
2864 case e1000_82574:
2865 case e1000_82583:
2866
2867
2868
2869 for (i = 0, j = 0; i < 8; i++) {
2870 mdef = er32(MDEF(i));
2871
2872
2873 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2874 continue;
2875
2876
2877 if (mdef)
2878 manc2h |= BIT(i);
2879
2880 j |= mdef;
2881 }
2882
2883 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2884 break;
2885
2886
2887 for (i = 0, j = 0; i < 8; i++)
2888 if (er32(MDEF(i)) == 0) {
2889 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2890 E1000_MDEF_PORT_664));
2891 manc2h |= BIT(1);
2892 j++;
2893 break;
2894 }
2895
2896 if (!j)
2897 e_warn("Unable to create IPMI pass-through filter\n");
2898 break;
2899 }
2900
2901 ew32(MANC2H, manc2h);
2902 ew32(MANC, manc);
2903}
2904
2905
2906
2907
2908
2909
2910
2911static void e1000_configure_tx(struct e1000_adapter *adapter)
2912{
2913 struct e1000_hw *hw = &adapter->hw;
2914 struct e1000_ring *tx_ring = adapter->tx_ring;
2915 u64 tdba;
2916 u32 tdlen, tctl, tarc;
2917
2918
2919 tdba = tx_ring->dma;
2920 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2921 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2922 ew32(TDBAH(0), (tdba >> 32));
2923 ew32(TDLEN(0), tdlen);
2924 ew32(TDH(0), 0);
2925 ew32(TDT(0), 0);
2926 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2927 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2928
2929 writel(0, tx_ring->head);
2930 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2931 e1000e_update_tdt_wa(tx_ring, 0);
2932 else
2933 writel(0, tx_ring->tail);
2934
2935
2936 ew32(TIDV, adapter->tx_int_delay);
2937
2938 ew32(TADV, adapter->tx_abs_int_delay);
2939
2940 if (adapter->flags2 & FLAG2_DMA_BURST) {
2941 u32 txdctl = er32(TXDCTL(0));
2942
2943 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2944 E1000_TXDCTL_WTHRESH);
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2955 ew32(TXDCTL(0), txdctl);
2956 }
2957
2958 ew32(TXDCTL(1), er32(TXDCTL(0)));
2959
2960
2961 tctl = er32(TCTL);
2962 tctl &= ~E1000_TCTL_CT;
2963 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2964 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2965
2966 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2967 tarc = er32(TARC(0));
2968
2969
2970
2971#define SPEED_MODE_BIT BIT(21)
2972 tarc |= SPEED_MODE_BIT;
2973 ew32(TARC(0), tarc);
2974 }
2975
2976
2977 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2978 tarc = er32(TARC(0));
2979 tarc |= 1;
2980 ew32(TARC(0), tarc);
2981 tarc = er32(TARC(1));
2982 tarc |= 1;
2983 ew32(TARC(1), tarc);
2984 }
2985
2986
2987 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2988
2989
2990 if (adapter->tx_int_delay)
2991 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2992
2993
2994 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2995
2996 ew32(TCTL, tctl);
2997
2998 hw->mac.ops.config_collision_dist(hw);
2999
3000
3001 if (hw->mac.type == e1000_pch_spt) {
3002 u32 reg_val;
3003
3004 reg_val = er32(IOSFPC);
3005 reg_val |= E1000_RCTL_RDMTS_HEX;
3006 ew32(IOSFPC, reg_val);
3007
3008 reg_val = er32(TARC(0));
3009
3010
3011
3012
3013 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3014 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3015 ew32(TARC(0), reg_val);
3016 }
3017}
3018
3019
3020
3021
3022
3023#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3025static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 u32 rctl, rfctl;
3029 u32 pages = 0;
3030
3031
3032
3033
3034
3035 if (hw->mac.type >= e1000_pch2lan) {
3036 s32 ret_val;
3037
3038 if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 else
3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042
3043 if (ret_val)
3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 }
3046
3047
3048 rctl = er32(RCTL);
3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053
3054
3055 rctl &= ~E1000_RCTL_SBP;
3056
3057
3058 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 rctl &= ~E1000_RCTL_LPE;
3060 else
3061 rctl |= E1000_RCTL_LPE;
3062
3063
3064
3065
3066
3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 rctl |= E1000_RCTL_SECRC;
3069
3070
3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 u16 phy_data;
3073
3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 phy_data &= 0xfff8;
3076 phy_data |= BIT(2);
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078
3079 e1e_rphy(hw, 22, &phy_data);
3080 phy_data &= 0x0fff;
3081 phy_data |= BIT(14);
3082 e1e_wphy(hw, 0x10, 0x2823);
3083 e1e_wphy(hw, 0x11, 0x0003);
3084 e1e_wphy(hw, 22, phy_data);
3085 }
3086
3087
3088 rctl &= ~E1000_RCTL_SZ_4096;
3089 rctl |= E1000_RCTL_BSEX;
3090 switch (adapter->rx_buffer_len) {
3091 case 2048:
3092 default:
3093 rctl |= E1000_RCTL_SZ_2048;
3094 rctl &= ~E1000_RCTL_BSEX;
3095 break;
3096 case 4096:
3097 rctl |= E1000_RCTL_SZ_4096;
3098 break;
3099 case 8192:
3100 rctl |= E1000_RCTL_SZ_8192;
3101 break;
3102 case 16384:
3103 rctl |= E1000_RCTL_SZ_16384;
3104 break;
3105 }
3106
3107
3108 rfctl = er32(RFCTL);
3109 rfctl |= E1000_RFCTL_EXTEN;
3110 ew32(RFCTL, rfctl);
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3128 adapter->rx_ps_pages = pages;
3129 else
3130 adapter->rx_ps_pages = 0;
3131
3132 if (adapter->rx_ps_pages) {
3133 u32 psrctl = 0;
3134
3135
3136 rctl |= E1000_RCTL_DTYP_PS;
3137
3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3139
3140 switch (adapter->rx_ps_pages) {
3141 case 3:
3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3143
3144 case 2:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3146
3147 case 1:
3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3149 break;
3150 }
3151
3152 ew32(PSRCTL, psrctl);
3153 }
3154
3155
3156 if (adapter->netdev->features & NETIF_F_RXALL) {
3157
3158
3159
3160 rctl |= (E1000_RCTL_SBP |
3161 E1000_RCTL_BAM |
3162 E1000_RCTL_PMCF);
3163
3164 rctl &= ~(E1000_RCTL_VFE |
3165 E1000_RCTL_DPF |
3166 E1000_RCTL_CFIEN);
3167
3168
3169
3170 }
3171
3172 ew32(RCTL, rctl);
3173
3174 adapter->flags &= ~FLAG_RESTART_NOW;
3175}
3176
3177
3178
3179
3180
3181
3182
3183static void e1000_configure_rx(struct e1000_adapter *adapter)
3184{
3185 struct e1000_hw *hw = &adapter->hw;
3186 struct e1000_ring *rx_ring = adapter->rx_ring;
3187 u64 rdba;
3188 u32 rdlen, rctl, rxcsum, ctrl_ext;
3189
3190 if (adapter->rx_ps_pages) {
3191
3192 rdlen = rx_ring->count *
3193 sizeof(union e1000_rx_desc_packet_split);
3194 adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3200 } else {
3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3202 adapter->clean_rx = e1000_clean_rx_irq;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 }
3205
3206
3207 rctl = er32(RCTL);
3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3210 e1e_flush();
3211 usleep_range(10000, 11000);
3212
3213 if (adapter->flags2 & FLAG2_DMA_BURST) {
3214
3215
3216
3217
3218
3219
3220
3221
3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3224 }
3225
3226
3227 ew32(RDTR, adapter->rx_int_delay);
3228
3229
3230 ew32(RADV, adapter->rx_abs_int_delay);
3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3232 e1000e_write_itr(adapter, adapter->itr);
3233
3234 ctrl_ext = er32(CTRL_EXT);
3235
3236 ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 ew32(IAM, 0xffffffff);
3238 ew32(CTRL_EXT, ctrl_ext);
3239 e1e_flush();
3240
3241
3242
3243
3244 rdba = rx_ring->dma;
3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 ew32(RDBAH(0), (rdba >> 32));
3247 ew32(RDLEN(0), rdlen);
3248 ew32(RDH(0), 0);
3249 ew32(RDT(0), 0);
3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3252
3253 writel(0, rx_ring->head);
3254 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3255 e1000e_update_rdt_wa(rx_ring, 0);
3256 else
3257 writel(0, rx_ring->tail);
3258
3259
3260 rxcsum = er32(RXCSUM);
3261 if (adapter->netdev->features & NETIF_F_RXCSUM)
3262 rxcsum |= E1000_RXCSUM_TUOFL;
3263 else
3264 rxcsum &= ~E1000_RXCSUM_TUOFL;
3265 ew32(RXCSUM, rxcsum);
3266
3267
3268
3269
3270 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3271 u32 lat =
3272 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3273 adapter->max_frame_size) * 8 / 1000;
3274
3275 if (adapter->flags & FLAG_IS_ICH) {
3276 u32 rxdctl = er32(RXDCTL(0));
3277
3278 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3279 }
3280
3281 dev_info(&adapter->pdev->dev,
3282 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3283 pm_qos_update_request(&adapter->pm_qos_req, lat);
3284 } else {
3285 pm_qos_update_request(&adapter->pm_qos_req,
3286 PM_QOS_DEFAULT_VALUE);
3287 }
3288
3289
3290 ew32(RCTL, rctl);
3291}
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302static int e1000e_write_mc_addr_list(struct net_device *netdev)
3303{
3304 struct e1000_adapter *adapter = netdev_priv(netdev);
3305 struct e1000_hw *hw = &adapter->hw;
3306 struct netdev_hw_addr *ha;
3307 u8 *mta_list;
3308 int i;
3309
3310 if (netdev_mc_empty(netdev)) {
3311
3312 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3313 return 0;
3314 }
3315
3316 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3317 if (!mta_list)
3318 return -ENOMEM;
3319
3320
3321 i = 0;
3322 netdev_for_each_mc_addr(ha, netdev)
3323 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3324
3325 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3326 kfree(mta_list);
3327
3328 return netdev_mc_count(netdev);
3329}
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340static int e1000e_write_uc_addr_list(struct net_device *netdev)
3341{
3342 struct e1000_adapter *adapter = netdev_priv(netdev);
3343 struct e1000_hw *hw = &adapter->hw;
3344 unsigned int rar_entries;
3345 int count = 0;
3346
3347 rar_entries = hw->mac.ops.rar_get_count(hw);
3348
3349
3350 rar_entries--;
3351
3352
3353 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3354 rar_entries--;
3355
3356
3357 if (netdev_uc_count(netdev) > rar_entries)
3358 return -ENOMEM;
3359
3360 if (!netdev_uc_empty(netdev) && rar_entries) {
3361 struct netdev_hw_addr *ha;
3362
3363
3364
3365
3366 netdev_for_each_uc_addr(ha, netdev) {
3367 int ret_val;
3368
3369 if (!rar_entries)
3370 break;
3371 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3372 if (ret_val < 0)
3373 return -ENOMEM;
3374 count++;
3375 }
3376 }
3377
3378
3379 for (; rar_entries > 0; rar_entries--) {
3380 ew32(RAH(rar_entries), 0);
3381 ew32(RAL(rar_entries), 0);
3382 }
3383 e1e_flush();
3384
3385 return count;
3386}
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397static void e1000e_set_rx_mode(struct net_device *netdev)
3398{
3399 struct e1000_adapter *adapter = netdev_priv(netdev);
3400 struct e1000_hw *hw = &adapter->hw;
3401 u32 rctl;
3402
3403 if (pm_runtime_suspended(netdev->dev.parent))
3404 return;
3405
3406
3407 rctl = er32(RCTL);
3408
3409
3410 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3411
3412 if (netdev->flags & IFF_PROMISC) {
3413 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3414
3415 e1000e_vlan_filter_disable(adapter);
3416 } else {
3417 int count;
3418
3419 if (netdev->flags & IFF_ALLMULTI) {
3420 rctl |= E1000_RCTL_MPE;
3421 } else {
3422
3423
3424
3425
3426 count = e1000e_write_mc_addr_list(netdev);
3427 if (count < 0)
3428 rctl |= E1000_RCTL_MPE;
3429 }
3430 e1000e_vlan_filter_enable(adapter);
3431
3432
3433
3434
3435 count = e1000e_write_uc_addr_list(netdev);
3436 if (count < 0)
3437 rctl |= E1000_RCTL_UPE;
3438 }
3439
3440 ew32(RCTL, rctl);
3441
3442 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3443 e1000e_vlan_strip_enable(adapter);
3444 else
3445 e1000e_vlan_strip_disable(adapter);
3446}
3447
3448static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3449{
3450 struct e1000_hw *hw = &adapter->hw;
3451 u32 mrqc, rxcsum;
3452 u32 rss_key[10];
3453 int i;
3454
3455 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3456 for (i = 0; i < 10; i++)
3457 ew32(RSSRK(i), rss_key[i]);
3458
3459
3460 for (i = 0; i < 32; i++)
3461 ew32(RETA(i), 0);
3462
3463
3464
3465
3466 rxcsum = er32(RXCSUM);
3467 rxcsum |= E1000_RXCSUM_PCSD;
3468
3469 ew32(RXCSUM, rxcsum);
3470
3471 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3472 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3473 E1000_MRQC_RSS_FIELD_IPV6 |
3474 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3475 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3476
3477 ew32(MRQC, mrqc);
3478}
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3489{
3490 struct e1000_hw *hw = &adapter->hw;
3491 u32 incvalue, incperiod, shift;
3492
3493
3494
3495
3496 if ((hw->mac.type >= e1000_pch_lpt) &&
3497 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3498 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3499 u32 fextnvm7 = er32(FEXTNVM7);
3500
3501 if (!(fextnvm7 & BIT(0))) {
3502 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3503 e1e_flush();
3504 }
3505 }
3506
3507 switch (hw->mac.type) {
3508 case e1000_pch2lan:
3509
3510 incperiod = INCPERIOD_96MHZ;
3511 incvalue = INCVALUE_96MHZ;
3512 shift = INCVALUE_SHIFT_96MHZ;
3513 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3514 break;
3515 case e1000_pch_lpt:
3516 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3517
3518 incperiod = INCPERIOD_96MHZ;
3519 incvalue = INCVALUE_96MHZ;
3520 shift = INCVALUE_SHIFT_96MHZ;
3521 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3522 } else {
3523
3524 incperiod = INCPERIOD_25MHZ;
3525 incvalue = INCVALUE_25MHZ;
3526 shift = INCVALUE_SHIFT_25MHZ;
3527 adapter->cc.shift = shift;
3528 }
3529 break;
3530 case e1000_pch_spt:
3531
3532 incperiod = INCPERIOD_24MHZ;
3533 incvalue = INCVALUE_24MHZ;
3534 shift = INCVALUE_SHIFT_24MHZ;
3535 adapter->cc.shift = shift;
3536 break;
3537 case e1000_pch_cnp:
3538 case e1000_pch_tgp:
3539 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3540
3541 incperiod = INCPERIOD_24MHZ;
3542 incvalue = INCVALUE_24MHZ;
3543 shift = INCVALUE_SHIFT_24MHZ;
3544 adapter->cc.shift = shift;
3545 } else {
3546
3547 incperiod = INCPERIOD_38400KHZ;
3548 incvalue = INCVALUE_38400KHZ;
3549 shift = INCVALUE_SHIFT_38400KHZ;
3550 adapter->cc.shift = shift;
3551 }
3552 break;
3553 case e1000_82574:
3554 case e1000_82583:
3555
3556 incperiod = INCPERIOD_25MHZ;
3557 incvalue = INCVALUE_25MHZ;
3558 shift = INCVALUE_SHIFT_25MHZ;
3559 adapter->cc.shift = shift;
3560 break;
3561 default:
3562 return -EINVAL;
3563 }
3564
3565 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3566 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3567
3568 return 0;
3569}
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3587 struct hwtstamp_config *config)
3588{
3589 struct e1000_hw *hw = &adapter->hw;
3590 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3591 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3592 u32 rxmtrl = 0;
3593 u16 rxudp = 0;
3594 bool is_l4 = false;
3595 bool is_l2 = false;
3596 u32 regval;
3597
3598 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3599 return -EINVAL;
3600
3601
3602 if (config->flags)
3603 return -EINVAL;
3604
3605 switch (config->tx_type) {
3606 case HWTSTAMP_TX_OFF:
3607 tsync_tx_ctl = 0;
3608 break;
3609 case HWTSTAMP_TX_ON:
3610 break;
3611 default:
3612 return -ERANGE;
3613 }
3614
3615 switch (config->rx_filter) {
3616 case HWTSTAMP_FILTER_NONE:
3617 tsync_rx_ctl = 0;
3618 break;
3619 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3620 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3621 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3622 is_l4 = true;
3623 break;
3624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3626 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3627 is_l4 = true;
3628 break;
3629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3630
3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3632 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3633 is_l2 = true;
3634 break;
3635 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3636
3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3638 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3639 is_l2 = true;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3642
3643
3644
3645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3646
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3649 is_l2 = true;
3650 is_l4 = true;
3651 break;
3652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3653
3654
3655
3656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3657
3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3659 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3660 is_l2 = true;
3661 is_l4 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3665
3666
3667
3668 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3670 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3671 is_l2 = true;
3672 is_l4 = true;
3673 break;
3674 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3675
3676
3677
3678
3679 case HWTSTAMP_FILTER_NTP_ALL:
3680 case HWTSTAMP_FILTER_ALL:
3681 is_l2 = true;
3682 is_l4 = true;
3683 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3684 config->rx_filter = HWTSTAMP_FILTER_ALL;
3685 break;
3686 default:
3687 return -ERANGE;
3688 }
3689
3690 adapter->hwtstamp_config = *config;
3691
3692
3693 regval = er32(TSYNCTXCTL);
3694 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3695 regval |= tsync_tx_ctl;
3696 ew32(TSYNCTXCTL, regval);
3697 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3698 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3699 e_err("Timesync Tx Control register not set as expected\n");
3700 return -EAGAIN;
3701 }
3702
3703
3704 regval = er32(TSYNCRXCTL);
3705 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3706 regval |= tsync_rx_ctl;
3707 ew32(TSYNCRXCTL, regval);
3708 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3709 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3710 (regval & (E1000_TSYNCRXCTL_ENABLED |
3711 E1000_TSYNCRXCTL_TYPE_MASK))) {
3712 e_err("Timesync Rx Control register not set as expected\n");
3713 return -EAGAIN;
3714 }
3715
3716
3717 if (is_l2)
3718 rxmtrl |= ETH_P_1588;
3719
3720
3721 ew32(RXMTRL, rxmtrl);
3722
3723
3724 if (is_l4) {
3725 rxudp = PTP_EV_PORT;
3726 cpu_to_be16s(&rxudp);
3727 }
3728 ew32(RXUDP, rxudp);
3729
3730 e1e_flush();
3731
3732
3733 er32(RXSTMPH);
3734 er32(TXSTMPH);
3735
3736 return 0;
3737}
3738
3739
3740
3741
3742
3743static void e1000_configure(struct e1000_adapter *adapter)
3744{
3745 struct e1000_ring *rx_ring = adapter->rx_ring;
3746
3747 e1000e_set_rx_mode(adapter->netdev);
3748
3749 e1000_restore_vlan(adapter);
3750 e1000_init_manageability_pt(adapter);
3751
3752 e1000_configure_tx(adapter);
3753
3754 if (adapter->netdev->features & NETIF_F_RXHASH)
3755 e1000e_setup_rss_hash(adapter);
3756 e1000_setup_rctl(adapter);
3757 e1000_configure_rx(adapter);
3758 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3759}
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769void e1000e_power_up_phy(struct e1000_adapter *adapter)
3770{
3771 if (adapter->hw.phy.ops.power_up)
3772 adapter->hw.phy.ops.power_up(&adapter->hw);
3773
3774 adapter->hw.mac.ops.setup_link(&adapter->hw);
3775}
3776
3777
3778
3779
3780
3781
3782
3783static void e1000_power_down_phy(struct e1000_adapter *adapter)
3784{
3785 if (adapter->hw.phy.ops.power_down)
3786 adapter->hw.phy.ops.power_down(&adapter->hw);
3787}
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3798{
3799 struct e1000_hw *hw = &adapter->hw;
3800 struct e1000_ring *tx_ring = adapter->tx_ring;
3801 struct e1000_tx_desc *tx_desc = NULL;
3802 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3803 u16 size = 512;
3804
3805 tctl = er32(TCTL);
3806 ew32(TCTL, tctl | E1000_TCTL_EN);
3807 tdt = er32(TDT(0));
3808 BUG_ON(tdt != tx_ring->next_to_use);
3809 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3810 tx_desc->buffer_addr = tx_ring->dma;
3811
3812 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3813 tx_desc->upper.data = 0;
3814
3815 wmb();
3816 tx_ring->next_to_use++;
3817 if (tx_ring->next_to_use == tx_ring->count)
3818 tx_ring->next_to_use = 0;
3819 ew32(TDT(0), tx_ring->next_to_use);
3820 usleep_range(200, 250);
3821}
3822
3823
3824
3825
3826
3827
3828static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3829{
3830 u32 rctl, rxdctl;
3831 struct e1000_hw *hw = &adapter->hw;
3832
3833 rctl = er32(RCTL);
3834 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3835 e1e_flush();
3836 usleep_range(100, 150);
3837
3838 rxdctl = er32(RXDCTL(0));
3839
3840 rxdctl &= 0xffffc000;
3841
3842
3843
3844
3845 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3846
3847 ew32(RXDCTL(0), rxdctl);
3848
3849 ew32(RCTL, rctl | E1000_RCTL_EN);
3850 e1e_flush();
3851 usleep_range(100, 150);
3852 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3853}
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3867{
3868 u16 hang_state;
3869 u32 fext_nvm11, tdlen;
3870 struct e1000_hw *hw = &adapter->hw;
3871
3872
3873 fext_nvm11 = er32(FEXTNVM11);
3874 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3875 ew32(FEXTNVM11, fext_nvm11);
3876
3877 tdlen = er32(TDLEN(0));
3878 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3879 &hang_state);
3880 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3881 return;
3882 e1000_flush_tx_ring(adapter);
3883
3884 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3885 &hang_state);
3886 if (hang_state & FLUSH_DESC_REQUIRED)
3887 e1000_flush_rx_ring(adapter);
3888}
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899static void e1000e_systim_reset(struct e1000_adapter *adapter)
3900{
3901 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3902 struct e1000_hw *hw = &adapter->hw;
3903 unsigned long flags;
3904 u32 timinca;
3905 s32 ret_val;
3906
3907 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3908 return;
3909
3910 if (info->adjfreq) {
3911
3912 ret_val = info->adjfreq(info, adapter->ptp_delta);
3913 } else {
3914
3915 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3916 if (!ret_val)
3917 ew32(TIMINCA, timinca);
3918 }
3919
3920 if (ret_val) {
3921 dev_warn(&adapter->pdev->dev,
3922 "Failed to restore TIMINCA clock rate delta: %d\n",
3923 ret_val);
3924 return;
3925 }
3926
3927
3928 spin_lock_irqsave(&adapter->systim_lock, flags);
3929 timecounter_init(&adapter->tc, &adapter->cc,
3930 ktime_to_ns(ktime_get_real()));
3931 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3932
3933
3934 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3935}
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945void e1000e_reset(struct e1000_adapter *adapter)
3946{
3947 struct e1000_mac_info *mac = &adapter->hw.mac;
3948 struct e1000_fc_info *fc = &adapter->hw.fc;
3949 struct e1000_hw *hw = &adapter->hw;
3950 u32 tx_space, min_tx_space, min_rx_space;
3951 u32 pba = adapter->pba;
3952 u16 hwm;
3953
3954
3955 ew32(PBA, pba);
3956
3957 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3958
3959
3960
3961
3962
3963
3964
3965 pba = er32(PBA);
3966
3967 tx_space = pba >> 16;
3968
3969 pba &= 0xffff;
3970
3971
3972
3973 min_tx_space = (adapter->max_frame_size +
3974 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3975 min_tx_space = ALIGN(min_tx_space, 1024);
3976 min_tx_space >>= 10;
3977
3978 min_rx_space = adapter->max_frame_size;
3979 min_rx_space = ALIGN(min_rx_space, 1024);
3980 min_rx_space >>= 10;
3981
3982
3983
3984
3985
3986 if ((tx_space < min_tx_space) &&
3987 ((min_tx_space - tx_space) < pba)) {
3988 pba -= min_tx_space - tx_space;
3989
3990
3991
3992
3993 if (pba < min_rx_space)
3994 pba = min_rx_space;
3995 }
3996
3997 ew32(PBA, pba);
3998 }
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4009 fc->pause_time = 0xFFFF;
4010 else
4011 fc->pause_time = E1000_FC_PAUSE_TIME;
4012 fc->send_xon = true;
4013 fc->current_mode = fc->requested_mode;
4014
4015 switch (hw->mac.type) {
4016 case e1000_ich9lan:
4017 case e1000_ich10lan:
4018 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4019 pba = 14;
4020 ew32(PBA, pba);
4021 fc->high_water = 0x2800;
4022 fc->low_water = fc->high_water - 8;
4023 break;
4024 }
4025
4026 default:
4027 hwm = min(((pba << 10) * 9 / 10),
4028 ((pba << 10) - adapter->max_frame_size));
4029
4030 fc->high_water = hwm & E1000_FCRTH_RTH;
4031 fc->low_water = fc->high_water - 8;
4032 break;
4033 case e1000_pchlan:
4034
4035
4036
4037 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4038 fc->high_water = 0x3500;
4039 fc->low_water = 0x1500;
4040 } else {
4041 fc->high_water = 0x5000;
4042 fc->low_water = 0x3000;
4043 }
4044 fc->refresh_time = 0x1000;
4045 break;
4046 case e1000_pch2lan:
4047 case e1000_pch_lpt:
4048 case e1000_pch_spt:
4049 case e1000_pch_cnp:
4050
4051 case e1000_pch_tgp:
4052 fc->refresh_time = 0xFFFF;
4053 fc->pause_time = 0xFFFF;
4054
4055 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4056 fc->high_water = 0x05C20;
4057 fc->low_water = 0x05048;
4058 break;
4059 }
4060
4061 pba = 14;
4062 ew32(PBA, pba);
4063 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4064 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4065 break;
4066 }
4067
4068
4069
4070
4071
4072
4073 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4074 24 << 10);
4075
4076
4077
4078
4079 if (adapter->itr_setting & 0x3) {
4080 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4081 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4082 dev_info(&adapter->pdev->dev,
4083 "Interrupt Throttle Rate off\n");
4084 adapter->flags2 |= FLAG2_DISABLE_AIM;
4085 e1000e_write_itr(adapter, 0);
4086 }
4087 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4088 dev_info(&adapter->pdev->dev,
4089 "Interrupt Throttle Rate on\n");
4090 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4091 adapter->itr = 20000;
4092 e1000e_write_itr(adapter, adapter->itr);
4093 }
4094 }
4095
4096 if (hw->mac.type >= e1000_pch_spt)
4097 e1000_flush_desc_rings(adapter);
4098
4099 mac->ops.reset_hw(hw);
4100
4101
4102
4103
4104 if (adapter->flags & FLAG_HAS_AMT)
4105 e1000e_get_hw_control(adapter);
4106
4107 ew32(WUC, 0);
4108
4109 if (mac->ops.init_hw(hw))
4110 e_err("Hardware Error\n");
4111
4112 e1000_update_mng_vlan(adapter);
4113
4114
4115 ew32(VET, ETH_P_8021Q);
4116
4117 e1000e_reset_adaptive(hw);
4118
4119
4120 e1000e_systim_reset(adapter);
4121
4122
4123 if (adapter->flags2 & FLAG2_HAS_EEE) {
4124 s32 ret_val;
4125 u16 adv_addr;
4126
4127 switch (hw->phy.type) {
4128 case e1000_phy_82579:
4129 adv_addr = I82579_EEE_ADVERTISEMENT;
4130 break;
4131 case e1000_phy_i217:
4132 adv_addr = I217_EEE_ADVERTISEMENT;
4133 break;
4134 default:
4135 dev_err(&adapter->pdev->dev,
4136 "Invalid PHY type setting EEE advertisement\n");
4137 return;
4138 }
4139
4140 ret_val = hw->phy.ops.acquire(hw);
4141 if (ret_val) {
4142 dev_err(&adapter->pdev->dev,
4143 "EEE advertisement - unable to acquire PHY\n");
4144 return;
4145 }
4146
4147 e1000_write_emi_reg_locked(hw, adv_addr,
4148 hw->dev_spec.ich8lan.eee_disable ?
4149 0 : adapter->eee_advert);
4150
4151 hw->phy.ops.release(hw);
4152 }
4153
4154 if (!netif_running(adapter->netdev) &&
4155 !test_bit(__E1000_TESTING, &adapter->state))
4156 e1000_power_down_phy(adapter);
4157
4158 e1000_get_phy_info(hw);
4159
4160 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4161 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4162 u16 phy_data = 0;
4163
4164
4165
4166
4167 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4168 phy_data &= ~IGP02E1000_PM_SPD;
4169 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4170 }
4171 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4172 u32 reg;
4173
4174
4175 reg = er32(FEXTNVM7);
4176 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4177 ew32(FEXTNVM7, reg);
4178
4179 reg = er32(FEXTNVM9);
4180 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4181 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4182 ew32(FEXTNVM9, reg);
4183 }
4184
4185}
4186
4187
4188
4189
4190
4191
4192
4193static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4194{
4195 struct e1000_hw *hw = &adapter->hw;
4196
4197 if (adapter->msix_entries)
4198 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4199 else
4200 ew32(ICS, E1000_ICS_LSC);
4201}
4202
4203void e1000e_up(struct e1000_adapter *adapter)
4204{
4205
4206 e1000_configure(adapter);
4207
4208 clear_bit(__E1000_DOWN, &adapter->state);
4209
4210 if (adapter->msix_entries)
4211 e1000_configure_msix(adapter);
4212 e1000_irq_enable(adapter);
4213
4214
4215
4216 e1000e_trigger_lsc(adapter);
4217}
4218
4219static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4220{
4221 struct e1000_hw *hw = &adapter->hw;
4222
4223 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4224 return;
4225
4226
4227 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4228 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4229
4230
4231 e1e_flush();
4232
4233
4234
4235
4236 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4237 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4238
4239
4240 e1e_flush();
4241}
4242
4243static void e1000e_update_stats(struct e1000_adapter *adapter);
4244
4245
4246
4247
4248
4249
4250void e1000e_down(struct e1000_adapter *adapter, bool reset)
4251{
4252 struct net_device *netdev = adapter->netdev;
4253 struct e1000_hw *hw = &adapter->hw;
4254 u32 tctl, rctl;
4255
4256
4257
4258
4259 set_bit(__E1000_DOWN, &adapter->state);
4260
4261 netif_carrier_off(netdev);
4262
4263
4264 rctl = er32(RCTL);
4265 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4266 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4267
4268
4269 netif_stop_queue(netdev);
4270
4271
4272 tctl = er32(TCTL);
4273 tctl &= ~E1000_TCTL_EN;
4274 ew32(TCTL, tctl);
4275
4276
4277 e1e_flush();
4278 usleep_range(10000, 11000);
4279
4280 e1000_irq_disable(adapter);
4281
4282 napi_synchronize(&adapter->napi);
4283
4284 del_timer_sync(&adapter->watchdog_timer);
4285 del_timer_sync(&adapter->phy_info_timer);
4286
4287 spin_lock(&adapter->stats64_lock);
4288 e1000e_update_stats(adapter);
4289 spin_unlock(&adapter->stats64_lock);
4290
4291 e1000e_flush_descriptors(adapter);
4292
4293 adapter->link_speed = 0;
4294 adapter->link_duplex = 0;
4295
4296
4297 if ((hw->mac.type >= e1000_pch2lan) &&
4298 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4299 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4300 e_dbg("failed to disable jumbo frame workaround mode\n");
4301
4302 if (!pci_channel_offline(adapter->pdev)) {
4303 if (reset)
4304 e1000e_reset(adapter);
4305 else if (hw->mac.type >= e1000_pch_spt)
4306 e1000_flush_desc_rings(adapter);
4307 }
4308 e1000_clean_tx_ring(adapter->tx_ring);
4309 e1000_clean_rx_ring(adapter->rx_ring);
4310}
4311
4312void e1000e_reinit_locked(struct e1000_adapter *adapter)
4313{
4314 might_sleep();
4315 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4316 usleep_range(1000, 1100);
4317 e1000e_down(adapter, true);
4318 e1000e_up(adapter);
4319 clear_bit(__E1000_RESETTING, &adapter->state);
4320}
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4334 struct ptp_system_timestamp *sts)
4335{
4336 u64 time_delta, rem, temp;
4337 u64 systim_next;
4338 u32 incvalue;
4339 int i;
4340
4341 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4342 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4343
4344 ptp_read_system_prets(sts);
4345 systim_next = (u64)er32(SYSTIML);
4346 ptp_read_system_postts(sts);
4347 systim_next |= (u64)er32(SYSTIMH) << 32;
4348
4349 time_delta = systim_next - systim;
4350 temp = time_delta;
4351
4352 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4353
4354 systim = systim_next;
4355
4356 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4357 break;
4358 }
4359
4360 return systim;
4361}
4362
4363
4364
4365
4366
4367
4368
4369u64 e1000e_read_systim(struct e1000_adapter *adapter,
4370 struct ptp_system_timestamp *sts)
4371{
4372 struct e1000_hw *hw = &adapter->hw;
4373 u32 systimel, systimel_2, systimeh;
4374 u64 systim;
4375
4376
4377
4378
4379
4380
4381 ptp_read_system_prets(sts);
4382 systimel = er32(SYSTIML);
4383 ptp_read_system_postts(sts);
4384 systimeh = er32(SYSTIMH);
4385
4386 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4387 ptp_read_system_prets(sts);
4388 systimel_2 = er32(SYSTIML);
4389 ptp_read_system_postts(sts);
4390 if (systimel > systimel_2) {
4391
4392
4393
4394 systimeh = er32(SYSTIMH);
4395 systimel = systimel_2;
4396 }
4397 }
4398 systim = (u64)systimel;
4399 systim |= (u64)systimeh << 32;
4400
4401 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4402 systim = e1000e_sanitize_systim(hw, systim, sts);
4403
4404 return systim;
4405}
4406
4407
4408
4409
4410
4411static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4412{
4413 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4414 cc);
4415
4416 return e1000e_read_systim(adapter, NULL);
4417}
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427static int e1000_sw_init(struct e1000_adapter *adapter)
4428{
4429 struct net_device *netdev = adapter->netdev;
4430
4431 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4432 adapter->rx_ps_bsize0 = 128;
4433 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4434 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4435 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4436 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4437
4438 spin_lock_init(&adapter->stats64_lock);
4439
4440 e1000e_set_interrupt_capability(adapter);
4441
4442 if (e1000_alloc_queues(adapter))
4443 return -ENOMEM;
4444
4445
4446 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4447 adapter->cc.read = e1000e_cyclecounter_read;
4448 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4449 adapter->cc.mult = 1;
4450
4451
4452 spin_lock_init(&adapter->systim_lock);
4453 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4454 }
4455
4456
4457 e1000_irq_disable(adapter);
4458
4459 set_bit(__E1000_DOWN, &adapter->state);
4460 return 0;
4461}
4462
4463
4464
4465
4466
4467
4468static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4469{
4470 struct net_device *netdev = data;
4471 struct e1000_adapter *adapter = netdev_priv(netdev);
4472 struct e1000_hw *hw = &adapter->hw;
4473 u32 icr = er32(ICR);
4474
4475 e_dbg("icr is %08X\n", icr);
4476 if (icr & E1000_ICR_RXSEQ) {
4477 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4478
4479
4480
4481 wmb();
4482 }
4483
4484 return IRQ_HANDLED;
4485}
4486
4487
4488
4489
4490
4491
4492
4493static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4494{
4495 struct net_device *netdev = adapter->netdev;
4496 struct e1000_hw *hw = &adapter->hw;
4497 int err;
4498
4499
4500
4501 er32(ICR);
4502
4503
4504 e1000_free_irq(adapter);
4505 e1000e_reset_interrupt_capability(adapter);
4506
4507
4508
4509
4510 adapter->flags |= FLAG_MSI_TEST_FAILED;
4511
4512 err = pci_enable_msi(adapter->pdev);
4513 if (err)
4514 goto msi_test_failed;
4515
4516 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4517 netdev->name, netdev);
4518 if (err) {
4519 pci_disable_msi(adapter->pdev);
4520 goto msi_test_failed;
4521 }
4522
4523
4524
4525
4526 wmb();
4527
4528 e1000_irq_enable(adapter);
4529
4530
4531 ew32(ICS, E1000_ICS_RXSEQ);
4532 e1e_flush();
4533 msleep(100);
4534
4535 e1000_irq_disable(adapter);
4536
4537 rmb();
4538
4539 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4540 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4541 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4542 } else {
4543 e_dbg("MSI interrupt test succeeded!\n");
4544 }
4545
4546 free_irq(adapter->pdev->irq, netdev);
4547 pci_disable_msi(adapter->pdev);
4548
4549msi_test_failed:
4550 e1000e_set_interrupt_capability(adapter);
4551 return e1000_request_irq(adapter);
4552}
4553
4554
4555
4556
4557
4558
4559
4560static int e1000_test_msi(struct e1000_adapter *adapter)
4561{
4562 int err;
4563 u16 pci_cmd;
4564
4565 if (!(adapter->flags & FLAG_MSI_ENABLED))
4566 return 0;
4567
4568
4569 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4570 if (pci_cmd & PCI_COMMAND_SERR)
4571 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4572 pci_cmd & ~PCI_COMMAND_SERR);
4573
4574 err = e1000_test_msi_interrupt(adapter);
4575
4576
4577 if (pci_cmd & PCI_COMMAND_SERR) {
4578 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4579 pci_cmd |= PCI_COMMAND_SERR;
4580 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4581 }
4582
4583 return err;
4584}
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598int e1000e_open(struct net_device *netdev)
4599{
4600 struct e1000_adapter *adapter = netdev_priv(netdev);
4601 struct e1000_hw *hw = &adapter->hw;
4602 struct pci_dev *pdev = adapter->pdev;
4603 int err;
4604
4605
4606 if (test_bit(__E1000_TESTING, &adapter->state))
4607 return -EBUSY;
4608
4609 pm_runtime_get_sync(&pdev->dev);
4610
4611 netif_carrier_off(netdev);
4612 netif_stop_queue(netdev);
4613
4614
4615 err = e1000e_setup_tx_resources(adapter->tx_ring);
4616 if (err)
4617 goto err_setup_tx;
4618
4619
4620 err = e1000e_setup_rx_resources(adapter->rx_ring);
4621 if (err)
4622 goto err_setup_rx;
4623
4624
4625
4626
4627 if (adapter->flags & FLAG_HAS_AMT) {
4628 e1000e_get_hw_control(adapter);
4629 e1000e_reset(adapter);
4630 }
4631
4632 e1000e_power_up_phy(adapter);
4633
4634 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4635 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4636 e1000_update_mng_vlan(adapter);
4637
4638
4639 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4640 PM_QOS_DEFAULT_VALUE);
4641
4642
4643
4644
4645
4646
4647 e1000_configure(adapter);
4648
4649 err = e1000_request_irq(adapter);
4650 if (err)
4651 goto err_req_irq;
4652
4653
4654
4655
4656
4657 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4658 err = e1000_test_msi(adapter);
4659 if (err) {
4660 e_err("Interrupt allocation failed\n");
4661 goto err_req_irq;
4662 }
4663 }
4664
4665
4666 clear_bit(__E1000_DOWN, &adapter->state);
4667
4668 napi_enable(&adapter->napi);
4669
4670 e1000_irq_enable(adapter);
4671
4672 adapter->tx_hang_recheck = false;
4673
4674 hw->mac.get_link_status = true;
4675 pm_runtime_put(&pdev->dev);
4676
4677 e1000e_trigger_lsc(adapter);
4678
4679 return 0;
4680
4681err_req_irq:
4682 pm_qos_remove_request(&adapter->pm_qos_req);
4683 e1000e_release_hw_control(adapter);
4684 e1000_power_down_phy(adapter);
4685 e1000e_free_rx_resources(adapter->rx_ring);
4686err_setup_rx:
4687 e1000e_free_tx_resources(adapter->tx_ring);
4688err_setup_tx:
4689 e1000e_reset(adapter);
4690 pm_runtime_put_sync(&pdev->dev);
4691
4692 return err;
4693}
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706int e1000e_close(struct net_device *netdev)
4707{
4708 struct e1000_adapter *adapter = netdev_priv(netdev);
4709 struct pci_dev *pdev = adapter->pdev;
4710 int count = E1000_CHECK_RESET_COUNT;
4711
4712 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4713 usleep_range(10000, 11000);
4714
4715 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4716
4717 pm_runtime_get_sync(&pdev->dev);
4718
4719 if (netif_device_present(netdev)) {
4720 e1000e_down(adapter, true);
4721 e1000_free_irq(adapter);
4722
4723
4724 netdev_info(netdev, "NIC Link is Down\n");
4725 }
4726
4727 napi_disable(&adapter->napi);
4728
4729 e1000e_free_tx_resources(adapter->tx_ring);
4730 e1000e_free_rx_resources(adapter->rx_ring);
4731
4732
4733
4734
4735 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4736 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4737 adapter->mng_vlan_id);
4738
4739
4740
4741
4742 if ((adapter->flags & FLAG_HAS_AMT) &&
4743 !test_bit(__E1000_TESTING, &adapter->state))
4744 e1000e_release_hw_control(adapter);
4745
4746 pm_qos_remove_request(&adapter->pm_qos_req);
4747
4748 pm_runtime_put_sync(&pdev->dev);
4749
4750 return 0;
4751}
4752
4753
4754
4755
4756
4757
4758
4759
4760static int e1000_set_mac(struct net_device *netdev, void *p)
4761{
4762 struct e1000_adapter *adapter = netdev_priv(netdev);
4763 struct e1000_hw *hw = &adapter->hw;
4764 struct sockaddr *addr = p;
4765
4766 if (!is_valid_ether_addr(addr->sa_data))
4767 return -EADDRNOTAVAIL;
4768
4769 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4770 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4771
4772 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4773
4774 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4775
4776 e1000e_set_laa_state_82571(&adapter->hw, 1);
4777
4778
4779
4780
4781
4782
4783
4784
4785 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4786 adapter->hw.mac.rar_entry_count - 1);
4787 }
4788
4789 return 0;
4790}
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800static void e1000e_update_phy_task(struct work_struct *work)
4801{
4802 struct e1000_adapter *adapter = container_of(work,
4803 struct e1000_adapter,
4804 update_phy_task);
4805 struct e1000_hw *hw = &adapter->hw;
4806
4807 if (test_bit(__E1000_DOWN, &adapter->state))
4808 return;
4809
4810 e1000_get_phy_info(hw);
4811
4812
4813 if (hw->phy.type >= e1000_phy_82579)
4814 e1000_set_eee_pchlan(hw);
4815}
4816
4817
4818
4819
4820
4821
4822
4823
4824static void e1000_update_phy_info(struct timer_list *t)
4825{
4826 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4827
4828 if (test_bit(__E1000_DOWN, &adapter->state))
4829 return;
4830
4831 schedule_work(&adapter->update_phy_task);
4832}
4833
4834
4835
4836
4837
4838
4839
4840static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4841{
4842 struct e1000_hw *hw = &adapter->hw;
4843 s32 ret_val;
4844 u16 phy_data;
4845
4846 ret_val = hw->phy.ops.acquire(hw);
4847 if (ret_val)
4848 return;
4849
4850
4851
4852
4853 hw->phy.addr = 1;
4854 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4855 &phy_data);
4856 if (ret_val)
4857 goto release;
4858 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4859 ret_val = hw->phy.ops.set_page(hw,
4860 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4861 if (ret_val)
4862 goto release;
4863 }
4864
4865
4866 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4867 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4868 if (!ret_val)
4869 adapter->stats.scc += phy_data;
4870
4871
4872 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4873 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4874 if (!ret_val)
4875 adapter->stats.ecol += phy_data;
4876
4877
4878 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4879 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4880 if (!ret_val)
4881 adapter->stats.mcc += phy_data;
4882
4883
4884 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4885 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4886 if (!ret_val)
4887 adapter->stats.latecol += phy_data;
4888
4889
4890 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4891 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4892 if (!ret_val)
4893 hw->mac.collision_delta = phy_data;
4894
4895
4896 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4897 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4898 if (!ret_val)
4899 adapter->stats.dc += phy_data;
4900
4901
4902 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4903 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4904 if (!ret_val)
4905 adapter->stats.tncrs += phy_data;
4906
4907release:
4908 hw->phy.ops.release(hw);
4909}
4910
4911
4912
4913
4914
4915static void e1000e_update_stats(struct e1000_adapter *adapter)
4916{
4917 struct net_device *netdev = adapter->netdev;
4918 struct e1000_hw *hw = &adapter->hw;
4919 struct pci_dev *pdev = adapter->pdev;
4920
4921
4922
4923
4924 if (adapter->link_speed == 0)
4925 return;
4926 if (pci_channel_offline(pdev))
4927 return;
4928
4929 adapter->stats.crcerrs += er32(CRCERRS);
4930 adapter->stats.gprc += er32(GPRC);
4931 adapter->stats.gorc += er32(GORCL);
4932 er32(GORCH);
4933 adapter->stats.bprc += er32(BPRC);
4934 adapter->stats.mprc += er32(MPRC);
4935 adapter->stats.roc += er32(ROC);
4936
4937 adapter->stats.mpc += er32(MPC);
4938
4939
4940 if (adapter->link_duplex == HALF_DUPLEX) {
4941 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4942 e1000e_update_phy_stats(adapter);
4943 } else {
4944 adapter->stats.scc += er32(SCC);
4945 adapter->stats.ecol += er32(ECOL);
4946 adapter->stats.mcc += er32(MCC);
4947 adapter->stats.latecol += er32(LATECOL);
4948 adapter->stats.dc += er32(DC);
4949
4950 hw->mac.collision_delta = er32(COLC);
4951
4952 if ((hw->mac.type != e1000_82574) &&
4953 (hw->mac.type != e1000_82583))
4954 adapter->stats.tncrs += er32(TNCRS);
4955 }
4956 adapter->stats.colc += hw->mac.collision_delta;
4957 }
4958
4959 adapter->stats.xonrxc += er32(XONRXC);
4960 adapter->stats.xontxc += er32(XONTXC);
4961 adapter->stats.xoffrxc += er32(XOFFRXC);
4962 adapter->stats.xofftxc += er32(XOFFTXC);
4963 adapter->stats.gptc += er32(GPTC);
4964 adapter->stats.gotc += er32(GOTCL);
4965 er32(GOTCH);
4966 adapter->stats.rnbc += er32(RNBC);
4967 adapter->stats.ruc += er32(RUC);
4968
4969 adapter->stats.mptc += er32(MPTC);
4970 adapter->stats.bptc += er32(BPTC);
4971
4972
4973
4974 hw->mac.tx_packet_delta = er32(TPT);
4975 adapter->stats.tpt += hw->mac.tx_packet_delta;
4976
4977 adapter->stats.algnerrc += er32(ALGNERRC);
4978 adapter->stats.rxerrc += er32(RXERRC);
4979 adapter->stats.cexterr += er32(CEXTERR);
4980 adapter->stats.tsctc += er32(TSCTC);
4981 adapter->stats.tsctfc += er32(TSCTFC);
4982
4983
4984 netdev->stats.multicast = adapter->stats.mprc;
4985 netdev->stats.collisions = adapter->stats.colc;
4986
4987
4988
4989
4990
4991
4992 netdev->stats.rx_errors = adapter->stats.rxerrc +
4993 adapter->stats.crcerrs + adapter->stats.algnerrc +
4994 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4995 netdev->stats.rx_length_errors = adapter->stats.ruc +
4996 adapter->stats.roc;
4997 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4998 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4999 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5000
5001
5002 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5003 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5004 netdev->stats.tx_window_errors = adapter->stats.latecol;
5005 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5006
5007
5008
5009
5010 adapter->stats.mgptc += er32(MGTPTC);
5011 adapter->stats.mgprc += er32(MGTPRC);
5012 adapter->stats.mgpdc += er32(MGTPDC);
5013
5014
5015 if (hw->mac.type >= e1000_pch_lpt) {
5016 u32 pbeccsts = er32(PBECCSTS);
5017
5018 adapter->corr_errors +=
5019 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5020 adapter->uncorr_errors +=
5021 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5022 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5023 }
5024}
5025
5026
5027
5028
5029
5030static void e1000_phy_read_status(struct e1000_adapter *adapter)
5031{
5032 struct e1000_hw *hw = &adapter->hw;
5033 struct e1000_phy_regs *phy = &adapter->phy_regs;
5034
5035 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5036 (er32(STATUS) & E1000_STATUS_LU) &&
5037 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5038 int ret_val;
5039
5040 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5041 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5042 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5043 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5044 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5045 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5046 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5047 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5048 if (ret_val)
5049 e_warn("Error reading PHY register\n");
5050 } else {
5051
5052
5053
5054 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5055 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5056 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5057 BMSR_ERCAP);
5058 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5059 ADVERTISE_ALL | ADVERTISE_CSMA);
5060 phy->lpa = 0;
5061 phy->expansion = EXPANSION_ENABLENPAGE;
5062 phy->ctrl1000 = ADVERTISE_1000FULL;
5063 phy->stat1000 = 0;
5064 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5065 }
5066}
5067
5068static void e1000_print_link_info(struct e1000_adapter *adapter)
5069{
5070 struct e1000_hw *hw = &adapter->hw;
5071 u32 ctrl = er32(CTRL);
5072
5073
5074 netdev_info(adapter->netdev,
5075 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5076 adapter->link_speed,
5077 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5078 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5079 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5080 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5081}
5082
5083static bool e1000e_has_link(struct e1000_adapter *adapter)
5084{
5085 struct e1000_hw *hw = &adapter->hw;
5086 bool link_active = false;
5087 s32 ret_val = 0;
5088
5089
5090
5091
5092
5093
5094 switch (hw->phy.media_type) {
5095 case e1000_media_type_copper:
5096 if (hw->mac.get_link_status) {
5097 ret_val = hw->mac.ops.check_for_link(hw);
5098 link_active = !hw->mac.get_link_status;
5099 } else {
5100 link_active = true;
5101 }
5102 break;
5103 case e1000_media_type_fiber:
5104 ret_val = hw->mac.ops.check_for_link(hw);
5105 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5106 break;
5107 case e1000_media_type_internal_serdes:
5108 ret_val = hw->mac.ops.check_for_link(hw);
5109 link_active = hw->mac.serdes_has_link;
5110 break;
5111 default:
5112 case e1000_media_type_unknown:
5113 break;
5114 }
5115
5116 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5117 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5118
5119 e_info("Gigabit has been disabled, downgrading speed\n");
5120 }
5121
5122 return link_active;
5123}
5124
5125static void e1000e_enable_receives(struct e1000_adapter *adapter)
5126{
5127
5128 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5129 (adapter->flags & FLAG_RESTART_NOW)) {
5130 struct e1000_hw *hw = &adapter->hw;
5131 u32 rctl = er32(RCTL);
5132
5133 ew32(RCTL, rctl | E1000_RCTL_EN);
5134 adapter->flags &= ~FLAG_RESTART_NOW;
5135 }
5136}
5137
5138static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5139{
5140 struct e1000_hw *hw = &adapter->hw;
5141
5142
5143
5144
5145 if (e1000_check_phy_82574(hw))
5146 adapter->phy_hang_count++;
5147 else
5148 adapter->phy_hang_count = 0;
5149
5150 if (adapter->phy_hang_count > 1) {
5151 adapter->phy_hang_count = 0;
5152 e_dbg("PHY appears hung - resetting\n");
5153 schedule_work(&adapter->reset_task);
5154 }
5155}
5156
5157
5158
5159
5160
5161static void e1000_watchdog(struct timer_list *t)
5162{
5163 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5164
5165
5166 schedule_work(&adapter->watchdog_task);
5167
5168
5169}
5170
5171static void e1000_watchdog_task(struct work_struct *work)
5172{
5173 struct e1000_adapter *adapter = container_of(work,
5174 struct e1000_adapter,
5175 watchdog_task);
5176 struct net_device *netdev = adapter->netdev;
5177 struct e1000_mac_info *mac = &adapter->hw.mac;
5178 struct e1000_phy_info *phy = &adapter->hw.phy;
5179 struct e1000_ring *tx_ring = adapter->tx_ring;
5180 u32 dmoff_exit_timeout = 100, tries = 0;
5181 struct e1000_hw *hw = &adapter->hw;
5182 u32 link, tctl, pcim_state;
5183
5184 if (test_bit(__E1000_DOWN, &adapter->state))
5185 return;
5186
5187 link = e1000e_has_link(adapter);
5188 if ((netif_carrier_ok(netdev)) && link) {
5189
5190 pm_runtime_resume(netdev->dev.parent);
5191
5192 e1000e_enable_receives(adapter);
5193 goto link_up;
5194 }
5195
5196 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5197 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5198 e1000_update_mng_vlan(adapter);
5199
5200 if (link) {
5201 if (!netif_carrier_ok(netdev)) {
5202 bool txb2b = true;
5203
5204
5205 pm_runtime_resume(netdev->dev.parent);
5206
5207
5208 pcim_state = er32(STATUS);
5209 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5210 if (tries++ == dmoff_exit_timeout) {
5211 e_dbg("Error in exiting dmoff\n");
5212 break;
5213 }
5214 usleep_range(10000, 20000);
5215 pcim_state = er32(STATUS);
5216
5217
5218 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5219 e1000_phy_hw_reset(&adapter->hw);
5220 }
5221
5222
5223 e1000_phy_read_status(adapter);
5224 mac->ops.get_link_up_info(&adapter->hw,
5225 &adapter->link_speed,
5226 &adapter->link_duplex);
5227 e1000_print_link_info(adapter);
5228
5229
5230 e1000e_check_downshift(hw);
5231 if (phy->speed_downgraded)
5232 netdev_warn(netdev,
5233 "Link Speed was downgraded by SmartSpeed\n");
5234
5235
5236
5237
5238 if ((hw->phy.type == e1000_phy_igp_3 ||
5239 hw->phy.type == e1000_phy_bm) &&
5240 hw->mac.autoneg &&
5241 (adapter->link_speed == SPEED_10 ||
5242 adapter->link_speed == SPEED_100) &&
5243 (adapter->link_duplex == HALF_DUPLEX)) {
5244 u16 autoneg_exp;
5245
5246 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5247
5248 if (!(autoneg_exp & EXPANSION_NWAY))
5249 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5250 }
5251
5252
5253 adapter->tx_timeout_factor = 1;
5254 switch (adapter->link_speed) {
5255 case SPEED_10:
5256 txb2b = false;
5257 adapter->tx_timeout_factor = 16;
5258 break;
5259 case SPEED_100:
5260 txb2b = false;
5261 adapter->tx_timeout_factor = 10;
5262 break;
5263 }
5264
5265
5266
5267
5268 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5269 !txb2b) {
5270 u32 tarc0;
5271
5272 tarc0 = er32(TARC(0));
5273 tarc0 &= ~SPEED_MODE_BIT;
5274 ew32(TARC(0), tarc0);
5275 }
5276
5277
5278
5279
5280 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5281 switch (adapter->link_speed) {
5282 case SPEED_10:
5283 case SPEED_100:
5284 e_info("10/100 speed: disabling TSO\n");
5285 netdev->features &= ~NETIF_F_TSO;
5286 netdev->features &= ~NETIF_F_TSO6;
5287 break;
5288 case SPEED_1000:
5289 netdev->features |= NETIF_F_TSO;
5290 netdev->features |= NETIF_F_TSO6;
5291 break;
5292 default:
5293
5294 break;
5295 }
5296 }
5297
5298
5299
5300
5301 tctl = er32(TCTL);
5302 tctl |= E1000_TCTL_EN;
5303 ew32(TCTL, tctl);
5304
5305
5306
5307
5308 if (phy->ops.cfg_on_link_up)
5309 phy->ops.cfg_on_link_up(hw);
5310
5311 netif_wake_queue(netdev);
5312 netif_carrier_on(netdev);
5313
5314 if (!test_bit(__E1000_DOWN, &adapter->state))
5315 mod_timer(&adapter->phy_info_timer,
5316 round_jiffies(jiffies + 2 * HZ));
5317 }
5318 } else {
5319 if (netif_carrier_ok(netdev)) {
5320 adapter->link_speed = 0;
5321 adapter->link_duplex = 0;
5322
5323 netdev_info(netdev, "NIC Link is Down\n");
5324 netif_carrier_off(netdev);
5325 netif_stop_queue(netdev);
5326 if (!test_bit(__E1000_DOWN, &adapter->state))
5327 mod_timer(&adapter->phy_info_timer,
5328 round_jiffies(jiffies + 2 * HZ));
5329
5330
5331
5332
5333
5334 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5335 adapter->flags |= FLAG_RESTART_NOW;
5336 else
5337 pm_schedule_suspend(netdev->dev.parent,
5338 LINK_TIMEOUT);
5339 }
5340 }
5341
5342link_up:
5343 spin_lock(&adapter->stats64_lock);
5344 e1000e_update_stats(adapter);
5345
5346 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5347 adapter->tpt_old = adapter->stats.tpt;
5348 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5349 adapter->colc_old = adapter->stats.colc;
5350
5351 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5352 adapter->gorc_old = adapter->stats.gorc;
5353 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5354 adapter->gotc_old = adapter->stats.gotc;
5355 spin_unlock(&adapter->stats64_lock);
5356
5357
5358
5359
5360
5361 if (!netif_carrier_ok(netdev) &&
5362 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5363 adapter->flags |= FLAG_RESTART_NOW;
5364
5365
5366 if (adapter->flags & FLAG_RESTART_NOW) {
5367 schedule_work(&adapter->reset_task);
5368
5369 return;
5370 }
5371
5372 e1000e_update_adaptive(&adapter->hw);
5373
5374
5375 if (adapter->itr_setting == 4) {
5376
5377
5378
5379
5380 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5381 u32 dif = (adapter->gotc > adapter->gorc ?
5382 adapter->gotc - adapter->gorc :
5383 adapter->gorc - adapter->gotc) / 10000;
5384 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5385
5386 e1000e_write_itr(adapter, itr);
5387 }
5388
5389
5390 if (adapter->msix_entries)
5391 ew32(ICS, adapter->rx_ring->ims_val);
5392 else
5393 ew32(ICS, E1000_ICS_RXDMT0);
5394
5395
5396 e1000e_flush_descriptors(adapter);
5397
5398
5399 adapter->detect_tx_hung = true;
5400
5401
5402
5403
5404 if (e1000e_get_laa_state_82571(hw))
5405 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5406
5407 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5408 e1000e_check_82574_phy_workaround(adapter);
5409
5410
5411 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5412 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5413 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5414 er32(RXSTMPH);
5415 adapter->rx_hwtstamp_cleared++;
5416 } else {
5417 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5418 }
5419 }
5420
5421
5422 if (!test_bit(__E1000_DOWN, &adapter->state))
5423 mod_timer(&adapter->watchdog_timer,
5424 round_jiffies(jiffies + 2 * HZ));
5425}
5426
5427#define E1000_TX_FLAGS_CSUM 0x00000001
5428#define E1000_TX_FLAGS_VLAN 0x00000002
5429#define E1000_TX_FLAGS_TSO 0x00000004
5430#define E1000_TX_FLAGS_IPV4 0x00000008
5431#define E1000_TX_FLAGS_NO_FCS 0x00000010
5432#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5433#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5434#define E1000_TX_FLAGS_VLAN_SHIFT 16
5435
5436static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5437 __be16 protocol)
5438{
5439 struct e1000_context_desc *context_desc;
5440 struct e1000_buffer *buffer_info;
5441 unsigned int i;
5442 u32 cmd_length = 0;
5443 u16 ipcse = 0, mss;
5444 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5445 int err;
5446
5447 if (!skb_is_gso(skb))
5448 return 0;
5449
5450 err = skb_cow_head(skb, 0);
5451 if (err < 0)
5452 return err;
5453
5454 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5455 mss = skb_shinfo(skb)->gso_size;
5456 if (protocol == htons(ETH_P_IP)) {
5457 struct iphdr *iph = ip_hdr(skb);
5458 iph->tot_len = 0;
5459 iph->check = 0;
5460 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5461 0, IPPROTO_TCP, 0);
5462 cmd_length = E1000_TXD_CMD_IP;
5463 ipcse = skb_transport_offset(skb) - 1;
5464 } else if (skb_is_gso_v6(skb)) {
5465 ipv6_hdr(skb)->payload_len = 0;
5466 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5467 &ipv6_hdr(skb)->daddr,
5468 0, IPPROTO_TCP, 0);
5469 ipcse = 0;
5470 }
5471 ipcss = skb_network_offset(skb);
5472 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5473 tucss = skb_transport_offset(skb);
5474 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5475
5476 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5477 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5478
5479 i = tx_ring->next_to_use;
5480 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5481 buffer_info = &tx_ring->buffer_info[i];
5482
5483 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5484 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5485 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5486 context_desc->upper_setup.tcp_fields.tucss = tucss;
5487 context_desc->upper_setup.tcp_fields.tucso = tucso;
5488 context_desc->upper_setup.tcp_fields.tucse = 0;
5489 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5490 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5491 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5492
5493 buffer_info->time_stamp = jiffies;
5494 buffer_info->next_to_watch = i;
5495
5496 i++;
5497 if (i == tx_ring->count)
5498 i = 0;
5499 tx_ring->next_to_use = i;
5500
5501 return 1;
5502}
5503
5504static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5505 __be16 protocol)
5506{
5507 struct e1000_adapter *adapter = tx_ring->adapter;
5508 struct e1000_context_desc *context_desc;
5509 struct e1000_buffer *buffer_info;
5510 unsigned int i;
5511 u8 css;
5512 u32 cmd_len = E1000_TXD_CMD_DEXT;
5513
5514 if (skb->ip_summed != CHECKSUM_PARTIAL)
5515 return false;
5516
5517 switch (protocol) {
5518 case cpu_to_be16(ETH_P_IP):
5519 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5520 cmd_len |= E1000_TXD_CMD_TCP;
5521 break;
5522 case cpu_to_be16(ETH_P_IPV6):
5523
5524 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5525 cmd_len |= E1000_TXD_CMD_TCP;
5526 break;
5527 default:
5528 if (unlikely(net_ratelimit()))
5529 e_warn("checksum_partial proto=%x!\n",
5530 be16_to_cpu(protocol));
5531 break;
5532 }
5533
5534 css = skb_checksum_start_offset(skb);
5535
5536 i = tx_ring->next_to_use;
5537 buffer_info = &tx_ring->buffer_info[i];
5538 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5539
5540 context_desc->lower_setup.ip_config = 0;
5541 context_desc->upper_setup.tcp_fields.tucss = css;
5542 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5543 context_desc->upper_setup.tcp_fields.tucse = 0;
5544 context_desc->tcp_seg_setup.data = 0;
5545 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5546
5547 buffer_info->time_stamp = jiffies;
5548 buffer_info->next_to_watch = i;
5549
5550 i++;
5551 if (i == tx_ring->count)
5552 i = 0;
5553 tx_ring->next_to_use = i;
5554
5555 return true;
5556}
5557
5558static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5559 unsigned int first, unsigned int max_per_txd,
5560 unsigned int nr_frags)
5561{
5562 struct e1000_adapter *adapter = tx_ring->adapter;
5563 struct pci_dev *pdev = adapter->pdev;
5564 struct e1000_buffer *buffer_info;
5565 unsigned int len = skb_headlen(skb);
5566 unsigned int offset = 0, size, count = 0, i;
5567 unsigned int f, bytecount, segs;
5568
5569 i = tx_ring->next_to_use;
5570
5571 while (len) {
5572 buffer_info = &tx_ring->buffer_info[i];
5573 size = min(len, max_per_txd);
5574
5575 buffer_info->length = size;
5576 buffer_info->time_stamp = jiffies;
5577 buffer_info->next_to_watch = i;
5578 buffer_info->dma = dma_map_single(&pdev->dev,
5579 skb->data + offset,
5580 size, DMA_TO_DEVICE);
5581 buffer_info->mapped_as_page = false;
5582 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5583 goto dma_error;
5584
5585 len -= size;
5586 offset += size;
5587 count++;
5588
5589 if (len) {
5590 i++;
5591 if (i == tx_ring->count)
5592 i = 0;
5593 }
5594 }
5595
5596 for (f = 0; f < nr_frags; f++) {
5597 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5598
5599 len = skb_frag_size(frag);
5600 offset = 0;
5601
5602 while (len) {
5603 i++;
5604 if (i == tx_ring->count)
5605 i = 0;
5606
5607 buffer_info = &tx_ring->buffer_info[i];
5608 size = min(len, max_per_txd);
5609
5610 buffer_info->length = size;
5611 buffer_info->time_stamp = jiffies;
5612 buffer_info->next_to_watch = i;
5613 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5614 offset, size,
5615 DMA_TO_DEVICE);
5616 buffer_info->mapped_as_page = true;
5617 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5618 goto dma_error;
5619
5620 len -= size;
5621 offset += size;
5622 count++;
5623 }
5624 }
5625
5626 segs = skb_shinfo(skb)->gso_segs ? : 1;
5627
5628 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5629
5630 tx_ring->buffer_info[i].skb = skb;
5631 tx_ring->buffer_info[i].segs = segs;
5632 tx_ring->buffer_info[i].bytecount = bytecount;
5633 tx_ring->buffer_info[first].next_to_watch = i;
5634
5635 return count;
5636
5637dma_error:
5638 dev_err(&pdev->dev, "Tx DMA map failed\n");
5639 buffer_info->dma = 0;
5640 if (count)
5641 count--;
5642
5643 while (count--) {
5644 if (i == 0)
5645 i += tx_ring->count;
5646 i--;
5647 buffer_info = &tx_ring->buffer_info[i];
5648 e1000_put_txbuf(tx_ring, buffer_info, true);
5649 }
5650
5651 return 0;
5652}
5653
5654static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5655{
5656 struct e1000_adapter *adapter = tx_ring->adapter;
5657 struct e1000_tx_desc *tx_desc = NULL;
5658 struct e1000_buffer *buffer_info;
5659 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5660 unsigned int i;
5661
5662 if (tx_flags & E1000_TX_FLAGS_TSO) {
5663 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5664 E1000_TXD_CMD_TSE;
5665 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5666
5667 if (tx_flags & E1000_TX_FLAGS_IPV4)
5668 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5669 }
5670
5671 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5672 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5673 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5674 }
5675
5676 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5677 txd_lower |= E1000_TXD_CMD_VLE;
5678 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5679 }
5680
5681 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5682 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5683
5684 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5685 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5686 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5687 }
5688
5689 i = tx_ring->next_to_use;
5690
5691 do {
5692 buffer_info = &tx_ring->buffer_info[i];
5693 tx_desc = E1000_TX_DESC(*tx_ring, i);
5694 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5695 tx_desc->lower.data = cpu_to_le32(txd_lower |
5696 buffer_info->length);
5697 tx_desc->upper.data = cpu_to_le32(txd_upper);
5698
5699 i++;
5700 if (i == tx_ring->count)
5701 i = 0;
5702 } while (--count > 0);
5703
5704 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5705
5706
5707 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5708 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5709
5710
5711
5712
5713
5714
5715 wmb();
5716
5717 tx_ring->next_to_use = i;
5718}
5719
5720#define MINIMUM_DHCP_PACKET_SIZE 282
5721static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5722 struct sk_buff *skb)
5723{
5724 struct e1000_hw *hw = &adapter->hw;
5725 u16 length, offset;
5726
5727 if (skb_vlan_tag_present(skb) &&
5728 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5729 (adapter->hw.mng_cookie.status &
5730 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5731 return 0;
5732
5733 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5734 return 0;
5735
5736 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5737 return 0;
5738
5739 {
5740 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5741 struct udphdr *udp;
5742
5743 if (ip->protocol != IPPROTO_UDP)
5744 return 0;
5745
5746 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5747 if (ntohs(udp->dest) != 67)
5748 return 0;
5749
5750 offset = (u8 *)udp + 8 - skb->data;
5751 length = skb->len - offset;
5752 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5753 }
5754
5755 return 0;
5756}
5757
5758static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5759{
5760 struct e1000_adapter *adapter = tx_ring->adapter;
5761
5762 netif_stop_queue(adapter->netdev);
5763
5764
5765
5766
5767 smp_mb();
5768
5769
5770
5771
5772 if (e1000_desc_unused(tx_ring) < size)
5773 return -EBUSY;
5774
5775
5776 netif_start_queue(adapter->netdev);
5777 ++adapter->restart_queue;
5778 return 0;
5779}
5780
5781static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5782{
5783 BUG_ON(size > tx_ring->count);
5784
5785 if (e1000_desc_unused(tx_ring) >= size)
5786 return 0;
5787 return __e1000_maybe_stop_tx(tx_ring, size);
5788}
5789
5790static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5791 struct net_device *netdev)
5792{
5793 struct e1000_adapter *adapter = netdev_priv(netdev);
5794 struct e1000_ring *tx_ring = adapter->tx_ring;
5795 unsigned int first;
5796 unsigned int tx_flags = 0;
5797 unsigned int len = skb_headlen(skb);
5798 unsigned int nr_frags;
5799 unsigned int mss;
5800 int count = 0;
5801 int tso;
5802 unsigned int f;
5803 __be16 protocol = vlan_get_protocol(skb);
5804
5805 if (test_bit(__E1000_DOWN, &adapter->state)) {
5806 dev_kfree_skb_any(skb);
5807 return NETDEV_TX_OK;
5808 }
5809
5810 if (skb->len <= 0) {
5811 dev_kfree_skb_any(skb);
5812 return NETDEV_TX_OK;
5813 }
5814
5815
5816
5817
5818 if (skb_put_padto(skb, 17))
5819 return NETDEV_TX_OK;
5820
5821 mss = skb_shinfo(skb)->gso_size;
5822 if (mss) {
5823 u8 hdr_len;
5824
5825
5826
5827
5828
5829 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5830
5831
5832
5833 if (skb->data_len && (hdr_len == len)) {
5834 unsigned int pull_size;
5835
5836 pull_size = min_t(unsigned int, 4, skb->data_len);
5837 if (!__pskb_pull_tail(skb, pull_size)) {
5838 e_err("__pskb_pull_tail failed.\n");
5839 dev_kfree_skb_any(skb);
5840 return NETDEV_TX_OK;
5841 }
5842 len = skb_headlen(skb);
5843 }
5844 }
5845
5846
5847 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5848 count++;
5849 count++;
5850
5851 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5852
5853 nr_frags = skb_shinfo(skb)->nr_frags;
5854 for (f = 0; f < nr_frags; f++)
5855 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5856 adapter->tx_fifo_limit);
5857
5858 if (adapter->hw.mac.tx_pkt_filtering)
5859 e1000_transfer_dhcp_info(adapter, skb);
5860
5861
5862
5863
5864 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5865 return NETDEV_TX_BUSY;
5866
5867 if (skb_vlan_tag_present(skb)) {
5868 tx_flags |= E1000_TX_FLAGS_VLAN;
5869 tx_flags |= (skb_vlan_tag_get(skb) <<
5870 E1000_TX_FLAGS_VLAN_SHIFT);
5871 }
5872
5873 first = tx_ring->next_to_use;
5874
5875 tso = e1000_tso(tx_ring, skb, protocol);
5876 if (tso < 0) {
5877 dev_kfree_skb_any(skb);
5878 return NETDEV_TX_OK;
5879 }
5880
5881 if (tso)
5882 tx_flags |= E1000_TX_FLAGS_TSO;
5883 else if (e1000_tx_csum(tx_ring, skb, protocol))
5884 tx_flags |= E1000_TX_FLAGS_CSUM;
5885
5886
5887
5888
5889
5890 if (protocol == htons(ETH_P_IP))
5891 tx_flags |= E1000_TX_FLAGS_IPV4;
5892
5893 if (unlikely(skb->no_fcs))
5894 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5895
5896
5897 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5898 nr_frags);
5899 if (count) {
5900 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5901 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5902 if (!adapter->tx_hwtstamp_skb) {
5903 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5904 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5905 adapter->tx_hwtstamp_skb = skb_get(skb);
5906 adapter->tx_hwtstamp_start = jiffies;
5907 schedule_work(&adapter->tx_hwtstamp_work);
5908 } else {
5909 adapter->tx_hwtstamp_skipped++;
5910 }
5911 }
5912
5913 skb_tx_timestamp(skb);
5914
5915 netdev_sent_queue(netdev, skb->len);
5916 e1000_tx_queue(tx_ring, tx_flags, count);
5917
5918 e1000_maybe_stop_tx(tx_ring,
5919 (MAX_SKB_FRAGS *
5920 DIV_ROUND_UP(PAGE_SIZE,
5921 adapter->tx_fifo_limit) + 2));
5922
5923 if (!netdev_xmit_more() ||
5924 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5925 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5926 e1000e_update_tdt_wa(tx_ring,
5927 tx_ring->next_to_use);
5928 else
5929 writel(tx_ring->next_to_use, tx_ring->tail);
5930 }
5931 } else {
5932 dev_kfree_skb_any(skb);
5933 tx_ring->buffer_info[first].time_stamp = 0;
5934 tx_ring->next_to_use = first;
5935 }
5936
5937 return NETDEV_TX_OK;
5938}
5939
5940
5941
5942
5943
5944static void e1000_tx_timeout(struct net_device *netdev, unsigned int txqueue)
5945{
5946 struct e1000_adapter *adapter = netdev_priv(netdev);
5947
5948
5949 adapter->tx_timeout_count++;
5950 schedule_work(&adapter->reset_task);
5951}
5952
5953static void e1000_reset_task(struct work_struct *work)
5954{
5955 struct e1000_adapter *adapter;
5956 adapter = container_of(work, struct e1000_adapter, reset_task);
5957
5958
5959 if (test_bit(__E1000_DOWN, &adapter->state))
5960 return;
5961
5962 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5963 e1000e_dump(adapter);
5964 e_err("Reset adapter unexpectedly\n");
5965 }
5966 e1000e_reinit_locked(adapter);
5967}
5968
5969
5970
5971
5972
5973
5974
5975
5976void e1000e_get_stats64(struct net_device *netdev,
5977 struct rtnl_link_stats64 *stats)
5978{
5979 struct e1000_adapter *adapter = netdev_priv(netdev);
5980
5981 spin_lock(&adapter->stats64_lock);
5982 e1000e_update_stats(adapter);
5983
5984 stats->rx_bytes = adapter->stats.gorc;
5985 stats->rx_packets = adapter->stats.gprc;
5986 stats->tx_bytes = adapter->stats.gotc;
5987 stats->tx_packets = adapter->stats.gptc;
5988 stats->multicast = adapter->stats.mprc;
5989 stats->collisions = adapter->stats.colc;
5990
5991
5992
5993
5994
5995
5996 stats->rx_errors = adapter->stats.rxerrc +
5997 adapter->stats.crcerrs + adapter->stats.algnerrc +
5998 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5999 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6000 stats->rx_crc_errors = adapter->stats.crcerrs;
6001 stats->rx_frame_errors = adapter->stats.algnerrc;
6002 stats->rx_missed_errors = adapter->stats.mpc;
6003
6004
6005 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6006 stats->tx_aborted_errors = adapter->stats.ecol;
6007 stats->tx_window_errors = adapter->stats.latecol;
6008 stats->tx_carrier_errors = adapter->stats.tncrs;
6009
6010
6011
6012 spin_unlock(&adapter->stats64_lock);
6013}
6014
6015
6016
6017
6018
6019
6020
6021
6022static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6023{
6024 struct e1000_adapter *adapter = netdev_priv(netdev);
6025 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6026
6027
6028 if ((new_mtu > ETH_DATA_LEN) &&
6029 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6030 e_err("Jumbo Frames not supported.\n");
6031 return -EINVAL;
6032 }
6033
6034
6035 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6036 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6037 (new_mtu > ETH_DATA_LEN)) {
6038 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6039 return -EINVAL;
6040 }
6041
6042 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6043 usleep_range(1000, 1100);
6044
6045 adapter->max_frame_size = max_frame;
6046 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6047 netdev->mtu, new_mtu);
6048 netdev->mtu = new_mtu;
6049
6050 pm_runtime_get_sync(netdev->dev.parent);
6051
6052 if (netif_running(netdev))
6053 e1000e_down(adapter, true);
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063 if (max_frame <= 2048)
6064 adapter->rx_buffer_len = 2048;
6065 else
6066 adapter->rx_buffer_len = 4096;
6067
6068
6069 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6070 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6071
6072 if (netif_running(netdev))
6073 e1000e_up(adapter);
6074 else
6075 e1000e_reset(adapter);
6076
6077 pm_runtime_put_sync(netdev->dev.parent);
6078
6079 clear_bit(__E1000_RESETTING, &adapter->state);
6080
6081 return 0;
6082}
6083
6084static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6085 int cmd)
6086{
6087 struct e1000_adapter *adapter = netdev_priv(netdev);
6088 struct mii_ioctl_data *data = if_mii(ifr);
6089
6090 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6091 return -EOPNOTSUPP;
6092
6093 switch (cmd) {
6094 case SIOCGMIIPHY:
6095 data->phy_id = adapter->hw.phy.addr;
6096 break;
6097 case SIOCGMIIREG:
6098 e1000_phy_read_status(adapter);
6099
6100 switch (data->reg_num & 0x1F) {
6101 case MII_BMCR:
6102 data->val_out = adapter->phy_regs.bmcr;
6103 break;
6104 case MII_BMSR:
6105 data->val_out = adapter->phy_regs.bmsr;
6106 break;
6107 case MII_PHYSID1:
6108 data->val_out = (adapter->hw.phy.id >> 16);
6109 break;
6110 case MII_PHYSID2:
6111 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6112 break;
6113 case MII_ADVERTISE:
6114 data->val_out = adapter->phy_regs.advertise;
6115 break;
6116 case MII_LPA:
6117 data->val_out = adapter->phy_regs.lpa;
6118 break;
6119 case MII_EXPANSION:
6120 data->val_out = adapter->phy_regs.expansion;
6121 break;
6122 case MII_CTRL1000:
6123 data->val_out = adapter->phy_regs.ctrl1000;
6124 break;
6125 case MII_STAT1000:
6126 data->val_out = adapter->phy_regs.stat1000;
6127 break;
6128 case MII_ESTATUS:
6129 data->val_out = adapter->phy_regs.estatus;
6130 break;
6131 default:
6132 return -EIO;
6133 }
6134 break;
6135 case SIOCSMIIREG:
6136 default:
6137 return -EOPNOTSUPP;
6138 }
6139 return 0;
6140}
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6159{
6160 struct e1000_adapter *adapter = netdev_priv(netdev);
6161 struct hwtstamp_config config;
6162 int ret_val;
6163
6164 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6165 return -EFAULT;
6166
6167 ret_val = e1000e_config_hwtstamp(adapter, &config);
6168 if (ret_val)
6169 return ret_val;
6170
6171 switch (config.rx_filter) {
6172 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6173 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6174 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6175 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6176 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6177 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6178
6179
6180
6181
6182
6183 config.rx_filter = HWTSTAMP_FILTER_SOME;
6184 break;
6185 default:
6186 break;
6187 }
6188
6189 return copy_to_user(ifr->ifr_data, &config,
6190 sizeof(config)) ? -EFAULT : 0;
6191}
6192
6193static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6194{
6195 struct e1000_adapter *adapter = netdev_priv(netdev);
6196
6197 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6198 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6199}
6200
6201static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6202{
6203 switch (cmd) {
6204 case SIOCGMIIPHY:
6205 case SIOCGMIIREG:
6206 case SIOCSMIIREG:
6207 return e1000_mii_ioctl(netdev, ifr, cmd);
6208 case SIOCSHWTSTAMP:
6209 return e1000e_hwtstamp_set(netdev, ifr);
6210 case SIOCGHWTSTAMP:
6211 return e1000e_hwtstamp_get(netdev, ifr);
6212 default:
6213 return -EOPNOTSUPP;
6214 }
6215}
6216
6217static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6218{
6219 struct e1000_hw *hw = &adapter->hw;
6220 u32 i, mac_reg, wuc;
6221 u16 phy_reg, wuc_enable;
6222 int retval;
6223
6224
6225 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6226
6227 retval = hw->phy.ops.acquire(hw);
6228 if (retval) {
6229 e_err("Could not acquire PHY\n");
6230 return retval;
6231 }
6232
6233
6234 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6235 if (retval)
6236 goto release;
6237
6238
6239 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6240 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6241 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6242 (u16)(mac_reg & 0xFFFF));
6243 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6244 (u16)((mac_reg >> 16) & 0xFFFF));
6245 }
6246
6247
6248 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6249 mac_reg = er32(RCTL);
6250 if (mac_reg & E1000_RCTL_UPE)
6251 phy_reg |= BM_RCTL_UPE;
6252 if (mac_reg & E1000_RCTL_MPE)
6253 phy_reg |= BM_RCTL_MPE;
6254 phy_reg &= ~(BM_RCTL_MO_MASK);
6255 if (mac_reg & E1000_RCTL_MO_3)
6256 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6257 << BM_RCTL_MO_SHIFT);
6258 if (mac_reg & E1000_RCTL_BAM)
6259 phy_reg |= BM_RCTL_BAM;
6260 if (mac_reg & E1000_RCTL_PMCF)
6261 phy_reg |= BM_RCTL_PMCF;
6262 mac_reg = er32(CTRL);
6263 if (mac_reg & E1000_CTRL_RFCE)
6264 phy_reg |= BM_RCTL_RFCE;
6265 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6266
6267 wuc = E1000_WUC_PME_EN;
6268 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6269 wuc |= E1000_WUC_APME;
6270
6271
6272 ew32(WUFC, wufc);
6273 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6274 E1000_WUC_PME_STATUS | wuc));
6275
6276
6277 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6278 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6279
6280
6281 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6282 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6283 if (retval)
6284 e_err("Could not set PHY Host Wakeup bit\n");
6285release:
6286 hw->phy.ops.release(hw);
6287
6288 return retval;
6289}
6290
6291static void e1000e_flush_lpic(struct pci_dev *pdev)
6292{
6293 struct net_device *netdev = pci_get_drvdata(pdev);
6294 struct e1000_adapter *adapter = netdev_priv(netdev);
6295 struct e1000_hw *hw = &adapter->hw;
6296 u32 ret_val;
6297
6298 pm_runtime_get_sync(netdev->dev.parent);
6299
6300 ret_val = hw->phy.ops.acquire(hw);
6301 if (ret_val)
6302 goto fl_out;
6303
6304 pr_info("EEE TX LPI TIMER: %08X\n",
6305 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6306
6307 hw->phy.ops.release(hw);
6308
6309fl_out:
6310 pm_runtime_put_sync(netdev->dev.parent);
6311}
6312
6313#ifdef CONFIG_PM_SLEEP
6314
6315static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6316{
6317 struct e1000_hw *hw = &adapter->hw;
6318 u32 mac_data;
6319 u16 phy_data;
6320
6321
6322
6323
6324 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6325 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6326 phy_data |= BIT(10);
6327 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6328
6329
6330
6331
6332 e1e_rphy(hw, I217_CGFREG, &phy_data);
6333 phy_data |= BIT(5);
6334 e1e_wphy(hw, I217_CGFREG, phy_data);
6335
6336
6337
6338
6339
6340 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6341 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6342 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6343 mac_data = er32(CTRL_EXT);
6344 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6345 ew32(CTRL_EXT, mac_data);
6346
6347
6348
6349
6350 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6351 phy_data |= BIT(0);
6352 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6353
6354 mac_data = er32(EXTCNF_CTRL);
6355 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6356 ew32(EXTCNF_CTRL, mac_data);
6357
6358
6359
6360
6361
6362 mac_data = er32(TDFH);
6363 if (mac_data)
6364 ew32(TDFH, 0);
6365 mac_data = er32(TDFT);
6366 if (mac_data)
6367 ew32(TDFT, 0);
6368 mac_data = er32(TDFHS);
6369 if (mac_data)
6370 ew32(TDFHS, 0);
6371 mac_data = er32(TDFTS);
6372 if (mac_data)
6373 ew32(TDFTS, 0);
6374 mac_data = er32(TDFPC);
6375 if (mac_data)
6376 ew32(TDFPC, 0);
6377 mac_data = er32(RDFH);
6378 if (mac_data)
6379 ew32(RDFH, 0);
6380 mac_data = er32(RDFT);
6381 if (mac_data)
6382 ew32(RDFT, 0);
6383 mac_data = er32(RDFHS);
6384 if (mac_data)
6385 ew32(RDFHS, 0);
6386 mac_data = er32(RDFTS);
6387 if (mac_data)
6388 ew32(RDFTS, 0);
6389 mac_data = er32(RDFPC);
6390 if (mac_data)
6391 ew32(RDFPC, 0);
6392
6393
6394 mac_data = er32(FEXTNVM7);
6395 mac_data |= BIT(22);
6396 ew32(FEXTNVM7, mac_data);
6397
6398
6399 mac_data = er32(FEXTNVM7);
6400 mac_data |= BIT(31);
6401 mac_data &= ~BIT(0);
6402 ew32(FEXTNVM7, mac_data);
6403
6404
6405 mac_data = er32(CTRL_EXT);
6406 mac_data |= BIT(3);
6407 ew32(CTRL_EXT, mac_data);
6408
6409
6410 mac_data = er32(CTRL_EXT);
6411 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6412 ew32(CTRL_EXT, mac_data);
6413
6414
6415
6416
6417 mac_data = er32(FEXTNVM5);
6418 mac_data |= BIT(7);
6419 ew32(FEXTNVM5, mac_data);
6420}
6421
6422static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6423{
6424 struct e1000_hw *hw = &adapter->hw;
6425 u32 mac_data;
6426 u16 phy_data;
6427
6428
6429 mac_data = er32(FEXTNVM7);
6430 mac_data &= 0xFFBFFFFF;
6431 ew32(FEXTNVM7, mac_data);
6432
6433
6434 mac_data = er32(FEXTNVM7);
6435 mac_data |= BIT(0);
6436 ew32(FEXTNVM7, mac_data);
6437
6438
6439 mac_data = er32(CTRL_EXT);
6440 mac_data &= 0xFFFFFFF7;
6441 ew32(CTRL_EXT, mac_data);
6442
6443
6444 mac_data = er32(CTRL_EXT);
6445 mac_data &= 0xFFF7FFFF;
6446 ew32(CTRL_EXT, mac_data);
6447
6448
6449
6450
6451 mac_data = er32(FEXTNVM5);
6452 mac_data &= 0xFFFFFF7F;
6453 ew32(FEXTNVM5, mac_data);
6454
6455
6456
6457
6458 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6459 phy_data &= 0xFBFF;
6460 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6461 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6462
6463
6464
6465
6466 e1e_rphy(hw, I217_CGFREG, &phy_data);
6467 phy_data &= 0xFFDF;
6468 e1e_wphy(hw, I217_CGFREG, phy_data);
6469
6470
6471
6472
6473
6474 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6475 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6476 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6477 mac_data = er32(CTRL_EXT);
6478 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6479 ew32(CTRL_EXT, mac_data);
6480}
6481#endif
6482
6483static int e1000e_pm_freeze(struct device *dev)
6484{
6485 struct net_device *netdev = dev_get_drvdata(dev);
6486 struct e1000_adapter *adapter = netdev_priv(netdev);
6487 bool present;
6488
6489 rtnl_lock();
6490
6491 present = netif_device_present(netdev);
6492 netif_device_detach(netdev);
6493
6494 if (present && netif_running(netdev)) {
6495 int count = E1000_CHECK_RESET_COUNT;
6496
6497 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6498 usleep_range(10000, 11000);
6499
6500 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6501
6502
6503 e1000e_down(adapter, false);
6504 e1000_free_irq(adapter);
6505 }
6506 rtnl_unlock();
6507
6508 e1000e_reset_interrupt_capability(adapter);
6509
6510
6511 e1000e_disable_pcie_master(&adapter->hw);
6512
6513 return 0;
6514}
6515
6516static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6517{
6518 struct net_device *netdev = pci_get_drvdata(pdev);
6519 struct e1000_adapter *adapter = netdev_priv(netdev);
6520 struct e1000_hw *hw = &adapter->hw;
6521 u32 ctrl, ctrl_ext, rctl, status;
6522
6523 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6524 int retval = 0;
6525
6526 status = er32(STATUS);
6527 if (status & E1000_STATUS_LU)
6528 wufc &= ~E1000_WUFC_LNKC;
6529
6530 if (wufc) {
6531 e1000_setup_rctl(adapter);
6532 e1000e_set_rx_mode(netdev);
6533
6534
6535 if (wufc & E1000_WUFC_MC) {
6536 rctl = er32(RCTL);
6537 rctl |= E1000_RCTL_MPE;
6538 ew32(RCTL, rctl);
6539 }
6540
6541 ctrl = er32(CTRL);
6542 ctrl |= E1000_CTRL_ADVD3WUC;
6543 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6544 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6545 ew32(CTRL, ctrl);
6546
6547 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6548 adapter->hw.phy.media_type ==
6549 e1000_media_type_internal_serdes) {
6550
6551 ctrl_ext = er32(CTRL_EXT);
6552 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6553 ew32(CTRL_EXT, ctrl_ext);
6554 }
6555
6556 if (!runtime)
6557 e1000e_power_up_phy(adapter);
6558
6559 if (adapter->flags & FLAG_IS_ICH)
6560 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6561
6562 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6563
6564 retval = e1000_init_phy_wakeup(adapter, wufc);
6565 if (retval)
6566 return retval;
6567 } else {
6568
6569 ew32(WUFC, wufc);
6570 ew32(WUC, E1000_WUC_PME_EN);
6571 }
6572 } else {
6573 ew32(WUC, 0);
6574 ew32(WUFC, 0);
6575
6576 e1000_power_down_phy(adapter);
6577 }
6578
6579 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6580 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6581 } else if (hw->mac.type >= e1000_pch_lpt) {
6582 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6583
6584
6585
6586 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6587
6588 if (retval)
6589 return retval;
6590 }
6591
6592
6593
6594
6595 if ((hw->phy.type >= e1000_phy_i217) &&
6596 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6597 u16 lpi_ctrl = 0;
6598
6599 retval = hw->phy.ops.acquire(hw);
6600 if (!retval) {
6601 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6602 &lpi_ctrl);
6603 if (!retval) {
6604 if (adapter->eee_advert &
6605 hw->dev_spec.ich8lan.eee_lp_ability &
6606 I82579_EEE_100_SUPPORTED)
6607 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6608 if (adapter->eee_advert &
6609 hw->dev_spec.ich8lan.eee_lp_ability &
6610 I82579_EEE_1000_SUPPORTED)
6611 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6612
6613 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6614 lpi_ctrl);
6615 }
6616 }
6617 hw->phy.ops.release(hw);
6618 }
6619
6620
6621
6622
6623 e1000e_release_hw_control(adapter);
6624
6625 pci_clear_master(pdev);
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6637 struct pci_dev *us_dev = pdev->bus->self;
6638 u16 devctl;
6639
6640 if (!us_dev)
6641 return 0;
6642
6643 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6644 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6645 (devctl & ~PCI_EXP_DEVCTL_CERE));
6646
6647 pci_save_state(pdev);
6648 pci_prepare_to_sleep(pdev);
6649
6650 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6651 }
6652
6653 return 0;
6654}
6655
6656
6657
6658
6659
6660
6661
6662
6663
6664static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6665{
6666 struct pci_dev *parent = pdev->bus->self;
6667 u16 aspm_dis_mask = 0;
6668 u16 pdev_aspmc, parent_aspmc;
6669
6670 switch (state) {
6671 case PCIE_LINK_STATE_L0S:
6672 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6673 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6674
6675 case PCIE_LINK_STATE_L1:
6676 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6677 break;
6678 default:
6679 return;
6680 }
6681
6682 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6683 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6684
6685 if (parent) {
6686 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6687 &parent_aspmc);
6688 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6689 }
6690
6691
6692 if (!(pdev_aspmc & aspm_dis_mask) &&
6693 (!parent || !(parent_aspmc & aspm_dis_mask)))
6694 return;
6695
6696 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6697 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6698 "L0s" : "",
6699 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6700 "L1" : "");
6701
6702#ifdef CONFIG_PCIEASPM
6703 if (locked)
6704 pci_disable_link_state_locked(pdev, state);
6705 else
6706 pci_disable_link_state(pdev, state);
6707
6708
6709
6710
6711
6712 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6713 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6714
6715 if (!(aspm_dis_mask & pdev_aspmc))
6716 return;
6717#endif
6718
6719
6720
6721
6722 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6723
6724 if (parent)
6725 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6726 aspm_dis_mask);
6727}
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6738{
6739 __e1000e_disable_aspm(pdev, state, 0);
6740}
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6751{
6752 __e1000e_disable_aspm(pdev, state, 1);
6753}
6754
6755static int e1000e_pm_thaw(struct device *dev)
6756{
6757 struct net_device *netdev = dev_get_drvdata(dev);
6758 struct e1000_adapter *adapter = netdev_priv(netdev);
6759 int rc = 0;
6760
6761 e1000e_set_interrupt_capability(adapter);
6762
6763 rtnl_lock();
6764 if (netif_running(netdev)) {
6765 rc = e1000_request_irq(adapter);
6766 if (rc)
6767 goto err_irq;
6768
6769 e1000e_up(adapter);
6770 }
6771
6772 netif_device_attach(netdev);
6773err_irq:
6774 rtnl_unlock();
6775
6776 return rc;
6777}
6778
6779#ifdef CONFIG_PM
6780static int __e1000_resume(struct pci_dev *pdev)
6781{
6782 struct net_device *netdev = pci_get_drvdata(pdev);
6783 struct e1000_adapter *adapter = netdev_priv(netdev);
6784 struct e1000_hw *hw = &adapter->hw;
6785 u16 aspm_disable_flag = 0;
6786
6787 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6788 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6789 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6790 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6791 if (aspm_disable_flag)
6792 e1000e_disable_aspm(pdev, aspm_disable_flag);
6793
6794 pci_set_master(pdev);
6795
6796 if (hw->mac.type >= e1000_pch2lan)
6797 e1000_resume_workarounds_pchlan(&adapter->hw);
6798
6799 e1000e_power_up_phy(adapter);
6800
6801
6802 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6803 u16 phy_data;
6804
6805 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6806 if (phy_data) {
6807 e_info("PHY Wakeup cause - %s\n",
6808 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6809 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6810 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6811 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6812 phy_data & E1000_WUS_LNKC ?
6813 "Link Status Change" : "other");
6814 }
6815 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6816 } else {
6817 u32 wus = er32(WUS);
6818
6819 if (wus) {
6820 e_info("MAC Wakeup cause - %s\n",
6821 wus & E1000_WUS_EX ? "Unicast Packet" :
6822 wus & E1000_WUS_MC ? "Multicast Packet" :
6823 wus & E1000_WUS_BC ? "Broadcast Packet" :
6824 wus & E1000_WUS_MAG ? "Magic Packet" :
6825 wus & E1000_WUS_LNKC ? "Link Status Change" :
6826 "other");
6827 }
6828 ew32(WUS, ~0);
6829 }
6830
6831 e1000e_reset(adapter);
6832
6833 e1000_init_manageability_pt(adapter);
6834
6835
6836
6837
6838
6839 if (!(adapter->flags & FLAG_HAS_AMT))
6840 e1000e_get_hw_control(adapter);
6841
6842 return 0;
6843}
6844
6845#ifdef CONFIG_PM_SLEEP
6846static int e1000e_pm_suspend(struct device *dev)
6847{
6848 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6849 struct e1000_adapter *adapter = netdev_priv(netdev);
6850 struct pci_dev *pdev = to_pci_dev(dev);
6851 struct e1000_hw *hw = &adapter->hw;
6852 int rc;
6853
6854 e1000e_flush_lpic(pdev);
6855
6856 e1000e_pm_freeze(dev);
6857
6858 rc = __e1000_shutdown(pdev, false);
6859 if (rc)
6860 e1000e_pm_thaw(dev);
6861
6862
6863 if (hw->mac.type >= e1000_pch_cnp)
6864 e1000e_s0ix_entry_flow(adapter);
6865
6866 return rc;
6867}
6868
6869static int e1000e_pm_resume(struct device *dev)
6870{
6871 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6872 struct e1000_adapter *adapter = netdev_priv(netdev);
6873 struct pci_dev *pdev = to_pci_dev(dev);
6874 struct e1000_hw *hw = &adapter->hw;
6875 int rc;
6876
6877
6878 if (hw->mac.type >= e1000_pch_cnp)
6879 e1000e_s0ix_exit_flow(adapter);
6880
6881 rc = __e1000_resume(pdev);
6882 if (rc)
6883 return rc;
6884
6885 return e1000e_pm_thaw(dev);
6886}
6887#endif
6888
6889static int e1000e_pm_runtime_idle(struct device *dev)
6890{
6891 struct net_device *netdev = dev_get_drvdata(dev);
6892 struct e1000_adapter *adapter = netdev_priv(netdev);
6893 u16 eee_lp;
6894
6895 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6896
6897 if (!e1000e_has_link(adapter)) {
6898 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6899 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6900 }
6901
6902 return -EBUSY;
6903}
6904
6905static int e1000e_pm_runtime_resume(struct device *dev)
6906{
6907 struct pci_dev *pdev = to_pci_dev(dev);
6908 struct net_device *netdev = pci_get_drvdata(pdev);
6909 struct e1000_adapter *adapter = netdev_priv(netdev);
6910 int rc;
6911
6912 rc = __e1000_resume(pdev);
6913 if (rc)
6914 return rc;
6915
6916 if (netdev->flags & IFF_UP)
6917 e1000e_up(adapter);
6918
6919 return rc;
6920}
6921
6922static int e1000e_pm_runtime_suspend(struct device *dev)
6923{
6924 struct pci_dev *pdev = to_pci_dev(dev);
6925 struct net_device *netdev = pci_get_drvdata(pdev);
6926 struct e1000_adapter *adapter = netdev_priv(netdev);
6927
6928 if (netdev->flags & IFF_UP) {
6929 int count = E1000_CHECK_RESET_COUNT;
6930
6931 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6932 usleep_range(10000, 11000);
6933
6934 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6935
6936
6937 e1000e_down(adapter, false);
6938 }
6939
6940 if (__e1000_shutdown(pdev, true)) {
6941 e1000e_pm_runtime_resume(dev);
6942 return -EBUSY;
6943 }
6944
6945 return 0;
6946}
6947#endif
6948
6949static void e1000_shutdown(struct pci_dev *pdev)
6950{
6951 e1000e_flush_lpic(pdev);
6952
6953 e1000e_pm_freeze(&pdev->dev);
6954
6955 __e1000_shutdown(pdev, false);
6956}
6957
6958#ifdef CONFIG_NET_POLL_CONTROLLER
6959
6960static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6961{
6962 struct net_device *netdev = data;
6963 struct e1000_adapter *adapter = netdev_priv(netdev);
6964
6965 if (adapter->msix_entries) {
6966 int vector, msix_irq;
6967
6968 vector = 0;
6969 msix_irq = adapter->msix_entries[vector].vector;
6970 if (disable_hardirq(msix_irq))
6971 e1000_intr_msix_rx(msix_irq, netdev);
6972 enable_irq(msix_irq);
6973
6974 vector++;
6975 msix_irq = adapter->msix_entries[vector].vector;
6976 if (disable_hardirq(msix_irq))
6977 e1000_intr_msix_tx(msix_irq, netdev);
6978 enable_irq(msix_irq);
6979
6980 vector++;
6981 msix_irq = adapter->msix_entries[vector].vector;
6982 if (disable_hardirq(msix_irq))
6983 e1000_msix_other(msix_irq, netdev);
6984 enable_irq(msix_irq);
6985 }
6986
6987 return IRQ_HANDLED;
6988}
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998static void e1000_netpoll(struct net_device *netdev)
6999{
7000 struct e1000_adapter *adapter = netdev_priv(netdev);
7001
7002 switch (adapter->int_mode) {
7003 case E1000E_INT_MODE_MSIX:
7004 e1000_intr_msix(adapter->pdev->irq, netdev);
7005 break;
7006 case E1000E_INT_MODE_MSI:
7007 if (disable_hardirq(adapter->pdev->irq))
7008 e1000_intr_msi(adapter->pdev->irq, netdev);
7009 enable_irq(adapter->pdev->irq);
7010 break;
7011 default:
7012 if (disable_hardirq(adapter->pdev->irq))
7013 e1000_intr(adapter->pdev->irq, netdev);
7014 enable_irq(adapter->pdev->irq);
7015 break;
7016 }
7017}
7018#endif
7019
7020
7021
7022
7023
7024
7025
7026
7027
7028static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7029 pci_channel_state_t state)
7030{
7031 e1000e_pm_freeze(&pdev->dev);
7032
7033 if (state == pci_channel_io_perm_failure)
7034 return PCI_ERS_RESULT_DISCONNECT;
7035
7036 pci_disable_device(pdev);
7037
7038
7039 return PCI_ERS_RESULT_NEED_RESET;
7040}
7041
7042
7043
7044
7045
7046
7047
7048
7049static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7050{
7051 struct net_device *netdev = pci_get_drvdata(pdev);
7052 struct e1000_adapter *adapter = netdev_priv(netdev);
7053 struct e1000_hw *hw = &adapter->hw;
7054 u16 aspm_disable_flag = 0;
7055 int err;
7056 pci_ers_result_t result;
7057
7058 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7059 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7060 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7061 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7062 if (aspm_disable_flag)
7063 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7064
7065 err = pci_enable_device_mem(pdev);
7066 if (err) {
7067 dev_err(&pdev->dev,
7068 "Cannot re-enable PCI device after reset.\n");
7069 result = PCI_ERS_RESULT_DISCONNECT;
7070 } else {
7071 pdev->state_saved = true;
7072 pci_restore_state(pdev);
7073 pci_set_master(pdev);
7074
7075 pci_enable_wake(pdev, PCI_D3hot, 0);
7076 pci_enable_wake(pdev, PCI_D3cold, 0);
7077
7078 e1000e_reset(adapter);
7079 ew32(WUS, ~0);
7080 result = PCI_ERS_RESULT_RECOVERED;
7081 }
7082
7083 return result;
7084}
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094static void e1000_io_resume(struct pci_dev *pdev)
7095{
7096 struct net_device *netdev = pci_get_drvdata(pdev);
7097 struct e1000_adapter *adapter = netdev_priv(netdev);
7098
7099 e1000_init_manageability_pt(adapter);
7100
7101 e1000e_pm_thaw(&pdev->dev);
7102
7103
7104
7105
7106
7107 if (!(adapter->flags & FLAG_HAS_AMT))
7108 e1000e_get_hw_control(adapter);
7109}
7110
7111static void e1000_print_device_info(struct e1000_adapter *adapter)
7112{
7113 struct e1000_hw *hw = &adapter->hw;
7114 struct net_device *netdev = adapter->netdev;
7115 u32 ret_val;
7116 u8 pba_str[E1000_PBANUM_LENGTH];
7117
7118
7119 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7120
7121 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7122 "Width x1"),
7123
7124 netdev->dev_addr);
7125 e_info("Intel(R) PRO/%s Network Connection\n",
7126 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7127 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7128 E1000_PBANUM_LENGTH);
7129 if (ret_val)
7130 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
7131 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7132 hw->mac.type, hw->phy.type, pba_str);
7133}
7134
7135static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7136{
7137 struct e1000_hw *hw = &adapter->hw;
7138 int ret_val;
7139 u16 buf = 0;
7140
7141 if (hw->mac.type != e1000_82573)
7142 return;
7143
7144 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7145 le16_to_cpus(&buf);
7146 if (!ret_val && (!(buf & BIT(0)))) {
7147
7148 dev_warn(&adapter->pdev->dev,
7149 "Warning: detected DSPD enabled in EEPROM\n");
7150 }
7151}
7152
7153static netdev_features_t e1000_fix_features(struct net_device *netdev,
7154 netdev_features_t features)
7155{
7156 struct e1000_adapter *adapter = netdev_priv(netdev);
7157 struct e1000_hw *hw = &adapter->hw;
7158
7159
7160 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7161 features &= ~NETIF_F_RXFCS;
7162
7163
7164
7165
7166 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7167 features |= NETIF_F_HW_VLAN_CTAG_TX;
7168 else
7169 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7170
7171 return features;
7172}
7173
7174static int e1000_set_features(struct net_device *netdev,
7175 netdev_features_t features)
7176{
7177 struct e1000_adapter *adapter = netdev_priv(netdev);
7178 netdev_features_t changed = features ^ netdev->features;
7179
7180 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7181 adapter->flags |= FLAG_TSO_FORCE;
7182
7183 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7184 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7185 NETIF_F_RXALL)))
7186 return 0;
7187
7188 if (changed & NETIF_F_RXFCS) {
7189 if (features & NETIF_F_RXFCS) {
7190 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7191 } else {
7192
7193
7194
7195 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7196 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7197 else
7198 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7199 }
7200 }
7201
7202 netdev->features = features;
7203
7204 if (netif_running(netdev))
7205 e1000e_reinit_locked(adapter);
7206 else
7207 e1000e_reset(adapter);
7208
7209 return 1;
7210}
7211
7212static const struct net_device_ops e1000e_netdev_ops = {
7213 .ndo_open = e1000e_open,
7214 .ndo_stop = e1000e_close,
7215 .ndo_start_xmit = e1000_xmit_frame,
7216 .ndo_get_stats64 = e1000e_get_stats64,
7217 .ndo_set_rx_mode = e1000e_set_rx_mode,
7218 .ndo_set_mac_address = e1000_set_mac,
7219 .ndo_change_mtu = e1000_change_mtu,
7220 .ndo_do_ioctl = e1000_ioctl,
7221 .ndo_tx_timeout = e1000_tx_timeout,
7222 .ndo_validate_addr = eth_validate_addr,
7223
7224 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7225 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7226#ifdef CONFIG_NET_POLL_CONTROLLER
7227 .ndo_poll_controller = e1000_netpoll,
7228#endif
7229 .ndo_set_features = e1000_set_features,
7230 .ndo_fix_features = e1000_fix_features,
7231 .ndo_features_check = passthru_features_check,
7232};
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7246{
7247 struct net_device *netdev;
7248 struct e1000_adapter *adapter;
7249 struct e1000_hw *hw;
7250 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7251 resource_size_t mmio_start, mmio_len;
7252 resource_size_t flash_start, flash_len;
7253 static int cards_found;
7254 u16 aspm_disable_flag = 0;
7255 int bars, i, err, pci_using_dac;
7256 u16 eeprom_data = 0;
7257 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7258 s32 ret_val = 0;
7259
7260 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7261 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7262 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7263 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7264 if (aspm_disable_flag)
7265 e1000e_disable_aspm(pdev, aspm_disable_flag);
7266
7267 err = pci_enable_device_mem(pdev);
7268 if (err)
7269 return err;
7270
7271 pci_using_dac = 0;
7272 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7273 if (!err) {
7274 pci_using_dac = 1;
7275 } else {
7276 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7277 if (err) {
7278 dev_err(&pdev->dev,
7279 "No usable DMA configuration, aborting\n");
7280 goto err_dma;
7281 }
7282 }
7283
7284 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7285 err = pci_request_selected_regions_exclusive(pdev, bars,
7286 e1000e_driver_name);
7287 if (err)
7288 goto err_pci_reg;
7289
7290
7291 pci_enable_pcie_error_reporting(pdev);
7292
7293 pci_set_master(pdev);
7294
7295 err = pci_save_state(pdev);
7296 if (err)
7297 goto err_alloc_etherdev;
7298
7299 err = -ENOMEM;
7300 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7301 if (!netdev)
7302 goto err_alloc_etherdev;
7303
7304 SET_NETDEV_DEV(netdev, &pdev->dev);
7305
7306 netdev->irq = pdev->irq;
7307
7308 pci_set_drvdata(pdev, netdev);
7309 adapter = netdev_priv(netdev);
7310 hw = &adapter->hw;
7311 adapter->netdev = netdev;
7312 adapter->pdev = pdev;
7313 adapter->ei = ei;
7314 adapter->pba = ei->pba;
7315 adapter->flags = ei->flags;
7316 adapter->flags2 = ei->flags2;
7317 adapter->hw.adapter = adapter;
7318 adapter->hw.mac.type = ei->mac;
7319 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7320 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7321
7322 mmio_start = pci_resource_start(pdev, 0);
7323 mmio_len = pci_resource_len(pdev, 0);
7324
7325 err = -EIO;
7326 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7327 if (!adapter->hw.hw_addr)
7328 goto err_ioremap;
7329
7330 if ((adapter->flags & FLAG_HAS_FLASH) &&
7331 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7332 (hw->mac.type < e1000_pch_spt)) {
7333 flash_start = pci_resource_start(pdev, 1);
7334 flash_len = pci_resource_len(pdev, 1);
7335 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7336 if (!adapter->hw.flash_address)
7337 goto err_flashmap;
7338 }
7339
7340
7341 if (adapter->flags2 & FLAG2_HAS_EEE)
7342 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7343
7344
7345 netdev->netdev_ops = &e1000e_netdev_ops;
7346 e1000e_set_ethtool_ops(netdev);
7347 netdev->watchdog_timeo = 5 * HZ;
7348 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7349 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7350
7351 netdev->mem_start = mmio_start;
7352 netdev->mem_end = mmio_start + mmio_len;
7353
7354 adapter->bd_number = cards_found++;
7355
7356 e1000e_check_options(adapter);
7357
7358
7359 err = e1000_sw_init(adapter);
7360 if (err)
7361 goto err_sw_init;
7362
7363 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7364 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7365 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7366
7367 err = ei->get_variants(adapter);
7368 if (err)
7369 goto err_hw_init;
7370
7371 if ((adapter->flags & FLAG_IS_ICH) &&
7372 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7373 (hw->mac.type < e1000_pch_spt))
7374 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7375
7376 hw->mac.ops.get_bus_info(&adapter->hw);
7377
7378 adapter->hw.phy.autoneg_wait_to_complete = 0;
7379
7380
7381 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7382 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7383 adapter->hw.phy.disable_polarity_correction = 0;
7384 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7385 }
7386
7387 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7388 dev_info(&pdev->dev,
7389 "PHY reset is blocked due to SOL/IDER session.\n");
7390
7391
7392 netdev->features = (NETIF_F_SG |
7393 NETIF_F_HW_VLAN_CTAG_RX |
7394 NETIF_F_HW_VLAN_CTAG_TX |
7395 NETIF_F_TSO |
7396 NETIF_F_TSO6 |
7397 NETIF_F_RXHASH |
7398 NETIF_F_RXCSUM |
7399 NETIF_F_HW_CSUM);
7400
7401
7402 netdev->hw_features = netdev->features;
7403 netdev->hw_features |= NETIF_F_RXFCS;
7404 netdev->priv_flags |= IFF_SUPP_NOFCS;
7405 netdev->hw_features |= NETIF_F_RXALL;
7406
7407 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7408 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7409
7410 netdev->vlan_features |= (NETIF_F_SG |
7411 NETIF_F_TSO |
7412 NETIF_F_TSO6 |
7413 NETIF_F_HW_CSUM);
7414
7415 netdev->priv_flags |= IFF_UNICAST_FLT;
7416
7417 if (pci_using_dac) {
7418 netdev->features |= NETIF_F_HIGHDMA;
7419 netdev->vlan_features |= NETIF_F_HIGHDMA;
7420 }
7421
7422
7423 netdev->min_mtu = ETH_MIN_MTU;
7424 netdev->max_mtu = adapter->max_hw_frame_size -
7425 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7426
7427 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7428 adapter->flags |= FLAG_MNG_PT_ENABLED;
7429
7430
7431
7432
7433 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7434
7435
7436
7437
7438 for (i = 0;; i++) {
7439 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7440 break;
7441 if (i == 2) {
7442 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7443 err = -EIO;
7444 goto err_eeprom;
7445 }
7446 }
7447
7448 e1000_eeprom_checks(adapter);
7449
7450
7451 if (e1000e_read_mac_addr(&adapter->hw))
7452 dev_err(&pdev->dev,
7453 "NVM Read Error while reading MAC address\n");
7454
7455 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7456
7457 if (!is_valid_ether_addr(netdev->dev_addr)) {
7458 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7459 netdev->dev_addr);
7460 err = -EIO;
7461 goto err_eeprom;
7462 }
7463
7464 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7465 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7466
7467 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7468 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7469 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7470 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7471 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7472
7473
7474 adapter->hw.mac.autoneg = 1;
7475 adapter->fc_autoneg = true;
7476 adapter->hw.fc.requested_mode = e1000_fc_default;
7477 adapter->hw.fc.current_mode = e1000_fc_default;
7478 adapter->hw.phy.autoneg_advertised = 0x2f;
7479
7480
7481
7482
7483 if (adapter->flags & FLAG_APME_IN_WUC) {
7484
7485 eeprom_data = er32(WUC);
7486 eeprom_apme_mask = E1000_WUC_APME;
7487 if ((hw->mac.type > e1000_ich10lan) &&
7488 (eeprom_data & E1000_WUC_PHY_WAKE))
7489 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7490 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7491 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7492 (adapter->hw.bus.func == 1))
7493 ret_val = e1000_read_nvm(&adapter->hw,
7494 NVM_INIT_CONTROL3_PORT_B,
7495 1, &eeprom_data);
7496 else
7497 ret_val = e1000_read_nvm(&adapter->hw,
7498 NVM_INIT_CONTROL3_PORT_A,
7499 1, &eeprom_data);
7500 }
7501
7502
7503 if (ret_val)
7504 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7505 else if (eeprom_data & eeprom_apme_mask)
7506 adapter->eeprom_wol |= E1000_WUFC_MAG;
7507
7508
7509
7510
7511
7512 if (!(adapter->flags & FLAG_HAS_WOL))
7513 adapter->eeprom_wol = 0;
7514
7515
7516 adapter->wol = adapter->eeprom_wol;
7517
7518
7519 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7520 (hw->mac.ops.check_mng_mode(hw)))
7521 device_wakeup_enable(&pdev->dev);
7522
7523
7524 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7525
7526 if (ret_val) {
7527 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7528 adapter->eeprom_vers = 0;
7529 }
7530
7531
7532 e1000e_ptp_init(adapter);
7533
7534
7535 e1000e_reset(adapter);
7536
7537
7538
7539
7540
7541 if (!(adapter->flags & FLAG_HAS_AMT))
7542 e1000e_get_hw_control(adapter);
7543
7544 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7545 err = register_netdev(netdev);
7546 if (err)
7547 goto err_register;
7548
7549
7550 netif_carrier_off(netdev);
7551
7552 e1000_print_device_info(adapter);
7553
7554 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
7555
7556 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp)
7557 pm_runtime_put_noidle(&pdev->dev);
7558
7559 return 0;
7560
7561err_register:
7562 if (!(adapter->flags & FLAG_HAS_AMT))
7563 e1000e_release_hw_control(adapter);
7564err_eeprom:
7565 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7566 e1000_phy_hw_reset(&adapter->hw);
7567err_hw_init:
7568 kfree(adapter->tx_ring);
7569 kfree(adapter->rx_ring);
7570err_sw_init:
7571 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7572 iounmap(adapter->hw.flash_address);
7573 e1000e_reset_interrupt_capability(adapter);
7574err_flashmap:
7575 iounmap(adapter->hw.hw_addr);
7576err_ioremap:
7577 free_netdev(netdev);
7578err_alloc_etherdev:
7579 pci_release_mem_regions(pdev);
7580err_pci_reg:
7581err_dma:
7582 pci_disable_device(pdev);
7583 return err;
7584}
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595static void e1000_remove(struct pci_dev *pdev)
7596{
7597 struct net_device *netdev = pci_get_drvdata(pdev);
7598 struct e1000_adapter *adapter = netdev_priv(netdev);
7599
7600 e1000e_ptp_remove(adapter);
7601
7602
7603
7604
7605 set_bit(__E1000_DOWN, &adapter->state);
7606 del_timer_sync(&adapter->watchdog_timer);
7607 del_timer_sync(&adapter->phy_info_timer);
7608
7609 cancel_work_sync(&adapter->reset_task);
7610 cancel_work_sync(&adapter->watchdog_task);
7611 cancel_work_sync(&adapter->downshift_task);
7612 cancel_work_sync(&adapter->update_phy_task);
7613 cancel_work_sync(&adapter->print_hang_task);
7614
7615 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7616 cancel_work_sync(&adapter->tx_hwtstamp_work);
7617 if (adapter->tx_hwtstamp_skb) {
7618 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7619 adapter->tx_hwtstamp_skb = NULL;
7620 }
7621 }
7622
7623 unregister_netdev(netdev);
7624
7625 if (pci_dev_run_wake(pdev))
7626 pm_runtime_get_noresume(&pdev->dev);
7627
7628
7629
7630
7631 e1000e_release_hw_control(adapter);
7632
7633 e1000e_reset_interrupt_capability(adapter);
7634 kfree(adapter->tx_ring);
7635 kfree(adapter->rx_ring);
7636
7637 iounmap(adapter->hw.hw_addr);
7638 if ((adapter->hw.flash_address) &&
7639 (adapter->hw.mac.type < e1000_pch_spt))
7640 iounmap(adapter->hw.flash_address);
7641 pci_release_mem_regions(pdev);
7642
7643 free_netdev(netdev);
7644
7645
7646 pci_disable_pcie_error_reporting(pdev);
7647
7648 pci_disable_device(pdev);
7649}
7650
7651
7652static const struct pci_error_handlers e1000_err_handler = {
7653 .error_detected = e1000_io_error_detected,
7654 .slot_reset = e1000_io_slot_reset,
7655 .resume = e1000_io_resume,
7656};
7657
7658static const struct pci_device_id e1000_pci_tbl[] = {
7659 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7660 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7661 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7662 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7663 board_82571 },
7664 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7665 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7666 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7667 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7668 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7669
7670 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7671 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7672 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7673 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7674
7675 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7676 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7677 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7678
7679 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7680 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7681 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7682
7683 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7684 board_80003es2lan },
7685 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7686 board_80003es2lan },
7687 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7688 board_80003es2lan },
7689 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7690 board_80003es2lan },
7691
7692 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7693 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7694 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7695 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7696 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7697 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7698 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7699 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7700
7701 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7702 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7703 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7704 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7705 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7706 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7707 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7708 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7709 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7710
7711 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7712 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7713 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7714
7715 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7716 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7717 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7718
7719 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7720 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7721 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7722 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7723
7724 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7725 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7726
7727 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7728 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7729 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7730 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7731 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7732 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7733 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7734 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7735 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7736 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7737 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7738 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7739 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7740 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7741 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7742 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7743 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7744 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7745 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7746 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7747 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7748 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7749 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7750 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7751 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7752 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7753 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp },
7759 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp },
7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp },
7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp },
7762 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp },
7763
7764 { 0, 0, 0, 0, 0, 0, 0 }
7765};
7766MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7767
7768static const struct dev_pm_ops e1000_pm_ops = {
7769#ifdef CONFIG_PM_SLEEP
7770 .suspend = e1000e_pm_suspend,
7771 .resume = e1000e_pm_resume,
7772 .freeze = e1000e_pm_freeze,
7773 .thaw = e1000e_pm_thaw,
7774 .poweroff = e1000e_pm_suspend,
7775 .restore = e1000e_pm_resume,
7776#endif
7777 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7778 e1000e_pm_runtime_idle)
7779};
7780
7781
7782static struct pci_driver e1000_driver = {
7783 .name = e1000e_driver_name,
7784 .id_table = e1000_pci_tbl,
7785 .probe = e1000_probe,
7786 .remove = e1000_remove,
7787 .driver = {
7788 .pm = &e1000_pm_ops,
7789 },
7790 .shutdown = e1000_shutdown,
7791 .err_handler = &e1000_err_handler
7792};
7793
7794
7795
7796
7797
7798
7799
7800static int __init e1000_init_module(void)
7801{
7802 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7803 e1000e_driver_version);
7804 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7805
7806 return pci_register_driver(&e1000_driver);
7807}
7808module_init(e1000_init_module);
7809
7810
7811
7812
7813
7814
7815
7816static void __exit e1000_exit_module(void)
7817{
7818 pci_unregister_driver(&e1000_driver);
7819}
7820module_exit(e1000_exit_module);
7821
7822MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7823MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7824MODULE_LICENSE("GPL v2");
7825MODULE_VERSION(DRV_VERSION);
7826
7827
7828