1
2
3
4
5
6#include "core.h"
7#include "dp_tx.h"
8#include "debug.h"
9#include "hw.h"
10
11
12static const u8
13ath11k_txq_tcl_ring_map[ATH11K_HW_MAX_QUEUES] = { 0x0, 0x1, 0x2, 0x2 };
14
15static enum hal_tcl_encap_type
16ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
17{
18
19 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
20}
21
22static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
23{
24 struct ieee80211_hdr *hdr = (void *)skb->data;
25 u8 *qos_ctl;
26
27 if (!ieee80211_is_data_qos(hdr->frame_control))
28 return;
29
30 qos_ctl = ieee80211_get_qos_ctl(hdr);
31 memmove(skb->data + IEEE80211_QOS_CTL_LEN,
32 skb->data, (void *)qos_ctl - (void *)skb->data);
33 skb_pull(skb, IEEE80211_QOS_CTL_LEN);
34
35 hdr = (void *)skb->data;
36 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
37}
38
39static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
40{
41 struct ieee80211_hdr *hdr = (void *)skb->data;
42
43 if (!ieee80211_is_data_qos(hdr->frame_control))
44 return HAL_DESC_REO_NON_QOS_TID;
45 else
46 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
47}
48
49static enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
50{
51 switch (cipher) {
52 case WLAN_CIPHER_SUITE_WEP40:
53 return HAL_ENCRYPT_TYPE_WEP_40;
54 case WLAN_CIPHER_SUITE_WEP104:
55 return HAL_ENCRYPT_TYPE_WEP_104;
56 case WLAN_CIPHER_SUITE_TKIP:
57 return HAL_ENCRYPT_TYPE_TKIP_MIC;
58 case WLAN_CIPHER_SUITE_CCMP:
59 return HAL_ENCRYPT_TYPE_CCMP_128;
60 case WLAN_CIPHER_SUITE_CCMP_256:
61 return HAL_ENCRYPT_TYPE_CCMP_256;
62 case WLAN_CIPHER_SUITE_GCMP:
63 return HAL_ENCRYPT_TYPE_GCMP_128;
64 case WLAN_CIPHER_SUITE_GCMP_256:
65 return HAL_ENCRYPT_TYPE_AES_GCMP_256;
66 default:
67 return HAL_ENCRYPT_TYPE_OPEN;
68 }
69}
70
71int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
72 struct sk_buff *skb)
73{
74 struct ath11k_base *ab = ar->ab;
75 struct ath11k_dp *dp = &ab->dp;
76 struct hal_tx_info ti = {0};
77 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
78 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
79 struct hal_srng *tcl_ring;
80 struct ieee80211_hdr *hdr = (void *)skb->data;
81 struct dp_tx_ring *tx_ring;
82 void *hal_tcl_desc;
83 u8 pool_id;
84 u8 hal_ring_id;
85 int ret;
86
87 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
88 return -ESHUTDOWN;
89
90 if (!ieee80211_is_data(hdr->frame_control))
91 return -ENOTSUPP;
92
93 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
94 ti.ring_id = ath11k_txq_tcl_ring_map[pool_id];
95
96 tx_ring = &dp->tx_ring[ti.ring_id];
97
98 spin_lock_bh(&tx_ring->tx_idr_lock);
99 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
100 DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
101 spin_unlock_bh(&tx_ring->tx_idr_lock);
102
103 if (ret < 0)
104 return -ENOSPC;
105
106 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
107 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
108 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
109 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
110 ti.meta_data_flags = arvif->tcl_metadata;
111
112 if (info->control.hw_key)
113 ti.encrypt_type =
114 ath11k_dp_tx_get_encrypt_type(info->control.hw_key->cipher);
115 else
116 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
117
118 ti.addr_search_flags = arvif->hal_addr_search_flags;
119 ti.search_type = arvif->search_type;
120 ti.type = HAL_TCL_DESC_TYPE_BUFFER;
121 ti.pkt_offset = 0;
122 ti.lmac_id = ar->lmac_id;
123 ti.bss_ast_hash = arvif->ast_hash;
124 ti.dscp_tid_tbl_idx = 0;
125
126 if (skb->ip_summed == CHECKSUM_PARTIAL) {
127 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
128 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
129 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
130 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
131 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
132 }
133
134 if (ieee80211_vif_is_mesh(arvif->vif))
135 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1);
136
137 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
138
139 ti.tid = ath11k_dp_tx_get_tid(skb);
140
141 switch (ti.encap_type) {
142 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
143 ath11k_dp_tx_encap_nwifi(skb);
144 break;
145 case HAL_TCL_ENCAP_TYPE_RAW:
146
147
148
149
150 case HAL_TCL_ENCAP_TYPE_ETHERNET:
151 case HAL_TCL_ENCAP_TYPE_802_3:
152
153 ret = -EINVAL;
154 goto fail_remove_idr;
155 }
156
157 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
158 if (dma_mapping_error(ab->dev, ti.paddr)) {
159 ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
160 ret = -ENOMEM;
161 goto fail_remove_idr;
162 }
163
164 ti.data_len = skb->len;
165 skb_cb->paddr = ti.paddr;
166 skb_cb->vif = arvif->vif;
167 skb_cb->ar = ar;
168
169 hal_ring_id = tx_ring->tcl_data_ring.ring_id;
170 tcl_ring = &ab->hal.srng_list[hal_ring_id];
171
172 spin_lock_bh(&tcl_ring->lock);
173
174 ath11k_hal_srng_access_begin(ab, tcl_ring);
175
176 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
177 if (!hal_tcl_desc) {
178
179
180
181
182 ath11k_hal_srng_access_end(ab, tcl_ring);
183 spin_unlock_bh(&tcl_ring->lock);
184 ret = -ENOMEM;
185 goto fail_unmap_dma;
186 }
187
188 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
189 sizeof(struct hal_tlv_hdr), &ti);
190
191 ath11k_hal_srng_access_end(ab, tcl_ring);
192
193 spin_unlock_bh(&tcl_ring->lock);
194
195 atomic_inc(&ar->dp.num_tx_pending);
196
197 return 0;
198
199fail_unmap_dma:
200 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
201
202fail_remove_idr:
203 spin_lock_bh(&tx_ring->tx_idr_lock);
204 idr_remove(&tx_ring->txbuf_idr,
205 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
206 spin_unlock_bh(&tx_ring->tx_idr_lock);
207
208 return ret;
209}
210
211static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
212 int msdu_id,
213 struct dp_tx_ring *tx_ring)
214{
215 struct ath11k *ar;
216 struct sk_buff *msdu;
217 struct ath11k_skb_cb *skb_cb;
218
219 spin_lock_bh(&tx_ring->tx_idr_lock);
220 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
221 if (!msdu) {
222 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
223 msdu_id);
224 spin_unlock_bh(&tx_ring->tx_idr_lock);
225 return;
226 }
227
228 skb_cb = ATH11K_SKB_CB(msdu);
229
230 idr_remove(&tx_ring->txbuf_idr, msdu_id);
231 spin_unlock_bh(&tx_ring->tx_idr_lock);
232
233 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
234 dev_kfree_skb_any(msdu);
235
236 ar = ab->pdevs[mac_id].ar;
237 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
238 wake_up(&ar->dp.tx_empty_waitq);
239}
240
241static void
242ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
243 struct dp_tx_ring *tx_ring,
244 struct ath11k_dp_htt_wbm_tx_status *ts)
245{
246 struct sk_buff *msdu;
247 struct ieee80211_tx_info *info;
248 struct ath11k_skb_cb *skb_cb;
249 struct ath11k *ar;
250
251 spin_lock_bh(&tx_ring->tx_idr_lock);
252 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id);
253 if (!msdu) {
254 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
255 ts->msdu_id);
256 spin_unlock_bh(&tx_ring->tx_idr_lock);
257 return;
258 }
259
260 skb_cb = ATH11K_SKB_CB(msdu);
261 info = IEEE80211_SKB_CB(msdu);
262
263 ar = skb_cb->ar;
264
265 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
266 spin_unlock_bh(&tx_ring->tx_idr_lock);
267
268 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
269 wake_up(&ar->dp.tx_empty_waitq);
270
271 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
272
273 memset(&info->status, 0, sizeof(info->status));
274
275 if (ts->acked) {
276 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
277 info->flags |= IEEE80211_TX_STAT_ACK;
278 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
279 ts->ack_rssi;
280 info->status.is_valid_ack_signal = true;
281 } else {
282 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
283 }
284 }
285
286 ieee80211_tx_status(ar->hw, msdu);
287}
288
289static void
290ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
291 void *desc, u8 mac_id,
292 u32 msdu_id, struct dp_tx_ring *tx_ring)
293{
294 struct htt_tx_wbm_completion *status_desc;
295 struct ath11k_dp_htt_wbm_tx_status ts = {0};
296 enum hal_wbm_htt_tx_comp_status wbm_status;
297
298 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
299
300 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
301 status_desc->info0);
302
303 switch (wbm_status) {
304 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
305 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
306 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
307 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
308 ts.msdu_id = msdu_id;
309 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
310 status_desc->info1);
311 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
312 break;
313 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
314 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
315 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
316 break;
317 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
318
319
320
321 break;
322 default:
323 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
324 break;
325 }
326}
327
328static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
329 struct sk_buff *msdu,
330 struct hal_tx_status *ts)
331{
332 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
333
334 if (ts->try_cnt > 1) {
335 peer_stats->retry_pkts += ts->try_cnt - 1;
336 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
337
338 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
339 peer_stats->failed_pkts += 1;
340 peer_stats->failed_bytes += msdu->len;
341 }
342 }
343}
344
345static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
346 struct sk_buff *msdu,
347 struct hal_tx_status *ts)
348{
349 struct ath11k_base *ab = ar->ab;
350 struct ieee80211_tx_info *info;
351 struct ath11k_skb_cb *skb_cb;
352
353 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
354
355 return;
356 }
357
358 skb_cb = ATH11K_SKB_CB(msdu);
359
360 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
361
362 rcu_read_lock();
363
364 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
365 dev_kfree_skb_any(msdu);
366 goto exit;
367 }
368
369 if (!skb_cb->vif) {
370 dev_kfree_skb_any(msdu);
371 goto exit;
372 }
373
374 info = IEEE80211_SKB_CB(msdu);
375 memset(&info->status, 0, sizeof(info->status));
376
377
378 info->status.rates[0].idx = -1;
379
380 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
381 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
382 info->flags |= IEEE80211_TX_STAT_ACK;
383 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
384 ts->ack_rssi;
385 info->status.is_valid_ack_signal = true;
386 }
387
388 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
389 (info->flags & IEEE80211_TX_CTL_NO_ACK))
390 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
391
392 if (ath11k_debug_is_extd_tx_stats_enabled(ar)) {
393 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
394 if (ar->last_ppdu_id == 0) {
395 ar->last_ppdu_id = ts->ppdu_id;
396 } else if (ar->last_ppdu_id == ts->ppdu_id ||
397 ar->cached_ppdu_id == ar->last_ppdu_id) {
398 ar->cached_ppdu_id = ar->last_ppdu_id;
399 ar->cached_stats.is_ampdu = true;
400 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
401 memset(&ar->cached_stats, 0,
402 sizeof(struct ath11k_per_peer_tx_stats));
403 } else {
404 ar->cached_stats.is_ampdu = false;
405 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
406 memset(&ar->cached_stats, 0,
407 sizeof(struct ath11k_per_peer_tx_stats));
408 }
409 ar->last_ppdu_id = ts->ppdu_id;
410 }
411
412 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
413 }
414
415
416
417
418
419
420 ieee80211_tx_status(ar->hw, msdu);
421
422exit:
423 rcu_read_unlock();
424}
425
426static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
427 struct hal_wbm_release_ring *desc,
428 struct hal_tx_status *ts)
429{
430 ts->buf_rel_source =
431 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
432 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
433 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
434 return;
435
436 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
437 return;
438
439 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
440 desc->info0);
441 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
442 desc->info1);
443 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
444 desc->info1);
445 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
446 desc->info2);
447 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
448 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
449 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
450 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
451 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
452 ts->rate_stats = desc->rate_stats.info0;
453 else
454 ts->rate_stats = 0;
455}
456
457void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
458{
459 struct ath11k *ar;
460 struct ath11k_dp *dp = &ab->dp;
461 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
462 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
463 struct sk_buff *msdu;
464 struct hal_tx_status ts = { 0 };
465 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
466 u32 *desc;
467 u32 msdu_id;
468 u8 mac_id;
469
470 ath11k_hal_srng_access_begin(ab, status_ring);
471
472 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
473 tx_ring->tx_status_tail) &&
474 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
475 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
476 desc, sizeof(struct hal_wbm_release_ring));
477 tx_ring->tx_status_head =
478 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
479 }
480
481 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
482 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
483
484 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
485 }
486
487 ath11k_hal_srng_access_end(ab, status_ring);
488
489 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
490 struct hal_wbm_release_ring *tx_status;
491 u32 desc_id;
492
493 tx_ring->tx_status_tail =
494 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
495 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
496 ath11k_dp_tx_status_parse(ab, tx_status, &ts);
497
498 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
499 tx_status->buf_addr_info.info1);
500 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
501 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
502
503 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
504 ath11k_dp_tx_process_htt_tx_complete(ab,
505 (void *)tx_status,
506 mac_id, msdu_id,
507 tx_ring);
508 continue;
509 }
510
511 spin_lock_bh(&tx_ring->tx_idr_lock);
512 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
513 if (!msdu) {
514 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
515 msdu_id);
516 spin_unlock_bh(&tx_ring->tx_idr_lock);
517 continue;
518 }
519 idr_remove(&tx_ring->txbuf_idr, msdu_id);
520 spin_unlock_bh(&tx_ring->tx_idr_lock);
521
522 ar = ab->pdevs[mac_id].ar;
523
524 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
525 wake_up(&ar->dp.tx_empty_waitq);
526
527 ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
528 }
529}
530
531int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
532 enum hal_reo_cmd_type type,
533 struct ath11k_hal_reo_cmd *cmd,
534 void (*cb)(struct ath11k_dp *, void *,
535 enum hal_reo_cmd_status))
536{
537 struct ath11k_dp *dp = &ab->dp;
538 struct dp_reo_cmd *dp_cmd;
539 struct hal_srng *cmd_ring;
540 int cmd_num;
541
542 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
543 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
544
545
546 if (cmd_num <= 0)
547 return -EINVAL;
548
549 if (!cb)
550 return 0;
551
552
553
554
555
556 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
557
558 if (!dp_cmd)
559 return -ENOMEM;
560
561 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
562 dp_cmd->cmd_num = cmd_num;
563 dp_cmd->handler = cb;
564
565 spin_lock_bh(&dp->reo_cmd_lock);
566 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
567 spin_unlock_bh(&dp->reo_cmd_lock);
568
569 return 0;
570}
571
572static int
573ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
574 int mac_id, u32 ring_id,
575 enum hal_ring_type ring_type,
576 enum htt_srng_ring_type *htt_ring_type,
577 enum htt_srng_ring_id *htt_ring_id)
578{
579 int lmac_ring_id_offset = 0;
580 int ret = 0;
581
582 switch (ring_type) {
583 case HAL_RXDMA_BUF:
584 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
585 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
586 lmac_ring_id_offset) ||
587 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
588 lmac_ring_id_offset))) {
589 ret = -EINVAL;
590 }
591 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
592 *htt_ring_type = HTT_SW_TO_HW_RING;
593 break;
594 case HAL_RXDMA_DST:
595 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
596 *htt_ring_type = HTT_HW_TO_SW_RING;
597 break;
598 case HAL_RXDMA_MONITOR_BUF:
599 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
600 *htt_ring_type = HTT_SW_TO_HW_RING;
601 break;
602 case HAL_RXDMA_MONITOR_STATUS:
603 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
604 *htt_ring_type = HTT_SW_TO_HW_RING;
605 break;
606 case HAL_RXDMA_MONITOR_DST:
607 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
608 *htt_ring_type = HTT_HW_TO_SW_RING;
609 break;
610 case HAL_RXDMA_MONITOR_DESC:
611 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
612 *htt_ring_type = HTT_SW_TO_HW_RING;
613 break;
614 default:
615 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
616 ret = -EINVAL;
617 }
618 return ret;
619}
620
621int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
622 int mac_id, enum hal_ring_type ring_type)
623{
624 struct htt_srng_setup_cmd *cmd;
625 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
626 struct hal_srng_params params;
627 struct sk_buff *skb;
628 u32 ring_entry_sz;
629 int len = sizeof(*cmd);
630 dma_addr_t hp_addr, tp_addr;
631 enum htt_srng_ring_type htt_ring_type;
632 enum htt_srng_ring_id htt_ring_id;
633 int ret;
634
635 skb = ath11k_htc_alloc_skb(ab, len);
636 if (!skb)
637 return -ENOMEM;
638
639 memset(¶ms, 0, sizeof(params));
640 ath11k_hal_srng_get_params(ab, srng, ¶ms);
641
642 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
643 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
644
645 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
646 ring_type, &htt_ring_type,
647 &htt_ring_id);
648 if (ret)
649 goto err_free;
650
651 skb_put(skb, len);
652 cmd = (struct htt_srng_setup_cmd *)skb->data;
653 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
654 HTT_H2T_MSG_TYPE_SRING_SETUP);
655 if (htt_ring_type == HTT_SW_TO_HW_RING ||
656 htt_ring_type == HTT_HW_TO_SW_RING)
657 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
658 DP_SW2HW_MACID(mac_id));
659 else
660 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
661 mac_id);
662 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
663 htt_ring_type);
664 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
665
666 cmd->ring_base_addr_lo = params.ring_base_paddr &
667 HAL_ADDR_LSB_REG_MASK;
668
669 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
670 HAL_ADDR_MSB_REG_SHIFT;
671
672 ret = ath11k_hal_srng_get_entrysize(ring_type);
673 if (ret < 0)
674 goto err_free;
675
676 ring_entry_sz = ret;
677
678 ring_entry_sz >>= 2;
679 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
680 ring_entry_sz);
681 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
682 params.num_entries * ring_entry_sz);
683 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
684 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
685 cmd->info1 |= FIELD_PREP(
686 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
687 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
688 cmd->info1 |= FIELD_PREP(
689 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
690 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
691 if (htt_ring_type == HTT_SW_TO_HW_RING)
692 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
693
694 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
695 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
696 HAL_ADDR_MSB_REG_SHIFT;
697
698 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
699 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
700 HAL_ADDR_MSB_REG_SHIFT;
701
702 cmd->ring_msi_addr_lo = 0;
703 cmd->ring_msi_addr_hi = 0;
704 cmd->msi_data = 0;
705
706 cmd->intr_info = FIELD_PREP(
707 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
708 params.intr_batch_cntr_thres_entries * ring_entry_sz);
709 cmd->intr_info |= FIELD_PREP(
710 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
711 params.intr_timer_thres_us >> 3);
712
713 cmd->info2 = 0;
714 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
715 cmd->info2 = FIELD_PREP(
716 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
717 params.low_threshold);
718 }
719
720 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
721 if (ret)
722 goto err_free;
723
724 return 0;
725
726err_free:
727 dev_kfree_skb_any(skb);
728
729 return ret;
730}
731
732#define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
733
734int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
735{
736 struct ath11k_dp *dp = &ab->dp;
737 struct sk_buff *skb;
738 struct htt_ver_req_cmd *cmd;
739 int len = sizeof(*cmd);
740 int ret;
741
742 init_completion(&dp->htt_tgt_version_received);
743
744 skb = ath11k_htc_alloc_skb(ab, len);
745 if (!skb)
746 return -ENOMEM;
747
748 skb_put(skb, len);
749 cmd = (struct htt_ver_req_cmd *)skb->data;
750 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
751 HTT_H2T_MSG_TYPE_VERSION_REQ);
752
753 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
754 if (ret) {
755 dev_kfree_skb_any(skb);
756 return ret;
757 }
758
759 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
760 HTT_TARGET_VERSION_TIMEOUT_HZ);
761 if (ret == 0) {
762 ath11k_warn(ab, "htt target version request timed out\n");
763 return -ETIMEDOUT;
764 }
765
766 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
767 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
768 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
769 return -ENOTSUPP;
770 }
771
772 return 0;
773}
774
775int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
776{
777 struct ath11k_base *ab = ar->ab;
778 struct ath11k_dp *dp = &ab->dp;
779 struct sk_buff *skb;
780 struct htt_ppdu_stats_cfg_cmd *cmd;
781 int len = sizeof(*cmd);
782 u8 pdev_mask;
783 int ret;
784
785 skb = ath11k_htc_alloc_skb(ab, len);
786 if (!skb)
787 return -ENOMEM;
788
789 skb_put(skb, len);
790 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
791 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
792 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
793
794 pdev_mask = 1 << (ar->pdev_idx);
795 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
796 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
797
798 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
799 if (ret) {
800 dev_kfree_skb_any(skb);
801 return ret;
802 }
803
804 return 0;
805}
806
807int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
808 int mac_id, enum hal_ring_type ring_type,
809 int rx_buf_size,
810 struct htt_rx_ring_tlv_filter *tlv_filter)
811{
812 struct htt_rx_ring_selection_cfg_cmd *cmd;
813 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
814 struct hal_srng_params params;
815 struct sk_buff *skb;
816 int len = sizeof(*cmd);
817 enum htt_srng_ring_type htt_ring_type;
818 enum htt_srng_ring_id htt_ring_id;
819 int ret;
820
821 skb = ath11k_htc_alloc_skb(ab, len);
822 if (!skb)
823 return -ENOMEM;
824
825 memset(¶ms, 0, sizeof(params));
826 ath11k_hal_srng_get_params(ab, srng, ¶ms);
827
828 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
829 ring_type, &htt_ring_type,
830 &htt_ring_id);
831 if (ret)
832 goto err_free;
833
834 skb_put(skb, len);
835 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
836 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
837 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
838 if (htt_ring_type == HTT_SW_TO_HW_RING ||
839 htt_ring_type == HTT_HW_TO_SW_RING)
840 cmd->info0 |=
841 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
842 DP_SW2HW_MACID(mac_id));
843 else
844 cmd->info0 |=
845 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
846 mac_id);
847 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
848 htt_ring_id);
849 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
850 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
851 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
852 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
853
854 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
855 rx_buf_size);
856 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
857 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
858 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
859 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
860 cmd->rx_filter_tlv = tlv_filter->rx_filter;
861
862 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
863 if (ret)
864 goto err_free;
865
866 return 0;
867
868err_free:
869 dev_kfree_skb_any(skb);
870
871 return ret;
872}
873
874int
875ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
876 struct htt_ext_stats_cfg_params *cfg_params,
877 u64 cookie)
878{
879 struct ath11k_base *ab = ar->ab;
880 struct ath11k_dp *dp = &ab->dp;
881 struct sk_buff *skb;
882 struct htt_ext_stats_cfg_cmd *cmd;
883 int len = sizeof(*cmd);
884 int ret;
885
886 skb = ath11k_htc_alloc_skb(ab, len);
887 if (!skb)
888 return -ENOMEM;
889
890 skb_put(skb, len);
891
892 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
893 memset(cmd, 0, sizeof(*cmd));
894 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
895
896 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id;
897
898 cmd->hdr.stats_type = type;
899 cmd->cfg_param0 = cfg_params->cfg0;
900 cmd->cfg_param1 = cfg_params->cfg1;
901 cmd->cfg_param2 = cfg_params->cfg2;
902 cmd->cfg_param3 = cfg_params->cfg3;
903 cmd->cookie_lsb = lower_32_bits(cookie);
904 cmd->cookie_msb = upper_32_bits(cookie);
905
906 ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
907 if (ret) {
908 ath11k_warn(ab, "failed to send htt type stats request: %d",
909 ret);
910 dev_kfree_skb_any(skb);
911 return ret;
912 }
913
914 return 0;
915}
916
917int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
918{
919 struct ath11k_pdev_dp *dp = &ar->dp;
920 struct htt_rx_ring_tlv_filter tlv_filter = {0};
921 int ret = 0, ring_id = 0;
922
923 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
924
925 if (!reset) {
926 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
927 tlv_filter.pkt_filter_flags0 =
928 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
929 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
930 tlv_filter.pkt_filter_flags1 =
931 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
932 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
933 tlv_filter.pkt_filter_flags2 =
934 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
935 HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
936 tlv_filter.pkt_filter_flags3 =
937 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
938 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
939 HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
940 HTT_RX_MON_MO_DATA_FILTER_FLASG3;
941 }
942
943 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
944 HAL_RXDMA_MONITOR_BUF,
945 DP_RXDMA_REFILL_RING_SIZE,
946 &tlv_filter);
947 if (ret)
948 return ret;
949
950 ring_id = dp->rx_mon_status_refill_ring.refill_buf_ring.ring_id;
951 if (!reset)
952 tlv_filter.rx_filter =
953 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
954 else
955 tlv_filter = ath11k_mac_mon_status_filter_default;
956
957 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
958 HAL_RXDMA_MONITOR_STATUS,
959 DP_RXDMA_REFILL_RING_SIZE,
960 &tlv_filter);
961 return ret;
962}
963
