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6#ifndef WIL6210_TXRX_EDMA_H
7#define WIL6210_TXRX_EDMA_H
8
9#include "wil6210.h"
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11
12#define WIL_SRING_SIZE_ORDER_MIN (WIL_RING_SIZE_ORDER_MIN)
13#define WIL_SRING_SIZE_ORDER_MAX (WIL_RING_SIZE_ORDER_MAX)
14
15#define WIL_RX_SRING_SIZE_ORDER_DEFAULT (12)
16#define WIL_TX_SRING_SIZE_ORDER_DEFAULT (14)
17#define WIL_RX_BUFF_ARR_SIZE_DEFAULT (2600)
18
19#define WIL_DEFAULT_RX_STATUS_RING_ID 0
20#define WIL_RX_DESC_RING_ID 0
21#define WIL_RX_STATUS_IRQ_IDX 0
22#define WIL_TX_STATUS_IRQ_IDX 1
23
24#define WIL_EDMA_AGG_WATERMARK (0xffff)
25#define WIL_EDMA_AGG_WATERMARK_POS (16)
26
27#define WIL_EDMA_IDLE_TIME_LIMIT_USEC (50)
28#define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330)
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30
31#define WIL_RX_EDMA_ERROR_MIC (1)
32#define WIL_RX_EDMA_ERROR_KEY (2)
33#define WIL_RX_EDMA_ERROR_REPLAY (3)
34#define WIL_RX_EDMA_ERROR_AMSDU (4)
35#define WIL_RX_EDMA_ERROR_FCS (7)
36
37#define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
38#define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
39
40#define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
41#define WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK 0x7
42#define WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK 0xf
43
44#define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2
45#define WIL_RX_EDMA_DLPF_LU_HIT_CID_POS 4
46
47#define WIL_RX_EDMA_DLPF_LU_MISS_TID_POS 5
48
49#define WIL_RX_EDMA_MID_VALID_BIT BIT(20)
50
51#define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS 16
52#define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_LEN 6
53
54#define WIL_EDMA_DESC_TX_CFG_EOP_POS 0
55#define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
56
57#define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS 3
58#define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2
59
60#define WIL_EDMA_DESC_TX_CFG_SEG_EN_POS 5
61#define WIL_EDMA_DESC_TX_CFG_SEG_EN_LEN 1
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63#define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS 6
64#define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_LEN 1
65
66#define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS 7
67#define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_LEN 1
68
69#define WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS 15
70#define WIL_EDMA_DESC_TX_CFG_L4_TYPE_LEN 1
71
72#define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS 5
73#define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_LEN 1
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83struct wil_ring_rx_enhanced_mac {
84 u32 d[3];
85 __le16 buff_id;
86 u16 reserved;
87} __packed;
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100struct wil_ring_rx_enhanced_dma {
101 u32 d0;
102 struct wil_ring_dma_addr addr;
103 u16 w5;
104 __le16 addr_high_high;
105 __le16 length;
106} __packed;
107
108struct wil_rx_enhanced_desc {
109 struct wil_ring_rx_enhanced_mac mac;
110 struct wil_ring_rx_enhanced_dma dma;
111} __packed;
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128struct wil_ring_tx_enhanced_dma {
129 u8 l4_hdr_len;
130 u8 cmd;
131 u16 w1;
132 struct wil_ring_dma_addr addr;
133 u8 ip_length;
134 u8 b11;
135 __le16 addr_high_high;
136 __le16 length;
137} __packed;
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176struct wil_ring_tx_enhanced_mac {
177 u32 d[3];
178 __le16 tso_mss;
179 u16 scratchpad;
180} __packed;
181
182struct wil_tx_enhanced_desc {
183 struct wil_ring_tx_enhanced_mac mac;
184 struct wil_ring_tx_enhanced_dma dma;
185} __packed;
186
187#define TX_STATUS_DESC_READY_POS 7
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225struct wil_ring_tx_status {
226 u8 num_descriptors;
227 u8 ring_id;
228 u8 status;
229 u8 desc_ready;
230 u32 timestamp;
231 u32 d2;
232 u16 seq_number;
233 u16 w7;
234} __packed;
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286struct wil_rx_status_compressed {
287 u32 d0;
288 u32 d1;
289 __le16 buff_id;
290 __le16 length;
291 u32 timestamp;
292} __packed;
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329struct wil_rx_status_extension {
330 u32 d0;
331 u32 d1;
332 __le16 seq_num;
333 u16 pn_15_0;
334 u32 pn_47_16;
335} __packed;
336
337struct wil_rx_status_extended {
338 struct wil_rx_status_compressed comp;
339 struct wil_rx_status_extension ext;
340} __packed;
341
342static inline void *wil_skb_rxstatus(struct sk_buff *skb)
343{
344 return (void *)skb->cb;
345}
346
347static inline __le16 wil_rx_status_get_length(void *msg)
348{
349 return ((struct wil_rx_status_compressed *)msg)->length;
350}
351
352static inline u8 wil_rx_status_get_mcs(void *msg)
353{
354 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1,
355 16, 21);
356}
357
358static inline u8 wil_rx_status_get_cb_mode(void *msg)
359{
360 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1,
361 22, 23);
362}
363
364static inline u16 wil_rx_status_get_flow_id(void *msg)
365{
366 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
367 8, 19);
368}
369
370static inline u8 wil_rx_status_get_mcast(void *msg)
371{
372 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
373 26, 26);
374}
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386static inline u8 wil_rx_status_get_cid(void *msg)
387{
388 u16 val = wil_rx_status_get_flow_id(msg);
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390 if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT)
391
392 return (val >> WIL_RX_EDMA_DLPF_LU_MISS_CID_POS) &
393 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK;
394 else
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396 return (val >> WIL_RX_EDMA_DLPF_LU_HIT_CID_POS) &
397 WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK;
398}
399
400static inline u8 wil_rx_status_get_tid(void *msg)
401{
402 u16 val = wil_rx_status_get_flow_id(msg);
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404 if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT)
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406 return (val >> WIL_RX_EDMA_DLPF_LU_MISS_TID_POS) &
407 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK;
408 else
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410 return val & WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK;
411}
412
413static inline int wil_rx_status_get_eop(void *msg)
414{
415 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
416 30, 30);
417}
418
419static inline void wil_rx_status_reset_buff_id(struct wil_status_ring *s)
420{
421 ((struct wil_rx_status_compressed *)
422 (s->va + (s->elem_size * s->swhead)))->buff_id = 0;
423}
424
425static inline __le16 wil_rx_status_get_buff_id(void *msg)
426{
427 return ((struct wil_rx_status_compressed *)msg)->buff_id;
428}
429
430static inline u8 wil_rx_status_get_data_offset(void *msg)
431{
432 u8 val = WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1,
433 24, 27);
434
435 switch (val) {
436 case 0: return 0;
437 case 3: return 2;
438 default: return 0xFF;
439 }
440}
441
442static inline int wil_rx_status_get_frame_type(struct wil6210_priv *wil,
443 void *msg)
444{
445 if (wil->use_compressed_rx_status)
446 return IEEE80211_FTYPE_DATA;
447
448 return WIL_GET_BITS(((struct wil_rx_status_extended *)msg)->ext.d1,
449 0, 1) << 2;
450}
451
452static inline int wil_rx_status_get_fc1(struct wil6210_priv *wil, void *msg)
453{
454 if (wil->use_compressed_rx_status)
455 return 0;
456
457 return WIL_GET_BITS(((struct wil_rx_status_extended *)msg)->ext.d1,
458 0, 5) << 2;
459}
460
461static inline __le16 wil_rx_status_get_seq(struct wil6210_priv *wil, void *msg)
462{
463 if (wil->use_compressed_rx_status)
464 return 0;
465
466 return ((struct wil_rx_status_extended *)msg)->ext.seq_num;
467}
468
469static inline u8 wil_rx_status_get_retry(void *msg)
470{
471
472 return 1;
473}
474
475static inline int wil_rx_status_get_mid(void *msg)
476{
477 if (!(((struct wil_rx_status_compressed *)msg)->d0 &
478 WIL_RX_EDMA_MID_VALID_BIT))
479 return 0;
480
481 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
482 21, 22);
483}
484
485static inline int wil_rx_status_get_error(void *msg)
486{
487 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
488 29, 29);
489}
490
491static inline int wil_rx_status_get_l2_rx_status(void *msg)
492{
493 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
494 0, 2);
495}
496
497static inline int wil_rx_status_get_l3_rx_status(void *msg)
498{
499 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
500 3, 4);
501}
502
503static inline int wil_rx_status_get_l4_rx_status(void *msg)
504{
505 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
506 5, 6);
507}
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523static inline int wil_rx_status_get_checksum(void *msg,
524 struct wil_net_stats *stats)
525{
526 int l3_rx_status = wil_rx_status_get_l3_rx_status(msg);
527 int l4_rx_status = wil_rx_status_get_l4_rx_status(msg);
528
529 if (l4_rx_status == 1)
530 return CHECKSUM_UNNECESSARY;
531
532 if (l4_rx_status == 0 && l3_rx_status == 1)
533 return CHECKSUM_UNNECESSARY;
534
535 if (l3_rx_status == 0 && l4_rx_status == 0)
536
537 return CHECKSUM_NONE;
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544 stats->rx_csum_err++;
545 return CHECKSUM_NONE;
546}
547
548static inline int wil_rx_status_get_security(void *msg)
549{
550 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0,
551 28, 28);
552}
553
554static inline u8 wil_rx_status_get_key_id(void *msg)
555{
556 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1,
557 31, 31);
558}
559
560static inline u8 wil_tx_status_get_mcs(struct wil_ring_tx_status *msg)
561{
562 return WIL_GET_BITS(msg->d2, 0, 4);
563}
564
565static inline u32 wil_ring_next_head(struct wil_ring *ring)
566{
567 return (ring->swhead + 1) % ring->size;
568}
569
570static inline void wil_desc_set_addr_edma(struct wil_ring_dma_addr *addr,
571 __le16 *addr_high_high,
572 dma_addr_t pa)
573{
574 addr->addr_low = cpu_to_le32(lower_32_bits(pa));
575 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
576 *addr_high_high = cpu_to_le16((u16)(upper_32_bits(pa) >> 16));
577}
578
579static inline
580dma_addr_t wil_tx_desc_get_addr_edma(struct wil_ring_tx_enhanced_dma *dma)
581{
582 return le32_to_cpu(dma->addr.addr_low) |
583 ((u64)le16_to_cpu(dma->addr.addr_high) << 32) |
584 ((u64)le16_to_cpu(dma->addr_high_high) << 48);
585}
586
587static inline
588dma_addr_t wil_rx_desc_get_addr_edma(struct wil_ring_rx_enhanced_dma *dma)
589{
590 return le32_to_cpu(dma->addr.addr_low) |
591 ((u64)le16_to_cpu(dma->addr.addr_high) << 32) |
592 ((u64)le16_to_cpu(dma->addr_high_high) << 48);
593}
594
595void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil);
596int wil_tx_sring_handler(struct wil6210_priv *wil,
597 struct wil_status_ring *sring);
598void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota);
599void wil_init_txrx_ops_edma(struct wil6210_priv *wil);
600
601#endif
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