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13#include <linux/pci.h>
14#include <linux/slab.h>
15#include <linux/firmware.h>
16#include <linux/etherdevice.h>
17#include <linux/delay.h>
18#include <linux/completion.h>
19#include <linux/module.h>
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "lmac.h"
24#include "p54pci.h"
25
26MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
27MODULE_DESCRIPTION("Prism54 PCI wireless driver");
28MODULE_LICENSE("GPL");
29MODULE_ALIAS("prism54pci");
30MODULE_FIRMWARE("isl3886pci");
31
32static const struct pci_device_id p54p_table[] = {
33
34 { PCI_DEVICE(0x1260, 0x3890) },
35
36 { PCI_DEVICE(0x10b7, 0x6001) },
37
38 { PCI_DEVICE(0x1260, 0x3877) },
39
40 { PCI_DEVICE(0x1260, 0x3886) },
41
42 { PCI_DEVICE(0x1260, 0xffff) },
43 { },
44};
45
46MODULE_DEVICE_TABLE(pci, p54p_table);
47
48static int p54p_upload_firmware(struct ieee80211_hw *dev)
49{
50 struct p54p_priv *priv = dev->priv;
51 __le32 reg;
52 int err;
53 __le32 *data;
54 u32 remains, left, device_addr;
55
56 P54P_WRITE(int_enable, cpu_to_le32(0));
57 P54P_READ(int_enable);
58 udelay(10);
59
60 reg = P54P_READ(ctrl_stat);
61 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
62 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
63 P54P_WRITE(ctrl_stat, reg);
64 P54P_READ(ctrl_stat);
65 udelay(10);
66
67 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
68 P54P_WRITE(ctrl_stat, reg);
69 wmb();
70 udelay(10);
71
72 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
73 P54P_WRITE(ctrl_stat, reg);
74 wmb();
75
76
77 mdelay(10);
78
79 err = p54_parse_firmware(dev, priv->firmware);
80 if (err)
81 return err;
82
83 if (priv->common.fw_interface != FW_LM86) {
84 dev_err(&priv->pdev->dev, "wrong firmware, "
85 "please get a LM86(PCI) firmware a try again.\n");
86 return -EINVAL;
87 }
88
89 data = (__le32 *) priv->firmware->data;
90 remains = priv->firmware->size;
91 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
92 while (remains) {
93 u32 i = 0;
94 left = min((u32)0x1000, remains);
95 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
96 P54P_READ(int_enable);
97
98 device_addr += 0x1000;
99 while (i < left) {
100 P54P_WRITE(direct_mem_win[i], *data++);
101 i += sizeof(u32);
102 }
103
104 remains -= left;
105 P54P_READ(int_enable);
106 }
107
108 reg = P54P_READ(ctrl_stat);
109 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
110 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
111 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
112 P54P_WRITE(ctrl_stat, reg);
113 P54P_READ(ctrl_stat);
114 udelay(10);
115
116 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
117 P54P_WRITE(ctrl_stat, reg);
118 wmb();
119 udelay(10);
120
121 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
122 P54P_WRITE(ctrl_stat, reg);
123 wmb();
124 udelay(10);
125
126
127 mdelay(100);
128
129 return 0;
130}
131
132static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
133 int ring_index, struct p54p_desc *ring, u32 ring_limit,
134 struct sk_buff **rx_buf, u32 index)
135{
136 struct p54p_priv *priv = dev->priv;
137 struct p54p_ring_control *ring_control = priv->ring_control;
138 u32 limit, idx, i;
139
140 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
141 limit = idx;
142 limit -= index;
143 limit = ring_limit - limit;
144
145 i = idx % ring_limit;
146 while (limit-- > 1) {
147 struct p54p_desc *desc = &ring[i];
148
149 if (!desc->host_addr) {
150 struct sk_buff *skb;
151 dma_addr_t mapping;
152 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
153 if (!skb)
154 break;
155
156 mapping = pci_map_single(priv->pdev,
157 skb_tail_pointer(skb),
158 priv->common.rx_mtu + 32,
159 PCI_DMA_FROMDEVICE);
160
161 if (pci_dma_mapping_error(priv->pdev, mapping)) {
162 dev_kfree_skb_any(skb);
163 dev_err(&priv->pdev->dev,
164 "RX DMA Mapping error\n");
165 break;
166 }
167
168 desc->host_addr = cpu_to_le32(mapping);
169 desc->device_addr = 0;
170 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
171 desc->flags = 0;
172 rx_buf[i] = skb;
173 }
174
175 i++;
176 idx++;
177 i %= ring_limit;
178 }
179
180 wmb();
181 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
182}
183
184static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
185 int ring_index, struct p54p_desc *ring, u32 ring_limit,
186 struct sk_buff **rx_buf)
187{
188 struct p54p_priv *priv = dev->priv;
189 struct p54p_ring_control *ring_control = priv->ring_control;
190 struct p54p_desc *desc;
191 u32 idx, i;
192
193 i = (*index) % ring_limit;
194 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
195 idx %= ring_limit;
196 while (i != idx) {
197 u16 len;
198 struct sk_buff *skb;
199 dma_addr_t dma_addr;
200 desc = &ring[i];
201 len = le16_to_cpu(desc->len);
202 skb = rx_buf[i];
203
204 if (!skb) {
205 i++;
206 i %= ring_limit;
207 continue;
208 }
209
210 if (unlikely(len > priv->common.rx_mtu)) {
211 if (net_ratelimit())
212 dev_err(&priv->pdev->dev, "rx'd frame size "
213 "exceeds length threshold.\n");
214
215 len = priv->common.rx_mtu;
216 }
217 dma_addr = le32_to_cpu(desc->host_addr);
218 pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
219 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
220 skb_put(skb, len);
221
222 if (p54_rx(dev, skb)) {
223 pci_unmap_single(priv->pdev, dma_addr,
224 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
225 rx_buf[i] = NULL;
226 desc->host_addr = cpu_to_le32(0);
227 } else {
228 skb_trim(skb, 0);
229 pci_dma_sync_single_for_device(priv->pdev, dma_addr,
230 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
231 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
232 }
233
234 i++;
235 i %= ring_limit;
236 }
237
238 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
239}
240
241static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
242 int ring_index, struct p54p_desc *ring, u32 ring_limit,
243 struct sk_buff **tx_buf)
244{
245 struct p54p_priv *priv = dev->priv;
246 struct p54p_ring_control *ring_control = priv->ring_control;
247 struct p54p_desc *desc;
248 struct sk_buff *skb;
249 u32 idx, i;
250
251 i = (*index) % ring_limit;
252 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
253 idx %= ring_limit;
254
255 while (i != idx) {
256 desc = &ring[i];
257
258 skb = tx_buf[i];
259 tx_buf[i] = NULL;
260
261 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
262 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
263
264 desc->host_addr = 0;
265 desc->device_addr = 0;
266 desc->len = 0;
267 desc->flags = 0;
268
269 if (skb && FREE_AFTER_TX(skb))
270 p54_free_skb(dev, skb);
271
272 i++;
273 i %= ring_limit;
274 }
275}
276
277static void p54p_tasklet(unsigned long dev_id)
278{
279 struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
280 struct p54p_priv *priv = dev->priv;
281 struct p54p_ring_control *ring_control = priv->ring_control;
282
283 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
284 ARRAY_SIZE(ring_control->tx_mgmt),
285 priv->tx_buf_mgmt);
286
287 p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
288 ARRAY_SIZE(ring_control->tx_data),
289 priv->tx_buf_data);
290
291 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
292 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
293
294 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
295 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
296
297 wmb();
298 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
299}
300
301static irqreturn_t p54p_interrupt(int irq, void *dev_id)
302{
303 struct ieee80211_hw *dev = dev_id;
304 struct p54p_priv *priv = dev->priv;
305 __le32 reg;
306
307 reg = P54P_READ(int_ident);
308 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
309 goto out;
310 }
311 P54P_WRITE(int_ack, reg);
312
313 reg &= P54P_READ(int_enable);
314
315 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
316 tasklet_schedule(&priv->tasklet);
317 else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
318 complete(&priv->boot_comp);
319
320out:
321 return reg ? IRQ_HANDLED : IRQ_NONE;
322}
323
324static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
325{
326 unsigned long flags;
327 struct p54p_priv *priv = dev->priv;
328 struct p54p_ring_control *ring_control = priv->ring_control;
329 struct p54p_desc *desc;
330 dma_addr_t mapping;
331 u32 idx, i;
332
333 spin_lock_irqsave(&priv->lock, flags);
334 idx = le32_to_cpu(ring_control->host_idx[1]);
335 i = idx % ARRAY_SIZE(ring_control->tx_data);
336
337 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
338 PCI_DMA_TODEVICE);
339 if (pci_dma_mapping_error(priv->pdev, mapping)) {
340 spin_unlock_irqrestore(&priv->lock, flags);
341 p54_free_skb(dev, skb);
342 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
343 return ;
344 }
345 priv->tx_buf_data[i] = skb;
346
347 desc = &ring_control->tx_data[i];
348 desc->host_addr = cpu_to_le32(mapping);
349 desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
350 desc->len = cpu_to_le16(skb->len);
351 desc->flags = 0;
352
353 wmb();
354 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
355 spin_unlock_irqrestore(&priv->lock, flags);
356
357 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
358 P54P_READ(dev_int);
359}
360
361static void p54p_stop(struct ieee80211_hw *dev)
362{
363 struct p54p_priv *priv = dev->priv;
364 struct p54p_ring_control *ring_control = priv->ring_control;
365 unsigned int i;
366 struct p54p_desc *desc;
367
368 P54P_WRITE(int_enable, cpu_to_le32(0));
369 P54P_READ(int_enable);
370 udelay(10);
371
372 free_irq(priv->pdev->irq, dev);
373
374 tasklet_kill(&priv->tasklet);
375
376 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
377
378 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
379 desc = &ring_control->rx_data[i];
380 if (desc->host_addr)
381 pci_unmap_single(priv->pdev,
382 le32_to_cpu(desc->host_addr),
383 priv->common.rx_mtu + 32,
384 PCI_DMA_FROMDEVICE);
385 kfree_skb(priv->rx_buf_data[i]);
386 priv->rx_buf_data[i] = NULL;
387 }
388
389 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
390 desc = &ring_control->rx_mgmt[i];
391 if (desc->host_addr)
392 pci_unmap_single(priv->pdev,
393 le32_to_cpu(desc->host_addr),
394 priv->common.rx_mtu + 32,
395 PCI_DMA_FROMDEVICE);
396 kfree_skb(priv->rx_buf_mgmt[i]);
397 priv->rx_buf_mgmt[i] = NULL;
398 }
399
400 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
401 desc = &ring_control->tx_data[i];
402 if (desc->host_addr)
403 pci_unmap_single(priv->pdev,
404 le32_to_cpu(desc->host_addr),
405 le16_to_cpu(desc->len),
406 PCI_DMA_TODEVICE);
407
408 p54_free_skb(dev, priv->tx_buf_data[i]);
409 priv->tx_buf_data[i] = NULL;
410 }
411
412 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
413 desc = &ring_control->tx_mgmt[i];
414 if (desc->host_addr)
415 pci_unmap_single(priv->pdev,
416 le32_to_cpu(desc->host_addr),
417 le16_to_cpu(desc->len),
418 PCI_DMA_TODEVICE);
419
420 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
421 priv->tx_buf_mgmt[i] = NULL;
422 }
423
424 memset(ring_control, 0, sizeof(*ring_control));
425}
426
427static int p54p_open(struct ieee80211_hw *dev)
428{
429 struct p54p_priv *priv = dev->priv;
430 int err;
431 long timeout;
432
433 init_completion(&priv->boot_comp);
434 err = request_irq(priv->pdev->irq, p54p_interrupt,
435 IRQF_SHARED, "p54pci", dev);
436 if (err) {
437 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
438 return err;
439 }
440
441 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
442 err = p54p_upload_firmware(dev);
443 if (err) {
444 free_irq(priv->pdev->irq, dev);
445 return err;
446 }
447 priv->rx_idx_data = priv->tx_idx_data = 0;
448 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
449
450 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
451 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
452
453 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
454 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
455
456 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
457 P54P_READ(ring_control_base);
458 wmb();
459 udelay(10);
460
461 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
462 P54P_READ(int_enable);
463 wmb();
464 udelay(10);
465
466 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
467 P54P_READ(dev_int);
468
469 timeout = wait_for_completion_interruptible_timeout(
470 &priv->boot_comp, HZ);
471 if (timeout <= 0) {
472 wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
473 p54p_stop(dev);
474 return timeout ? -ERESTARTSYS : -ETIMEDOUT;
475 }
476
477 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
478 P54P_READ(int_enable);
479 wmb();
480 udelay(10);
481
482 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
483 P54P_READ(dev_int);
484 wmb();
485 udelay(10);
486
487 return 0;
488}
489
490static void p54p_firmware_step2(const struct firmware *fw,
491 void *context)
492{
493 struct p54p_priv *priv = context;
494 struct ieee80211_hw *dev = priv->common.hw;
495 struct pci_dev *pdev = priv->pdev;
496 int err;
497
498 if (!fw) {
499 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
500 err = -ENOENT;
501 goto out;
502 }
503
504 priv->firmware = fw;
505
506 err = p54p_open(dev);
507 if (err)
508 goto out;
509 err = p54_read_eeprom(dev);
510 p54p_stop(dev);
511 if (err)
512 goto out;
513
514 err = p54_register_common(dev, &pdev->dev);
515 if (err)
516 goto out;
517
518out:
519
520 complete(&priv->fw_loaded);
521
522 if (err) {
523 struct device *parent = pdev->dev.parent;
524
525 if (parent)
526 device_lock(parent);
527
528
529
530
531
532
533 device_release_driver(&pdev->dev);
534
535 if (parent)
536 device_unlock(parent);
537 }
538
539 pci_dev_put(pdev);
540}
541
542static int p54p_probe(struct pci_dev *pdev,
543 const struct pci_device_id *id)
544{
545 struct p54p_priv *priv;
546 struct ieee80211_hw *dev;
547 unsigned long mem_addr, mem_len;
548 int err;
549
550 pci_dev_get(pdev);
551 err = pci_enable_device(pdev);
552 if (err) {
553 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
554 goto err_put;
555 }
556
557 mem_addr = pci_resource_start(pdev, 0);
558 mem_len = pci_resource_len(pdev, 0);
559 if (mem_len < sizeof(struct p54p_csr)) {
560 dev_err(&pdev->dev, "Too short PCI resources\n");
561 err = -ENODEV;
562 goto err_disable_dev;
563 }
564
565 err = pci_request_regions(pdev, "p54pci");
566 if (err) {
567 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
568 goto err_disable_dev;
569 }
570
571 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
572 if (!err)
573 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
574 if (err) {
575 dev_err(&pdev->dev, "No suitable DMA available\n");
576 goto err_free_reg;
577 }
578
579 pci_set_master(pdev);
580 pci_try_set_mwi(pdev);
581
582 pci_write_config_byte(pdev, 0x40, 0);
583 pci_write_config_byte(pdev, 0x41, 0);
584
585 dev = p54_init_common(sizeof(*priv));
586 if (!dev) {
587 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
588 err = -ENOMEM;
589 goto err_free_reg;
590 }
591
592 priv = dev->priv;
593 priv->pdev = pdev;
594
595 init_completion(&priv->fw_loaded);
596 SET_IEEE80211_DEV(dev, &pdev->dev);
597 pci_set_drvdata(pdev, dev);
598
599 priv->map = ioremap(mem_addr, mem_len);
600 if (!priv->map) {
601 dev_err(&pdev->dev, "Cannot map device memory\n");
602 err = -ENOMEM;
603 goto err_free_dev;
604 }
605
606 priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
607 &priv->ring_control_dma);
608 if (!priv->ring_control) {
609 dev_err(&pdev->dev, "Cannot allocate rings\n");
610 err = -ENOMEM;
611 goto err_iounmap;
612 }
613 priv->common.open = p54p_open;
614 priv->common.stop = p54p_stop;
615 priv->common.tx = p54p_tx;
616
617 spin_lock_init(&priv->lock);
618 tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
619
620 err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
621 &priv->pdev->dev, GFP_KERNEL,
622 priv, p54p_firmware_step2);
623 if (!err)
624 return 0;
625
626 pci_free_consistent(pdev, sizeof(*priv->ring_control),
627 priv->ring_control, priv->ring_control_dma);
628
629 err_iounmap:
630 iounmap(priv->map);
631
632 err_free_dev:
633 p54_free_common(dev);
634
635 err_free_reg:
636 pci_release_regions(pdev);
637 err_disable_dev:
638 pci_disable_device(pdev);
639err_put:
640 pci_dev_put(pdev);
641 return err;
642}
643
644static void p54p_remove(struct pci_dev *pdev)
645{
646 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
647 struct p54p_priv *priv;
648
649 if (!dev)
650 return;
651
652 priv = dev->priv;
653 wait_for_completion(&priv->fw_loaded);
654 p54_unregister_common(dev);
655 release_firmware(priv->firmware);
656 pci_free_consistent(pdev, sizeof(*priv->ring_control),
657 priv->ring_control, priv->ring_control_dma);
658 iounmap(priv->map);
659 pci_release_regions(pdev);
660 pci_disable_device(pdev);
661 p54_free_common(dev);
662}
663
664#ifdef CONFIG_PM_SLEEP
665static int p54p_suspend(struct device *device)
666{
667 struct pci_dev *pdev = to_pci_dev(device);
668
669 pci_save_state(pdev);
670 pci_set_power_state(pdev, PCI_D3hot);
671 pci_disable_device(pdev);
672 return 0;
673}
674
675static int p54p_resume(struct device *device)
676{
677 struct pci_dev *pdev = to_pci_dev(device);
678 int err;
679
680 err = pci_reenable_device(pdev);
681 if (err)
682 return err;
683 return pci_set_power_state(pdev, PCI_D0);
684}
685
686static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
687
688#define P54P_PM_OPS (&p54pci_pm_ops)
689#else
690#define P54P_PM_OPS (NULL)
691#endif
692
693static struct pci_driver p54p_driver = {
694 .name = "p54pci",
695 .id_table = p54p_table,
696 .probe = p54p_probe,
697 .remove = p54p_remove,
698 .driver.pm = P54P_PM_OPS,
699};
700
701module_pci_driver(p54p_driver);
702
