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6#ifndef __MT76_H
7#define __MT76_H
8
9#include <linux/kernel.h>
10#include <linux/io.h>
11#include <linux/spinlock.h>
12#include <linux/skbuff.h>
13#include <linux/leds.h>
14#include <linux/usb.h>
15#include <linux/average.h>
16#include <net/mac80211.h>
17#include "util.h"
18
19#define MT_TX_RING_SIZE 256
20#define MT_MCU_RING_SIZE 32
21#define MT_RX_BUF_SIZE 2048
22#define MT_SKB_HEAD_LEN 128
23
24struct mt76_dev;
25struct mt76_wcid;
26
27struct mt76_reg_pair {
28 u32 reg;
29 u32 value;
30};
31
32enum mt76_bus_type {
33 MT76_BUS_MMIO,
34 MT76_BUS_USB,
35};
36
37struct mt76_bus_ops {
38 u32 (*rr)(struct mt76_dev *dev, u32 offset);
39 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
40 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
41 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
42 int len);
43 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
44 int len);
45 int (*wr_rp)(struct mt76_dev *dev, u32 base,
46 const struct mt76_reg_pair *rp, int len);
47 int (*rd_rp)(struct mt76_dev *dev, u32 base,
48 struct mt76_reg_pair *rp, int len);
49 enum mt76_bus_type type;
50};
51
52#define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
53#define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
54
55enum mt76_txq_id {
56 MT_TXQ_VO = IEEE80211_AC_VO,
57 MT_TXQ_VI = IEEE80211_AC_VI,
58 MT_TXQ_BE = IEEE80211_AC_BE,
59 MT_TXQ_BK = IEEE80211_AC_BK,
60 MT_TXQ_PSD,
61 MT_TXQ_MCU,
62 MT_TXQ_BEACON,
63 MT_TXQ_CAB,
64 MT_TXQ_FWDL,
65 __MT_TXQ_MAX
66};
67
68enum mt76_rxq_id {
69 MT_RXQ_MAIN,
70 MT_RXQ_MCU,
71 __MT_RXQ_MAX
72};
73
74struct mt76_queue_buf {
75 dma_addr_t addr;
76 int len;
77};
78
79struct mt76_tx_info {
80 struct mt76_queue_buf buf[32];
81 struct sk_buff *skb;
82 int nbuf;
83 u32 info;
84};
85
86struct mt76_queue_entry {
87 union {
88 void *buf;
89 struct sk_buff *skb;
90 };
91 union {
92 struct mt76_txwi_cache *txwi;
93 struct urb *urb;
94 };
95 enum mt76_txq_id qid;
96 bool skip_buf0:1;
97 bool schedule:1;
98 bool done:1;
99};
100
101struct mt76_queue_regs {
102 u32 desc_base;
103 u32 ring_size;
104 u32 cpu_idx;
105 u32 dma_idx;
106} __packed __aligned(4);
107
108struct mt76_queue {
109 struct mt76_queue_regs __iomem *regs;
110
111 spinlock_t lock;
112 struct mt76_queue_entry *entry;
113 struct mt76_desc *desc;
114
115 u16 first;
116 u16 head;
117 u16 tail;
118 int ndesc;
119 int queued;
120 int buf_size;
121 bool stopped;
122
123 u8 buf_offset;
124 u8 hw_idx;
125
126 dma_addr_t desc_dma;
127 struct sk_buff *rx_head;
128 struct page_frag_cache rx_page;
129};
130
131struct mt76_sw_queue {
132 struct mt76_queue *q;
133
134 struct list_head swq;
135 int swq_queued;
136};
137
138struct mt76_mcu_ops {
139 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
140 int len, bool wait_resp);
141 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
142 const struct mt76_reg_pair *rp, int len);
143 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
144 struct mt76_reg_pair *rp, int len);
145 int (*mcu_restart)(struct mt76_dev *dev);
146};
147
148struct mt76_queue_ops {
149 int (*init)(struct mt76_dev *dev);
150
151 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
152 int idx, int n_desc, int bufsize,
153 u32 ring_base);
154
155 int (*tx_queue_skb)(struct mt76_dev *dev, enum mt76_txq_id qid,
156 struct sk_buff *skb, struct mt76_wcid *wcid,
157 struct ieee80211_sta *sta);
158
159 int (*tx_queue_skb_raw)(struct mt76_dev *dev, enum mt76_txq_id qid,
160 struct sk_buff *skb, u32 tx_info);
161
162 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
163 int *len, u32 *info, bool *more);
164
165 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
166
167 void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid,
168 bool flush);
169
170 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
171};
172
173enum mt76_wcid_flags {
174 MT_WCID_FLAG_CHECK_PS,
175 MT_WCID_FLAG_PS,
176};
177
178#define MT76_N_WCIDS 128
179
180DECLARE_EWMA(signal, 10, 8);
181
182#define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
183#define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
184#define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
185#define MT_WCID_TX_INFO_SET BIT(31)
186
187struct mt76_wcid {
188 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
189
190 unsigned long flags;
191
192 struct ewma_signal rssi;
193 int inactive_count;
194
195 u8 idx;
196 u8 hw_key_idx;
197
198 u8 sta:1;
199
200 u8 rx_check_pn;
201 u8 rx_key_pn[IEEE80211_NUM_TIDS][6];
202 u16 cipher;
203
204 u32 tx_info;
205 bool sw_iv;
206
207 u8 packet_id;
208};
209
210struct mt76_txq {
211 struct mt76_sw_queue *swq;
212 struct mt76_wcid *wcid;
213
214 struct sk_buff_head retry_q;
215
216 u16 agg_ssn;
217 bool send_bar;
218 bool aggr;
219};
220
221struct mt76_txwi_cache {
222 struct list_head list;
223 dma_addr_t dma_addr;
224
225 struct sk_buff *skb;
226};
227
228struct mt76_rx_tid {
229 struct rcu_head rcu_head;
230
231 struct mt76_dev *dev;
232
233 spinlock_t lock;
234 struct delayed_work reorder_work;
235
236 u16 head;
237 u8 size;
238 u8 nframes;
239
240 u8 started:1, stopped:1, timer_pending:1;
241
242 struct sk_buff *reorder_buf[];
243};
244
245#define MT_TX_CB_DMA_DONE BIT(0)
246#define MT_TX_CB_TXS_DONE BIT(1)
247#define MT_TX_CB_TXS_FAILED BIT(2)
248
249#define MT_PACKET_ID_MASK GENMASK(6, 0)
250#define MT_PACKET_ID_NO_ACK 0
251#define MT_PACKET_ID_NO_SKB 1
252#define MT_PACKET_ID_FIRST 2
253#define MT_PACKET_ID_HAS_RATE BIT(7)
254
255#define MT_TX_STATUS_SKB_TIMEOUT HZ
256
257struct mt76_tx_cb {
258 unsigned long jiffies;
259 u8 wcid;
260 u8 pktid;
261 u8 flags;
262};
263
264enum {
265 MT76_STATE_INITIALIZED,
266 MT76_STATE_RUNNING,
267 MT76_STATE_MCU_RUNNING,
268 MT76_SCANNING,
269 MT76_RESET,
270 MT76_REMOVED,
271 MT76_READING_STATS,
272};
273
274struct mt76_hw_cap {
275 bool has_2ghz;
276 bool has_5ghz;
277};
278
279#define MT_DRV_TXWI_NO_FREE BIT(0)
280#define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
281#define MT_DRV_SW_RX_AIRTIME BIT(2)
282
283struct mt76_driver_ops {
284 u32 drv_flags;
285 u32 survey_flags;
286 u16 txwi_size;
287
288 void (*update_survey)(struct mt76_dev *dev);
289
290 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
291 enum mt76_txq_id qid, struct mt76_wcid *wcid,
292 struct ieee80211_sta *sta,
293 struct mt76_tx_info *tx_info);
294
295 void (*tx_complete_skb)(struct mt76_dev *dev, enum mt76_txq_id qid,
296 struct mt76_queue_entry *e);
297
298 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
299
300 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
301 struct sk_buff *skb);
302
303 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
304
305 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
306 bool ps);
307
308 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
309 struct ieee80211_sta *sta);
310
311 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif,
312 struct ieee80211_sta *sta);
313
314 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
315 struct ieee80211_sta *sta);
316};
317
318struct mt76_channel_state {
319 u64 cc_active;
320 u64 cc_busy;
321 u64 cc_rx;
322 u64 cc_bss_rx;
323 u64 cc_tx;
324};
325
326struct mt76_sband {
327 struct ieee80211_supported_band sband;
328 struct mt76_channel_state *chan;
329};
330
331struct mt76_rate_power {
332 union {
333 struct {
334 s8 cck[4];
335 s8 ofdm[8];
336 s8 stbc[10];
337 s8 ht[16];
338 s8 vht[10];
339 };
340 s8 all[48];
341 };
342};
343
344
345#define MT_VEND_TYPE_EEPROM BIT(31)
346#define MT_VEND_TYPE_CFG BIT(30)
347#define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
348
349#define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
350enum mt_vendor_req {
351 MT_VEND_DEV_MODE = 0x1,
352 MT_VEND_WRITE = 0x2,
353 MT_VEND_MULTI_WRITE = 0x6,
354 MT_VEND_MULTI_READ = 0x7,
355 MT_VEND_READ_EEPROM = 0x9,
356 MT_VEND_WRITE_FCE = 0x42,
357 MT_VEND_WRITE_CFG = 0x46,
358 MT_VEND_READ_CFG = 0x47,
359};
360
361enum mt76u_in_ep {
362 MT_EP_IN_PKT_RX,
363 MT_EP_IN_CMD_RESP,
364 __MT_EP_IN_MAX,
365};
366
367enum mt76u_out_ep {
368 MT_EP_OUT_INBAND_CMD,
369 MT_EP_OUT_AC_BE,
370 MT_EP_OUT_AC_BK,
371 MT_EP_OUT_AC_VI,
372 MT_EP_OUT_AC_VO,
373 MT_EP_OUT_HCCA,
374 __MT_EP_OUT_MAX,
375};
376
377#define MT_TX_SG_MAX_SIZE 8
378#define MT_RX_SG_MAX_SIZE 1
379#define MT_NUM_TX_ENTRIES 256
380#define MT_NUM_RX_ENTRIES 128
381#define MCU_RESP_URB_SIZE 1024
382struct mt76_usb {
383 struct mutex usb_ctrl_mtx;
384 union {
385 u8 data[32];
386 __le32 reg_val;
387 };
388
389 struct tasklet_struct rx_tasklet;
390 struct workqueue_struct *stat_wq;
391 struct work_struct stat_work;
392
393 u8 out_ep[__MT_EP_OUT_MAX];
394 u8 in_ep[__MT_EP_IN_MAX];
395 bool sg_en;
396
397 struct mt76u_mcu {
398 struct mutex mutex;
399 u8 *data;
400 u32 msg_seq;
401
402
403 struct mt76_reg_pair *rp;
404 int rp_len;
405 u32 base;
406 bool burst;
407 } mcu;
408};
409
410struct mt76_mmio {
411 struct mt76e_mcu {
412 struct mutex mutex;
413
414 wait_queue_head_t wait;
415 struct sk_buff_head res_q;
416
417 u32 msg_seq;
418 } mcu;
419 void __iomem *regs;
420 spinlock_t irq_lock;
421 u32 irqmask;
422};
423
424struct mt76_rx_status {
425 union {
426 struct mt76_wcid *wcid;
427 u8 wcid_idx;
428 };
429
430 unsigned long reorder_time;
431
432 u32 ampdu_ref;
433
434 u8 iv[6];
435
436 u8 aggr:1;
437 u8 tid;
438 u16 seqno;
439
440 u16 freq;
441 u32 flag;
442 u8 enc_flags;
443 u8 encoding:2, bw:3;
444 u8 rate_idx;
445 u8 nss;
446 u8 band;
447 s8 signal;
448 u8 chains;
449 s8 chain_signal[IEEE80211_MAX_CHAINS];
450};
451
452struct mt76_dev {
453 struct ieee80211_hw *hw;
454 struct cfg80211_chan_def chandef;
455 struct ieee80211_channel *main_chan;
456
457 struct mt76_channel_state *chan_state;
458 spinlock_t lock;
459 spinlock_t cc_lock;
460
461 u32 cur_cc_bss_rx;
462
463 struct mt76_rx_status rx_ampdu_status;
464 u32 rx_ampdu_len;
465 u32 rx_ampdu_ref;
466
467 struct mutex mutex;
468
469 const struct mt76_bus_ops *bus;
470 const struct mt76_driver_ops *drv;
471 const struct mt76_mcu_ops *mcu_ops;
472 struct device *dev;
473
474 struct net_device napi_dev;
475 spinlock_t rx_lock;
476 struct napi_struct napi[__MT_RXQ_MAX];
477 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
478 u32 ampdu_ref;
479
480 struct list_head txwi_cache;
481 struct mt76_sw_queue q_tx[__MT_TXQ_MAX];
482 struct mt76_queue q_rx[__MT_RXQ_MAX];
483 const struct mt76_queue_ops *queue_ops;
484 int tx_dma_idx[4];
485
486 struct tasklet_struct tx_tasklet;
487 struct napi_struct tx_napi;
488 struct delayed_work mac_work;
489
490 wait_queue_head_t tx_wait;
491 struct sk_buff_head status_list;
492
493 unsigned long wcid_mask[MT76_N_WCIDS / BITS_PER_LONG];
494
495 struct mt76_wcid global_wcid;
496 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
497
498 u8 macaddr[ETH_ALEN];
499 u32 rev;
500 unsigned long state;
501
502 u32 aggr_stats[32];
503
504 u8 antenna_mask;
505 u16 chainmask;
506
507 struct tasklet_struct pre_tbtt_tasklet;
508 int beacon_int;
509 u8 beacon_mask;
510
511 struct mt76_sband sband_2g;
512 struct mt76_sband sband_5g;
513 struct debugfs_blob_wrapper eeprom;
514 struct debugfs_blob_wrapper otp;
515 struct mt76_hw_cap cap;
516
517 struct mt76_rate_power rate_power;
518 int txpower_conf;
519 int txpower_cur;
520
521 enum nl80211_dfs_regions region;
522
523 u32 debugfs_reg;
524
525 struct led_classdev led_cdev;
526 char led_name[32];
527 bool led_al;
528 u8 led_pin;
529
530 u8 csa_complete;
531
532 ktime_t survey_time;
533
534 u32 rxfilter;
535
536 union {
537 struct mt76_mmio mmio;
538 struct mt76_usb usb;
539 };
540};
541
542enum mt76_phy_type {
543 MT_PHY_TYPE_CCK,
544 MT_PHY_TYPE_OFDM,
545 MT_PHY_TYPE_HT,
546 MT_PHY_TYPE_HT_GF,
547 MT_PHY_TYPE_VHT,
548};
549
550#define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
551#define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
552#define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
553#define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
554#define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
555
556#define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
557#define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
558
559#define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
560#define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
561#define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
562#define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
563#define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
564#define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
565#define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
566
567#define mt76_mcu_send_msg(dev, ...) (dev)->mt76.mcu_ops->mcu_send_msg(&((dev)->mt76), __VA_ARGS__)
568#define __mt76_mcu_send_msg(dev, ...) (dev)->mcu_ops->mcu_send_msg((dev), __VA_ARGS__)
569#define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
570#define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev))
571
572#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
573#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
574
575#define mt76_get_field(_dev, _reg, _field) \
576 FIELD_GET(_field, mt76_rr(dev, _reg))
577
578#define mt76_rmw_field(_dev, _reg, _field, _val) \
579 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
580
581#define __mt76_rmw_field(_dev, _reg, _field, _val) \
582 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
583
584#define mt76_hw(dev) (dev)->mt76.hw
585
586bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
587 int timeout);
588
589#define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
590
591bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
592 int timeout);
593
594#define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
595
596void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
597void mt76_pci_disable_aspm(struct pci_dev *pdev);
598
599static inline u16 mt76_chip(struct mt76_dev *dev)
600{
601 return dev->rev >> 16;
602}
603
604static inline u16 mt76_rev(struct mt76_dev *dev)
605{
606 return dev->rev & 0xffff;
607}
608
609#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
610#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
611
612#define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76))
613#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
614#define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
615#define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
616#define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
617#define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
618#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
619
620struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
621 const struct ieee80211_ops *ops,
622 const struct mt76_driver_ops *drv_ops);
623int mt76_register_device(struct mt76_dev *dev, bool vht,
624 struct ieee80211_rate *rates, int n_rates);
625void mt76_unregister_device(struct mt76_dev *dev);
626void mt76_free_device(struct mt76_dev *dev);
627
628struct dentry *mt76_register_debugfs(struct mt76_dev *dev);
629int mt76_queues_read(struct seq_file *s, void *data);
630void mt76_seq_puts_array(struct seq_file *file, const char *str,
631 s8 *val, int len);
632
633int mt76_eeprom_init(struct mt76_dev *dev, int len);
634void mt76_eeprom_override(struct mt76_dev *dev);
635
636static inline u8 *
637mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
638{
639 return (u8 *)t - dev->drv->txwi_size;
640}
641
642
643static inline int mt76_incr(int val, int size)
644{
645 return (val + 1) & (size - 1);
646}
647
648
649static inline int mt76_decr(int val, int size)
650{
651 return (val - 1) & (size - 1);
652}
653
654u8 mt76_ac_to_hwq(u8 ac);
655
656static inline struct ieee80211_txq *
657mtxq_to_txq(struct mt76_txq *mtxq)
658{
659 void *ptr = mtxq;
660
661 return container_of(ptr, struct ieee80211_txq, drv_priv);
662}
663
664static inline struct ieee80211_sta *
665wcid_to_sta(struct mt76_wcid *wcid)
666{
667 void *ptr = wcid;
668
669 if (!wcid || !wcid->sta)
670 return NULL;
671
672 return container_of(ptr, struct ieee80211_sta, drv_priv);
673}
674
675static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
676{
677 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
678 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
679 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
680}
681
682static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
683{
684 int len = ieee80211_get_hdrlen_from_skb(skb);
685
686 if (len % 4 == 0)
687 return;
688
689 skb_push(skb, 2);
690 memmove(skb->data, skb->data + 2, len);
691
692 skb->data[len] = 0;
693 skb->data[len + 1] = 0;
694}
695
696static inline bool mt76_is_skb_pktid(u8 pktid)
697{
698 if (pktid & MT_PACKET_ID_HAS_RATE)
699 return false;
700
701 return pktid >= MT_PACKET_ID_FIRST;
702}
703
704void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
705void mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta,
706 struct mt76_wcid *wcid, struct sk_buff *skb);
707void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq);
708void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq);
709void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
710void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta,
711 bool send_bar);
712void mt76_txq_schedule(struct mt76_dev *dev, enum mt76_txq_id qid);
713void mt76_txq_schedule_all(struct mt76_dev *dev);
714void mt76_tx_tasklet(unsigned long data);
715void mt76_release_buffered_frames(struct ieee80211_hw *hw,
716 struct ieee80211_sta *sta,
717 u16 tids, int nframes,
718 enum ieee80211_frame_release_type reason,
719 bool more_data);
720bool mt76_has_tx_pending(struct mt76_dev *dev);
721void mt76_set_channel(struct mt76_dev *dev);
722void mt76_update_survey(struct mt76_dev *dev);
723int mt76_get_survey(struct ieee80211_hw *hw, int idx,
724 struct survey_info *survey);
725void mt76_set_stream_caps(struct mt76_dev *dev, bool vht);
726
727int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
728 u16 ssn, u8 size);
729void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
730
731void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
732 struct ieee80211_key_conf *key);
733
734void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
735 __acquires(&dev->status_list.lock);
736void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
737 __releases(&dev->status_list.lock);
738
739int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
740 struct sk_buff *skb);
741struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
742 struct mt76_wcid *wcid, int pktid,
743 struct sk_buff_head *list);
744void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
745 struct sk_buff_head *list);
746void mt76_tx_complete_skb(struct mt76_dev *dev, struct sk_buff *skb);
747void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid,
748 bool flush);
749int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
750 struct ieee80211_sta *sta,
751 enum ieee80211_sta_state old_state,
752 enum ieee80211_sta_state new_state);
753void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,
754 struct ieee80211_sta *sta);
755
756int mt76_get_min_avg_rssi(struct mt76_dev *dev);
757
758int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
759 int *dbm);
760
761void mt76_csa_check(struct mt76_dev *dev);
762void mt76_csa_finish(struct mt76_dev *dev);
763
764int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
765int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
766void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
767int mt76_get_rate(struct mt76_dev *dev,
768 struct ieee80211_supported_band *sband,
769 int idx, bool cck);
770void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
771 const u8 *mac);
772void mt76_sw_scan_complete(struct ieee80211_hw *hw,
773 struct ieee80211_vif *vif);
774u32 mt76_calc_tx_airtime(struct mt76_dev *dev, struct ieee80211_tx_info *info,
775 int len);
776
777
778void mt76_tx_free(struct mt76_dev *dev);
779struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev);
780void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
781void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
782 struct napi_struct *napi);
783void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
784 struct napi_struct *napi);
785void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
786u32 mt76_calc_rx_airtime(struct mt76_dev *dev, struct mt76_rx_status *status,
787 int len);
788
789
790static inline bool mt76u_urb_error(struct urb *urb)
791{
792 return urb->status &&
793 urb->status != -ECONNRESET &&
794 urb->status != -ESHUTDOWN &&
795 urb->status != -ENOENT;
796}
797
798
799static inline u8 q2ep(u8 qid)
800{
801
802 return qid + 1;
803}
804
805static inline int
806mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
807 int timeout)
808{
809 struct usb_interface *uintf = to_usb_interface(dev->dev);
810 struct usb_device *udev = interface_to_usbdev(uintf);
811 struct mt76_usb *usb = &dev->usb;
812 unsigned int pipe;
813
814 if (actual_len)
815 pipe = usb_rcvbulkpipe(udev, usb->in_ep[MT_EP_IN_CMD_RESP]);
816 else
817 pipe = usb_sndbulkpipe(udev, usb->out_ep[MT_EP_OUT_INBAND_CMD]);
818
819 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
820}
821
822int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
823 u8 req_type, u16 val, u16 offset,
824 void *buf, size_t len);
825void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
826 const u16 offset, const u32 val);
827int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
828void mt76u_deinit(struct mt76_dev *dev);
829int mt76u_alloc_queues(struct mt76_dev *dev);
830void mt76u_stop_tx(struct mt76_dev *dev);
831void mt76u_stop_rx(struct mt76_dev *dev);
832int mt76u_resume_rx(struct mt76_dev *dev);
833void mt76u_queues_deinit(struct mt76_dev *dev);
834
835struct sk_buff *
836mt76_mcu_msg_alloc(const void *data, int head_len,
837 int data_len, int tail_len);
838void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
839struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
840 unsigned long expires);
841
842void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
843
844#endif
845