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7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/machine.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/reboot.h>
23#include <linux/pm.h>
24#include <linux/log2.h>
25
26#include <linux/soc/qcom/irq.h>
27
28#include "../core.h"
29#include "../pinconf.h"
30#include "pinctrl-msm.h"
31#include "../pinctrl-utils.h"
32
33#define MAX_NR_GPIO 300
34#define MAX_NR_TILES 4
35#define PS_HOLD_OFFSET 0x820
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52
53struct msm_pinctrl {
54 struct device *dev;
55 struct pinctrl_dev *pctrl;
56 struct gpio_chip chip;
57 struct pinctrl_desc desc;
58 struct notifier_block restart_nb;
59
60 struct irq_chip irq_chip;
61 int irq;
62
63 raw_spinlock_t lock;
64
65 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
66 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
68
69 const struct msm_pinctrl_soc_data *soc;
70 void __iomem *regs[MAX_NR_TILES];
71};
72
73#define MSM_ACCESSOR(name) \
74static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
75 const struct msm_pingroup *g) \
76{ \
77 return readl(pctrl->regs[g->tile] + g->name##_reg); \
78} \
79static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
80 const struct msm_pingroup *g) \
81{ \
82 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
83}
84
85MSM_ACCESSOR(ctl)
86MSM_ACCESSOR(io)
87MSM_ACCESSOR(intr_cfg)
88MSM_ACCESSOR(intr_status)
89MSM_ACCESSOR(intr_target)
90
91static int msm_get_groups_count(struct pinctrl_dev *pctldev)
92{
93 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
94
95 return pctrl->soc->ngroups;
96}
97
98static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
99 unsigned group)
100{
101 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
102
103 return pctrl->soc->groups[group].name;
104}
105
106static int msm_get_group_pins(struct pinctrl_dev *pctldev,
107 unsigned group,
108 const unsigned **pins,
109 unsigned *num_pins)
110{
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112
113 *pins = pctrl->soc->groups[group].pins;
114 *num_pins = pctrl->soc->groups[group].npins;
115 return 0;
116}
117
118static const struct pinctrl_ops msm_pinctrl_ops = {
119 .get_groups_count = msm_get_groups_count,
120 .get_group_name = msm_get_group_name,
121 .get_group_pins = msm_get_group_pins,
122 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
123 .dt_free_map = pinctrl_utils_free_map,
124};
125
126static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
127{
128 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
129 struct gpio_chip *chip = &pctrl->chip;
130
131 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
132}
133
134static int msm_get_functions_count(struct pinctrl_dev *pctldev)
135{
136 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
137
138 return pctrl->soc->nfunctions;
139}
140
141static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
142 unsigned function)
143{
144 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
145
146 return pctrl->soc->functions[function].name;
147}
148
149static int msm_get_function_groups(struct pinctrl_dev *pctldev,
150 unsigned function,
151 const char * const **groups,
152 unsigned * const num_groups)
153{
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
155
156 *groups = pctrl->soc->functions[function].groups;
157 *num_groups = pctrl->soc->functions[function].ngroups;
158 return 0;
159}
160
161static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
162 unsigned function,
163 unsigned group)
164{
165 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
166 const struct msm_pingroup *g;
167 unsigned long flags;
168 u32 val, mask;
169 int i;
170
171 g = &pctrl->soc->groups[group];
172 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
173
174 for (i = 0; i < g->nfuncs; i++) {
175 if (g->funcs[i] == function)
176 break;
177 }
178
179 if (WARN_ON(i == g->nfuncs))
180 return -EINVAL;
181
182 raw_spin_lock_irqsave(&pctrl->lock, flags);
183
184 val = msm_readl_ctl(pctrl, g);
185 val &= ~mask;
186 val |= i << g->mux_bit;
187 msm_writel_ctl(val, pctrl, g);
188
189 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
190
191 return 0;
192}
193
194static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
195 struct pinctrl_gpio_range *range,
196 unsigned offset)
197{
198 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
199 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
200
201
202 if (!g->nfuncs)
203 return 0;
204
205
206 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
207}
208
209static const struct pinmux_ops msm_pinmux_ops = {
210 .request = msm_pinmux_request,
211 .get_functions_count = msm_get_functions_count,
212 .get_function_name = msm_get_function_name,
213 .get_function_groups = msm_get_function_groups,
214 .gpio_request_enable = msm_pinmux_request_gpio,
215 .set_mux = msm_pinmux_set_mux,
216};
217
218static int msm_config_reg(struct msm_pinctrl *pctrl,
219 const struct msm_pingroup *g,
220 unsigned param,
221 unsigned *mask,
222 unsigned *bit)
223{
224 switch (param) {
225 case PIN_CONFIG_BIAS_DISABLE:
226 case PIN_CONFIG_BIAS_PULL_DOWN:
227 case PIN_CONFIG_BIAS_BUS_HOLD:
228 case PIN_CONFIG_BIAS_PULL_UP:
229 *bit = g->pull_bit;
230 *mask = 3;
231 break;
232 case PIN_CONFIG_DRIVE_STRENGTH:
233 *bit = g->drv_bit;
234 *mask = 7;
235 break;
236 case PIN_CONFIG_OUTPUT:
237 case PIN_CONFIG_INPUT_ENABLE:
238 *bit = g->oe_bit;
239 *mask = 1;
240 break;
241 default:
242 return -ENOTSUPP;
243 }
244
245 return 0;
246}
247
248#define MSM_NO_PULL 0
249#define MSM_PULL_DOWN 1
250#define MSM_KEEPER 2
251#define MSM_PULL_UP_NO_KEEPER 2
252#define MSM_PULL_UP 3
253
254static unsigned msm_regval_to_drive(u32 val)
255{
256 return (val + 1) * 2;
257}
258
259static int msm_config_group_get(struct pinctrl_dev *pctldev,
260 unsigned int group,
261 unsigned long *config)
262{
263 const struct msm_pingroup *g;
264 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
265 unsigned param = pinconf_to_config_param(*config);
266 unsigned mask;
267 unsigned arg;
268 unsigned bit;
269 int ret;
270 u32 val;
271
272 g = &pctrl->soc->groups[group];
273
274 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
275 if (ret < 0)
276 return ret;
277
278 val = msm_readl_ctl(pctrl, g);
279 arg = (val >> bit) & mask;
280
281
282 switch (param) {
283 case PIN_CONFIG_BIAS_DISABLE:
284 if (arg != MSM_NO_PULL)
285 return -EINVAL;
286 arg = 1;
287 break;
288 case PIN_CONFIG_BIAS_PULL_DOWN:
289 if (arg != MSM_PULL_DOWN)
290 return -EINVAL;
291 arg = 1;
292 break;
293 case PIN_CONFIG_BIAS_BUS_HOLD:
294 if (pctrl->soc->pull_no_keeper)
295 return -ENOTSUPP;
296
297 if (arg != MSM_KEEPER)
298 return -EINVAL;
299 arg = 1;
300 break;
301 case PIN_CONFIG_BIAS_PULL_UP:
302 if (pctrl->soc->pull_no_keeper)
303 arg = arg == MSM_PULL_UP_NO_KEEPER;
304 else
305 arg = arg == MSM_PULL_UP;
306 if (!arg)
307 return -EINVAL;
308 break;
309 case PIN_CONFIG_DRIVE_STRENGTH:
310 arg = msm_regval_to_drive(arg);
311 break;
312 case PIN_CONFIG_OUTPUT:
313
314 if (!arg)
315 return -EINVAL;
316
317 val = msm_readl_io(pctrl, g);
318 arg = !!(val & BIT(g->in_bit));
319 break;
320 case PIN_CONFIG_INPUT_ENABLE:
321
322 if (arg)
323 return -EINVAL;
324 arg = 1;
325 break;
326 default:
327 return -ENOTSUPP;
328 }
329
330 *config = pinconf_to_config_packed(param, arg);
331
332 return 0;
333}
334
335static int msm_config_group_set(struct pinctrl_dev *pctldev,
336 unsigned group,
337 unsigned long *configs,
338 unsigned num_configs)
339{
340 const struct msm_pingroup *g;
341 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
342 unsigned long flags;
343 unsigned param;
344 unsigned mask;
345 unsigned arg;
346 unsigned bit;
347 int ret;
348 u32 val;
349 int i;
350
351 g = &pctrl->soc->groups[group];
352
353 for (i = 0; i < num_configs; i++) {
354 param = pinconf_to_config_param(configs[i]);
355 arg = pinconf_to_config_argument(configs[i]);
356
357 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
358 if (ret < 0)
359 return ret;
360
361
362 switch (param) {
363 case PIN_CONFIG_BIAS_DISABLE:
364 arg = MSM_NO_PULL;
365 break;
366 case PIN_CONFIG_BIAS_PULL_DOWN:
367 arg = MSM_PULL_DOWN;
368 break;
369 case PIN_CONFIG_BIAS_BUS_HOLD:
370 if (pctrl->soc->pull_no_keeper)
371 return -ENOTSUPP;
372
373 arg = MSM_KEEPER;
374 break;
375 case PIN_CONFIG_BIAS_PULL_UP:
376 if (pctrl->soc->pull_no_keeper)
377 arg = MSM_PULL_UP_NO_KEEPER;
378 else
379 arg = MSM_PULL_UP;
380 break;
381 case PIN_CONFIG_DRIVE_STRENGTH:
382
383 if (arg > 16 || arg < 2 || (arg % 2) != 0)
384 arg = -1;
385 else
386 arg = (arg / 2) - 1;
387 break;
388 case PIN_CONFIG_OUTPUT:
389
390 raw_spin_lock_irqsave(&pctrl->lock, flags);
391 val = msm_readl_io(pctrl, g);
392 if (arg)
393 val |= BIT(g->out_bit);
394 else
395 val &= ~BIT(g->out_bit);
396 msm_writel_io(val, pctrl, g);
397 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
398
399
400 arg = 1;
401 break;
402 case PIN_CONFIG_INPUT_ENABLE:
403
404 arg = 0;
405 break;
406 default:
407 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
408 param);
409 return -EINVAL;
410 }
411
412
413 if (arg & ~mask) {
414 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
415 return -EINVAL;
416 }
417
418 raw_spin_lock_irqsave(&pctrl->lock, flags);
419 val = msm_readl_ctl(pctrl, g);
420 val &= ~(mask << bit);
421 val |= arg << bit;
422 msm_writel_ctl(val, pctrl, g);
423 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
424 }
425
426 return 0;
427}
428
429static const struct pinconf_ops msm_pinconf_ops = {
430 .is_generic = true,
431 .pin_config_group_get = msm_config_group_get,
432 .pin_config_group_set = msm_config_group_set,
433};
434
435static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
436{
437 const struct msm_pingroup *g;
438 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
439 unsigned long flags;
440 u32 val;
441
442 g = &pctrl->soc->groups[offset];
443
444 raw_spin_lock_irqsave(&pctrl->lock, flags);
445
446 val = msm_readl_ctl(pctrl, g);
447 val &= ~BIT(g->oe_bit);
448 msm_writel_ctl(val, pctrl, g);
449
450 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
451
452 return 0;
453}
454
455static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
456{
457 const struct msm_pingroup *g;
458 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
459 unsigned long flags;
460 u32 val;
461
462 g = &pctrl->soc->groups[offset];
463
464 raw_spin_lock_irqsave(&pctrl->lock, flags);
465
466 val = msm_readl_io(pctrl, g);
467 if (value)
468 val |= BIT(g->out_bit);
469 else
470 val &= ~BIT(g->out_bit);
471 msm_writel_io(val, pctrl, g);
472
473 val = msm_readl_ctl(pctrl, g);
474 val |= BIT(g->oe_bit);
475 msm_writel_ctl(val, pctrl, g);
476
477 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
478
479 return 0;
480}
481
482static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
483{
484 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
485 const struct msm_pingroup *g;
486 u32 val;
487
488 g = &pctrl->soc->groups[offset];
489
490 val = msm_readl_ctl(pctrl, g);
491
492
493 return val & BIT(g->oe_bit) ? 0 : 1;
494}
495
496static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
497{
498 const struct msm_pingroup *g;
499 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
500 u32 val;
501
502 g = &pctrl->soc->groups[offset];
503
504 val = msm_readl_io(pctrl, g);
505 return !!(val & BIT(g->in_bit));
506}
507
508static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
509{
510 const struct msm_pingroup *g;
511 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
512 unsigned long flags;
513 u32 val;
514
515 g = &pctrl->soc->groups[offset];
516
517 raw_spin_lock_irqsave(&pctrl->lock, flags);
518
519 val = msm_readl_io(pctrl, g);
520 if (value)
521 val |= BIT(g->out_bit);
522 else
523 val &= ~BIT(g->out_bit);
524 msm_writel_io(val, pctrl, g);
525
526 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
527}
528
529#ifdef CONFIG_DEBUG_FS
530#include <linux/seq_file.h>
531
532static void msm_gpio_dbg_show_one(struct seq_file *s,
533 struct pinctrl_dev *pctldev,
534 struct gpio_chip *chip,
535 unsigned offset,
536 unsigned gpio)
537{
538 const struct msm_pingroup *g;
539 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
540 unsigned func;
541 int is_out;
542 int drive;
543 int pull;
544 int val;
545 u32 ctl_reg, io_reg;
546
547 static const char * const pulls_keeper[] = {
548 "no pull",
549 "pull down",
550 "keeper",
551 "pull up"
552 };
553
554 static const char * const pulls_no_keeper[] = {
555 "no pull",
556 "pull down",
557 "pull up",
558 };
559
560 if (!gpiochip_line_is_valid(chip, offset))
561 return;
562
563 g = &pctrl->soc->groups[offset];
564 ctl_reg = msm_readl_ctl(pctrl, g);
565 io_reg = msm_readl_io(pctrl, g);
566
567 is_out = !!(ctl_reg & BIT(g->oe_bit));
568 func = (ctl_reg >> g->mux_bit) & 7;
569 drive = (ctl_reg >> g->drv_bit) & 7;
570 pull = (ctl_reg >> g->pull_bit) & 3;
571
572 if (is_out)
573 val = !!(io_reg & BIT(g->out_bit));
574 else
575 val = !!(io_reg & BIT(g->in_bit));
576
577 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
578 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
579 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
580 if (pctrl->soc->pull_no_keeper)
581 seq_printf(s, " %s", pulls_no_keeper[pull]);
582 else
583 seq_printf(s, " %s", pulls_keeper[pull]);
584 seq_puts(s, "\n");
585}
586
587static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
588{
589 unsigned gpio = chip->base;
590 unsigned i;
591
592 for (i = 0; i < chip->ngpio; i++, gpio++)
593 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
594}
595
596#else
597#define msm_gpio_dbg_show NULL
598#endif
599
600static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
601 unsigned long *valid_mask,
602 unsigned int ngpios)
603{
604 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
605 int ret;
606 unsigned int len, i;
607 const int *reserved = pctrl->soc->reserved_gpios;
608 u16 *tmp;
609
610
611 if (reserved) {
612 bitmap_fill(valid_mask, ngpios);
613 for (i = 0; reserved[i] >= 0; i++) {
614 if (i >= ngpios || reserved[i] >= ngpios) {
615 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
616 return -EINVAL;
617 }
618 clear_bit(reserved[i], valid_mask);
619 }
620
621 return 0;
622 }
623
624
625 len = ret = device_property_count_u16(pctrl->dev, "gpios");
626 if (ret < 0)
627 return 0;
628
629 if (ret > ngpios)
630 return -EINVAL;
631
632 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
633 if (!tmp)
634 return -ENOMEM;
635
636 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
637 if (ret < 0) {
638 dev_err(pctrl->dev, "could not read list of GPIOs\n");
639 goto out;
640 }
641
642 bitmap_zero(valid_mask, ngpios);
643 for (i = 0; i < len; i++)
644 set_bit(tmp[i], valid_mask);
645
646out:
647 kfree(tmp);
648 return ret;
649}
650
651static const struct gpio_chip msm_gpio_template = {
652 .direction_input = msm_gpio_direction_input,
653 .direction_output = msm_gpio_direction_output,
654 .get_direction = msm_gpio_get_direction,
655 .get = msm_gpio_get,
656 .set = msm_gpio_set,
657 .request = gpiochip_generic_request,
658 .free = gpiochip_generic_free,
659 .dbg_show = msm_gpio_dbg_show,
660};
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682static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
683 const struct msm_pingroup *g,
684 struct irq_data *d)
685{
686 int loop_limit = 100;
687 unsigned val, val2, intstat;
688 unsigned pol;
689
690 do {
691 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
692
693 pol = msm_readl_intr_cfg(pctrl, g);
694 pol ^= BIT(g->intr_polarity_bit);
695 msm_writel_intr_cfg(val, pctrl, g);
696
697 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
698 intstat = msm_readl_intr_status(pctrl, g);
699 if (intstat || (val == val2))
700 return;
701 } while (loop_limit-- > 0);
702 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
703 val, val2);
704}
705
706static void msm_gpio_irq_mask(struct irq_data *d)
707{
708 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
709 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
710 const struct msm_pingroup *g;
711 unsigned long flags;
712 u32 val;
713
714 if (d->parent_data)
715 irq_chip_mask_parent(d);
716
717 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
718 return;
719
720 g = &pctrl->soc->groups[d->hwirq];
721
722 raw_spin_lock_irqsave(&pctrl->lock, flags);
723
724 val = msm_readl_intr_cfg(pctrl, g);
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745 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
746 val &= ~BIT(g->intr_raw_status_bit);
747
748 val &= ~BIT(g->intr_enable_bit);
749 msm_writel_intr_cfg(val, pctrl, g);
750
751 clear_bit(d->hwirq, pctrl->enabled_irqs);
752
753 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
754}
755
756static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
757{
758 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
759 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
760 const struct msm_pingroup *g;
761 unsigned long flags;
762 u32 val;
763
764 if (d->parent_data)
765 irq_chip_unmask_parent(d);
766
767 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
768 return;
769
770 g = &pctrl->soc->groups[d->hwirq];
771
772 raw_spin_lock_irqsave(&pctrl->lock, flags);
773
774 if (status_clear) {
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780 val = msm_readl_intr_status(pctrl, g);
781 val &= ~BIT(g->intr_status_bit);
782 msm_writel_intr_status(val, pctrl, g);
783 }
784
785 val = msm_readl_intr_cfg(pctrl, g);
786 val |= BIT(g->intr_raw_status_bit);
787 val |= BIT(g->intr_enable_bit);
788 msm_writel_intr_cfg(val, pctrl, g);
789
790 set_bit(d->hwirq, pctrl->enabled_irqs);
791
792 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
793}
794
795static void msm_gpio_irq_enable(struct irq_data *d)
796{
797
798
799
800
801
802
803
804
805
806 if (d->parent_data) {
807 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
808 irq_chip_enable_parent(d);
809 }
810
811 msm_gpio_irq_clear_unmask(d, true);
812}
813
814static void msm_gpio_irq_disable(struct irq_data *d)
815{
816 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
817 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
818
819 if (d->parent_data)
820 irq_chip_disable_parent(d);
821
822 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
823 msm_gpio_irq_mask(d);
824}
825
826static void msm_gpio_irq_unmask(struct irq_data *d)
827{
828 msm_gpio_irq_clear_unmask(d, false);
829}
830
831static void msm_gpio_irq_ack(struct irq_data *d)
832{
833 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
834 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
835 const struct msm_pingroup *g;
836 unsigned long flags;
837 u32 val;
838
839 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
840 return;
841
842 g = &pctrl->soc->groups[d->hwirq];
843
844 raw_spin_lock_irqsave(&pctrl->lock, flags);
845
846 val = msm_readl_intr_status(pctrl, g);
847 if (g->intr_ack_high)
848 val |= BIT(g->intr_status_bit);
849 else
850 val &= ~BIT(g->intr_status_bit);
851 msm_writel_intr_status(val, pctrl, g);
852
853 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
854 msm_gpio_update_dual_edge_pos(pctrl, g, d);
855
856 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
857}
858
859static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
860{
861 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
862 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
863 const struct msm_pingroup *g;
864 unsigned long flags;
865 u32 val;
866
867 if (d->parent_data)
868 irq_chip_set_type_parent(d, type);
869
870 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
871 return 0;
872
873 g = &pctrl->soc->groups[d->hwirq];
874
875 raw_spin_lock_irqsave(&pctrl->lock, flags);
876
877
878
879
880 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
881 set_bit(d->hwirq, pctrl->dual_edge_irqs);
882 else
883 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
884
885
886 val = msm_readl_intr_target(pctrl, g);
887 val &= ~(7 << g->intr_target_bit);
888 val |= g->intr_target_kpss_val << g->intr_target_bit;
889 msm_writel_intr_target(val, pctrl, g);
890
891
892
893
894
895
896 val = msm_readl_intr_cfg(pctrl, g);
897 val |= BIT(g->intr_raw_status_bit);
898 if (g->intr_detection_width == 2) {
899 val &= ~(3 << g->intr_detection_bit);
900 val &= ~(1 << g->intr_polarity_bit);
901 switch (type) {
902 case IRQ_TYPE_EDGE_RISING:
903 val |= 1 << g->intr_detection_bit;
904 val |= BIT(g->intr_polarity_bit);
905 break;
906 case IRQ_TYPE_EDGE_FALLING:
907 val |= 2 << g->intr_detection_bit;
908 val |= BIT(g->intr_polarity_bit);
909 break;
910 case IRQ_TYPE_EDGE_BOTH:
911 val |= 3 << g->intr_detection_bit;
912 val |= BIT(g->intr_polarity_bit);
913 break;
914 case IRQ_TYPE_LEVEL_LOW:
915 break;
916 case IRQ_TYPE_LEVEL_HIGH:
917 val |= BIT(g->intr_polarity_bit);
918 break;
919 }
920 } else if (g->intr_detection_width == 1) {
921 val &= ~(1 << g->intr_detection_bit);
922 val &= ~(1 << g->intr_polarity_bit);
923 switch (type) {
924 case IRQ_TYPE_EDGE_RISING:
925 val |= BIT(g->intr_detection_bit);
926 val |= BIT(g->intr_polarity_bit);
927 break;
928 case IRQ_TYPE_EDGE_FALLING:
929 val |= BIT(g->intr_detection_bit);
930 break;
931 case IRQ_TYPE_EDGE_BOTH:
932 val |= BIT(g->intr_detection_bit);
933 val |= BIT(g->intr_polarity_bit);
934 break;
935 case IRQ_TYPE_LEVEL_LOW:
936 break;
937 case IRQ_TYPE_LEVEL_HIGH:
938 val |= BIT(g->intr_polarity_bit);
939 break;
940 }
941 } else {
942 BUG();
943 }
944 msm_writel_intr_cfg(val, pctrl, g);
945
946 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
947 msm_gpio_update_dual_edge_pos(pctrl, g, d);
948
949 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
950
951 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
952 irq_set_handler_locked(d, handle_level_irq);
953 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
954 irq_set_handler_locked(d, handle_edge_irq);
955
956 return 0;
957}
958
959static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
960{
961 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
963
964
965
966
967
968
969
970 if (d->parent_data)
971 irq_chip_set_wake_parent(d, on);
972
973 irq_set_irq_wake(pctrl->irq, on);
974
975 return 0;
976}
977
978static int msm_gpio_irq_reqres(struct irq_data *d)
979{
980 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
981 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
982 int ret;
983
984 if (!try_module_get(gc->owner))
985 return -ENODEV;
986
987 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
988 if (ret)
989 goto out;
990 msm_gpio_direction_input(gc, d->hwirq);
991
992 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
993 dev_err(gc->parent,
994 "unable to lock HW IRQ %lu for IRQ\n",
995 d->hwirq);
996 ret = -EINVAL;
997 goto out;
998 }
999 return 0;
1000out:
1001 module_put(gc->owner);
1002 return ret;
1003}
1004
1005static void msm_gpio_irq_relres(struct irq_data *d)
1006{
1007 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1008
1009 gpiochip_unlock_as_irq(gc, d->hwirq);
1010 module_put(gc->owner);
1011}
1012
1013static void msm_gpio_irq_handler(struct irq_desc *desc)
1014{
1015 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1016 const struct msm_pingroup *g;
1017 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1018 struct irq_chip *chip = irq_desc_get_chip(desc);
1019 int irq_pin;
1020 int handled = 0;
1021 u32 val;
1022 int i;
1023
1024 chained_irq_enter(chip, desc);
1025
1026
1027
1028
1029
1030 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1031 g = &pctrl->soc->groups[i];
1032 val = msm_readl_intr_status(pctrl, g);
1033 if (val & BIT(g->intr_status_bit)) {
1034 irq_pin = irq_find_mapping(gc->irq.domain, i);
1035 generic_handle_irq(irq_pin);
1036 handled++;
1037 }
1038 }
1039
1040
1041 if (handled == 0)
1042 handle_bad_irq(desc);
1043
1044 chained_irq_exit(chip, desc);
1045}
1046
1047static int msm_gpio_wakeirq(struct gpio_chip *gc,
1048 unsigned int child,
1049 unsigned int child_type,
1050 unsigned int *parent,
1051 unsigned int *parent_type)
1052{
1053 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1054 const struct msm_gpio_wakeirq_map *map;
1055 int i;
1056
1057 *parent = GPIO_NO_WAKE_IRQ;
1058 *parent_type = IRQ_TYPE_EDGE_RISING;
1059
1060 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1061 map = &pctrl->soc->wakeirq_map[i];
1062 if (map->gpio == child) {
1063 *parent = map->wakeirq;
1064 break;
1065 }
1066 }
1067
1068 return 0;
1069}
1070
1071static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1072{
1073 if (pctrl->soc->reserved_gpios)
1074 return true;
1075
1076 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1077}
1078
1079static int msm_gpio_init(struct msm_pinctrl *pctrl)
1080{
1081 struct gpio_chip *chip;
1082 struct gpio_irq_chip *girq;
1083 int i, ret;
1084 unsigned gpio, ngpio = pctrl->soc->ngpios;
1085 struct device_node *np;
1086 bool skip;
1087
1088 if (WARN_ON(ngpio > MAX_NR_GPIO))
1089 return -EINVAL;
1090
1091 chip = &pctrl->chip;
1092 chip->base = -1;
1093 chip->ngpio = ngpio;
1094 chip->label = dev_name(pctrl->dev);
1095 chip->parent = pctrl->dev;
1096 chip->owner = THIS_MODULE;
1097 chip->of_node = pctrl->dev->of_node;
1098 if (msm_gpio_needs_valid_mask(pctrl))
1099 chip->init_valid_mask = msm_gpio_init_valid_mask;
1100
1101 pctrl->irq_chip.name = "msmgpio";
1102 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1103 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1104 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1105 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1106 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1107 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1108 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1109 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1110 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1111
1112 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1113 if (np) {
1114 chip->irq.parent_domain = irq_find_matching_host(np,
1115 DOMAIN_BUS_WAKEUP);
1116 of_node_put(np);
1117 if (!chip->irq.parent_domain)
1118 return -EPROBE_DEFER;
1119 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1120 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1121
1122
1123
1124
1125 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1126 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1127 gpio = pctrl->soc->wakeirq_map[i].gpio;
1128 set_bit(gpio, pctrl->skip_wake_irqs);
1129 }
1130 }
1131
1132 girq = &chip->irq;
1133 girq->chip = &pctrl->irq_chip;
1134 girq->parent_handler = msm_gpio_irq_handler;
1135 girq->fwnode = pctrl->dev->fwnode;
1136 girq->num_parents = 1;
1137 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1138 GFP_KERNEL);
1139 if (!girq->parents)
1140 return -ENOMEM;
1141 girq->default_type = IRQ_TYPE_NONE;
1142 girq->handler = handle_bad_irq;
1143 girq->parents[0] = pctrl->irq;
1144
1145 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1146 if (ret) {
1147 dev_err(pctrl->dev, "Failed register gpiochip\n");
1148 return ret;
1149 }
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1162 ret = gpiochip_add_pin_range(&pctrl->chip,
1163 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1164 if (ret) {
1165 dev_err(pctrl->dev, "Failed to add pin range\n");
1166 gpiochip_remove(&pctrl->chip);
1167 return ret;
1168 }
1169 }
1170
1171 return 0;
1172}
1173
1174static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1175 void *data)
1176{
1177 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1178
1179 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1180 mdelay(1000);
1181 return NOTIFY_DONE;
1182}
1183
1184static struct msm_pinctrl *poweroff_pctrl;
1185
1186static void msm_ps_hold_poweroff(void)
1187{
1188 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1189}
1190
1191static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1192{
1193 int i;
1194 const struct msm_function *func = pctrl->soc->functions;
1195
1196 for (i = 0; i < pctrl->soc->nfunctions; i++)
1197 if (!strcmp(func[i].name, "ps_hold")) {
1198 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1199 pctrl->restart_nb.priority = 128;
1200 if (register_restart_handler(&pctrl->restart_nb))
1201 dev_err(pctrl->dev,
1202 "failed to setup restart handler.\n");
1203 poweroff_pctrl = pctrl;
1204 pm_power_off = msm_ps_hold_poweroff;
1205 break;
1206 }
1207}
1208
1209static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1210{
1211 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1212
1213 return pinctrl_force_sleep(pctrl->pctrl);
1214}
1215
1216static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1217{
1218 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1219
1220 return pinctrl_force_default(pctrl->pctrl);
1221}
1222
1223SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1224 msm_pinctrl_resume);
1225
1226EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1227
1228int msm_pinctrl_probe(struct platform_device *pdev,
1229 const struct msm_pinctrl_soc_data *soc_data)
1230{
1231 struct msm_pinctrl *pctrl;
1232 struct resource *res;
1233 int ret;
1234 int i;
1235
1236 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1237 if (!pctrl)
1238 return -ENOMEM;
1239
1240 pctrl->dev = &pdev->dev;
1241 pctrl->soc = soc_data;
1242 pctrl->chip = msm_gpio_template;
1243
1244 raw_spin_lock_init(&pctrl->lock);
1245
1246 if (soc_data->tiles) {
1247 for (i = 0; i < soc_data->ntiles; i++) {
1248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1249 soc_data->tiles[i]);
1250 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1251 if (IS_ERR(pctrl->regs[i]))
1252 return PTR_ERR(pctrl->regs[i]);
1253 }
1254 } else {
1255 pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
1256 if (IS_ERR(pctrl->regs[0]))
1257 return PTR_ERR(pctrl->regs[0]);
1258 }
1259
1260 msm_pinctrl_setup_pm_reset(pctrl);
1261
1262 pctrl->irq = platform_get_irq(pdev, 0);
1263 if (pctrl->irq < 0)
1264 return pctrl->irq;
1265
1266 pctrl->desc.owner = THIS_MODULE;
1267 pctrl->desc.pctlops = &msm_pinctrl_ops;
1268 pctrl->desc.pmxops = &msm_pinmux_ops;
1269 pctrl->desc.confops = &msm_pinconf_ops;
1270 pctrl->desc.name = dev_name(&pdev->dev);
1271 pctrl->desc.pins = pctrl->soc->pins;
1272 pctrl->desc.npins = pctrl->soc->npins;
1273
1274 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1275 if (IS_ERR(pctrl->pctrl)) {
1276 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1277 return PTR_ERR(pctrl->pctrl);
1278 }
1279
1280 ret = msm_gpio_init(pctrl);
1281 if (ret)
1282 return ret;
1283
1284 platform_set_drvdata(pdev, pctrl);
1285
1286 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1287
1288 return 0;
1289}
1290EXPORT_SYMBOL(msm_pinctrl_probe);
1291
1292int msm_pinctrl_remove(struct platform_device *pdev)
1293{
1294 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1295
1296 gpiochip_remove(&pctrl->chip);
1297
1298 unregister_restart_handler(&pctrl->restart_nb);
1299
1300 return 0;
1301}
1302EXPORT_SYMBOL(msm_pinctrl_remove);
1303
1304