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12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25
26#define XHCI_SBRN_OFFSET (0x60)
27
28
29#define MAX_HC_SLOTS 256
30
31#define MAX_HC_PORTS 127
32
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49
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2;
59
60};
61
62
63
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68
69
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77
78
79
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83
84
85
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88
89
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94
95
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99
100
101
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103
104#define HCC_PPC(p) ((p) & (1 << 3))
105
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109
110#define HCC_LTC(p) ((p) & (1 << 6))
111
112#define HCC_NSS(p) ((p) & (1 << 7))
113
114#define HCC_SPC(p) ((p) & (1 << 9))
115
116#define HCC_CFC(p) ((p) & (1 << 11))
117
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124
125#define DBOFF_MASK (~0x3)
126
127
128#define RTSOFF_MASK (~0x1f)
129
130
131
132#define HCC2_U3C(p) ((p) & (1 << 0))
133
134#define HCC2_CMC(p) ((p) & (1 << 1))
135
136#define HCC2_FSC(p) ((p) & (1 << 2))
137
138#define HCC2_CTC(p) ((p) & (1 << 3))
139
140#define HCC2_LEC(p) ((p) & (1 << 4))
141
142#define HCC2_CIC(p) ((p) & (1 << 5))
143
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
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176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188
189 __le32 reserved4[241];
190
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199
200
201#define CMD_RUN XHCI_CMD_RUN
202
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204
205
206#define CMD_RESET (1 << 1)
207
208#define CMD_EIE XHCI_CMD_EIE
209
210#define CMD_HSEIE XHCI_CMD_HSEIE
211
212
213#define CMD_LRESET (1 << 7)
214
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217
218#define CMD_EWE XHCI_CMD_EWE
219
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222
223
224#define CMD_PM_INDEX (1 << 11)
225
226#define CMD_ETE (1 << 14)
227
228
229
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233
234
235#define STS_HALT XHCI_STS_HALT
236
237#define STS_FATAL (1 << 2)
238
239#define STS_EINT (1 << 3)
240
241#define STS_PORT (1 << 4)
242
243
244#define STS_SAVE (1 << 8)
245
246#define STS_RESTORE (1 << 9)
247
248#define STS_SRE (1 << 10)
249
250#define STS_CNR XHCI_STS_CNR
251
252#define STS_HCE (1 << 12)
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259
260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
262
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264
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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269
270#define CMD_RING_PAUSE (1 << 1)
271
272#define CMD_RING_ABORT (1 << 2)
273
274#define CMD_RING_RUNNING (1 << 3)
275
276
277#define CMD_RING_RSVD_BITS (0x3f)
278
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280
281#define MAX_DEVS(p) ((p) & 0xff)
282
283#define CONFIG_U3E (1 << 8)
284
285#define CONFIG_CIE (1 << 9)
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289
290#define PORT_CONNECT (1 << 0)
291
292#define PORT_PE (1 << 1)
293
294
295#define PORT_OC (1 << 3)
296
297#define PORT_RESET (1 << 4)
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301
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317
318#define PORT_POWER (1 << 9)
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327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353
354#define PORT_LINK_STROBE (1 << 16)
355
356#define PORT_CSC (1 << 17)
357
358#define PORT_PEC (1 << 18)
359
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363
364#define PORT_WRC (1 << 19)
365
366#define PORT_OCC (1 << 20)
367
368#define PORT_RC (1 << 21)
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382#define PORT_PLC (1 << 22)
383
384#define PORT_CEC (1 << 23)
385#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
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393#define PORT_CAS (1 << 24)
394
395#define PORT_WKCONN_E (1 << 25)
396
397#define PORT_WKDISC_E (1 << 26)
398
399#define PORT_WKOC_E (1 << 27)
400
401
402#define PORT_DEV_REMOVE (1 << 30)
403
404#define PORT_WR (1 << 31)
405
406
407#define DUPLICATE_ENTRY ((u8)(-1))
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412
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418
419
420
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429#define PORT_TEST_MODE_SHIFT 28
430
431
432#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
434
435
436#define PORT_HIRDM(p)((p) & 3)
437#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438#define PORT_BESLD(p)(((p) & 0xf) << 10)
439
440
441#define XHCI_L1_TIMEOUT 512
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452
453#define XHCI_DEFAULT_BESL 4
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461#define XHCI_PORT_POLLING_LFPS_TIME 36
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480struct xhci_intr_reg {
481 __le32 irq_pending;
482 __le32 irq_control;
483 __le32 erst_size;
484 __le32 rsvd;
485 __le64 erst_base;
486 __le64 erst_dequeue;
487};
488
489
490#define ER_IRQ_PENDING(p) ((p) & 0x1)
491
492
493#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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501
502#define ER_IRQ_INTERVAL_MASK (0xffff)
503
504#define ER_IRQ_COUNTER_MASK (0xffff << 16)
505
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508#define ERST_SIZE_MASK (0xffff << 16)
509
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514#define ERST_DESI_MASK (0x7)
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518#define ERST_EHB (1 << 3)
519#define ERST_PTR_MASK (0xf)
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530struct xhci_run_regs {
531 __le32 microframe_index;
532 __le32 rsvd[7];
533 struct xhci_intr_reg ir_set[128];
534};
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545struct xhci_doorbell_array {
546 __le32 doorbell[256];
547};
548
549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550#define DB_VALUE_HOST 0x00000000
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560struct xhci_protocol_caps {
561 u32 revision;
562 u32 name_string;
563 u32 port_info;
564};
565
566#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
571
572#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
578
579#define PLT_MASK (0x03 << 6)
580#define PLT_SYM (0x00 << 6)
581#define PLT_ASYM_RX (0x02 << 6)
582#define PLT_ASYM_TX (0x03 << 6)
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594struct xhci_container_ctx {
595 unsigned type;
596#define XHCI_CTX_TYPE_DEVICE 0x1
597#define XHCI_CTX_TYPE_INPUT 0x2
598
599 int size;
600
601 u8 *bytes;
602 dma_addr_t dma;
603};
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616struct xhci_slot_ctx {
617 __le32 dev_info;
618 __le32 dev_info2;
619 __le32 tt_info;
620 __le32 dev_state;
621
622 __le32 reserved[4];
623};
624
625
626
627#define ROUTE_STRING_MASK (0xfffff)
628
629#define DEV_SPEED (0xf << 20)
630#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631
632
633#define DEV_MTT (0x1 << 25)
634
635#define DEV_HUB (0x1 << 26)
636
637#define LAST_CTX_MASK (0x1f << 27)
638#define LAST_CTX(p) ((p) << 27)
639#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640#define SLOT_FLAG (1 << 0)
641#define EP0_FLAG (1 << 1)
642
643
644
645#define MAX_EXIT (0xffff)
646
647#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649
650#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
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657
658
659#define TT_SLOT (0xff)
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664#define TT_PORT (0xff << 8)
665#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
667
668
669
670#define DEV_ADDR_MASK (0xff)
671
672
673#define SLOT_STATE (0x1f << 27)
674#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
675
676#define SLOT_STATE_DISABLED 0
677#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678#define SLOT_STATE_DEFAULT 1
679#define SLOT_STATE_ADDRESSED 2
680#define SLOT_STATE_CONFIGURED 3
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700struct xhci_ep_ctx {
701 __le32 ep_info;
702 __le32 ep_info2;
703 __le64 deq;
704 __le32 tx_info;
705
706 __le32 reserved[3];
707};
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718
719#define EP_STATE_MASK (0xf)
720#define EP_STATE_DISABLED 0
721#define EP_STATE_RUNNING 1
722#define EP_STATE_HALTED 2
723#define EP_STATE_STOPPED 3
724#define EP_STATE_ERROR 4
725#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
726
727
728#define EP_MULT(p) (((p) & 0x3) << 8)
729#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730
731
732
733#define EP_INTERVAL(p) (((p) & 0xff) << 16)
734#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736#define EP_MAXPSTREAMS_MASK (0x1f << 10)
737#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739
740#define EP_HAS_LSA (1 << 15)
741
742#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
743
744
745
746
747
748
749#define FORCE_EVENT (0x1)
750#define ERROR_COUNT(p) (((p) & 0x3) << 1)
751#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752#define EP_TYPE(p) ((p) << 3)
753#define ISOC_OUT_EP 1
754#define BULK_OUT_EP 2
755#define INT_OUT_EP 3
756#define CTRL_EP 4
757#define ISOC_IN_EP 5
758#define BULK_IN_EP 6
759#define INT_IN_EP 7
760
761
762#define MAX_BURST(p) (((p)&0xff) << 8)
763#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764#define MAX_PACKET(p) (((p)&0xffff) << 16)
765#define MAX_PACKET_MASK (0xffff << 16)
766#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
767
768
769#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
773
774
775#define EP_CTX_CYCLE_MASK (1 << 0)
776#define SCTX_DEQ_MASK (~0xfL)
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785
786struct xhci_input_control_ctx {
787 __le32 drop_flags;
788 __le32 add_flags;
789 __le32 rsvd2[6];
790};
791
792#define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794#define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
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799
800
801struct xhci_command {
802
803 struct xhci_container_ctx *in_ctx;
804 u32 status;
805 int slot_id;
806
807
808
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
812};
813
814
815#define DROP_EP(x) (0x1 << x)
816
817#define ADD_EP(x) (0x1 << x)
818
819struct xhci_stream_ctx {
820
821 __le64 stream_ring;
822
823 __le32 reserved[2];
824};
825
826
827#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828
829#define SCT_SEC_TR 0
830
831#define SCT_PRI_TR 1
832
833#define SCT_SSA_8 2
834#define SCT_SSA_16 3
835#define SCT_SSA_32 4
836#define SCT_SSA_64 5
837#define SCT_SSA_128 6
838#define SCT_SSA_256 7
839
840
841struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843
844 unsigned int num_streams;
845
846
847
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
854};
855
856#define SMALL_STREAM_ARRAY_SIZE 256
857#define MEDIUM_STREAM_ARRAY_SIZE 1024
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864
865struct xhci_bw_info {
866
867 unsigned int ep_interval;
868
869 unsigned int mult;
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
873 unsigned int type;
874};
875
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879
880
881#define FS_BLOCK 1
882#define HS_BLOCK 4
883#define SS_BLOCK 16
884#define DMI_BLOCK 32
885
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890
891#define DMI_OVERHEAD 8
892#define DMI_OVERHEAD_BURST 4
893#define SS_OVERHEAD 8
894#define SS_OVERHEAD_BURST 32
895#define HS_OVERHEAD 26
896#define FS_OVERHEAD 20
897#define LS_OVERHEAD 128
898
899
900
901
902
903#define TT_HS_OVERHEAD (31 + 94)
904#define TT_DMI_OVERHEAD (25 + 12)
905
906
907#define FS_BW_LIMIT 1285
908#define TT_BW_LIMIT 1320
909#define HS_BW_LIMIT 1607
910#define SS_BW_LIMIT_IN 3906
911#define DMI_BW_LIMIT_IN 3906
912#define SS_BW_LIMIT_OUT 3906
913#define DMI_BW_LIMIT_OUT 3906
914
915
916#define FS_BW_RESERVED 10
917#define HS_BW_RESERVED 20
918#define SS_BW_RESERVED 10
919
920struct xhci_virt_ep {
921 struct xhci_ring *ring;
922
923 struct xhci_stream_info *stream_info;
924
925
926
927 struct xhci_ring *new_ring;
928 unsigned int ep_state;
929#define SET_DEQ_PENDING (1 << 0)
930#define EP_HALTED (1 << 1)
931#define EP_STOP_CMD_PENDING (1 << 2)
932
933#define EP_GETTING_STREAMS (1 << 3)
934#define EP_HAS_STREAMS (1 << 4)
935
936#define EP_GETTING_NO_STREAMS (1 << 5)
937#define EP_HARD_CLEAR_TOGGLE (1 << 6)
938#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
939
940#define EP_CLEARING_TT (1 << 8)
941
942 struct list_head cancelled_td_list;
943
944 struct timer_list stop_cmd_timer;
945 struct xhci_hcd *xhci;
946
947
948
949
950 struct xhci_segment *queued_deq_seg;
951 union xhci_trb *queued_deq_ptr;
952
953
954
955
956
957
958
959 bool skip;
960
961 struct xhci_bw_info bw_info;
962 struct list_head bw_endpoint_list;
963
964 int next_frame_id;
965
966 bool use_extended_tbc;
967};
968
969enum xhci_overhead_type {
970 LS_OVERHEAD_TYPE = 0,
971 FS_OVERHEAD_TYPE,
972 HS_OVERHEAD_TYPE,
973};
974
975struct xhci_interval_bw {
976 unsigned int num_packets;
977
978
979
980 struct list_head endpoints;
981
982 unsigned int overhead[3];
983};
984
985#define XHCI_MAX_INTERVAL 16
986
987struct xhci_interval_bw_table {
988 unsigned int interval0_esit_payload;
989 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
990
991 unsigned int bw_used;
992 unsigned int ss_bw_in;
993 unsigned int ss_bw_out;
994};
995
996
997struct xhci_virt_device {
998 struct usb_device *udev;
999
1000
1001
1002
1003
1004
1005
1006
1007 struct xhci_container_ctx *out_ctx;
1008
1009 struct xhci_container_ctx *in_ctx;
1010 struct xhci_virt_ep eps[31];
1011 u8 fake_port;
1012 u8 real_port;
1013 struct xhci_interval_bw_table *bw_table;
1014 struct xhci_tt_bw_info *tt_info;
1015
1016
1017
1018
1019
1020
1021 unsigned long flags;
1022#define VDEV_PORT_ERROR BIT(0)
1023
1024
1025 u16 current_mel;
1026
1027 void *debugfs_private;
1028};
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038struct xhci_root_port_bw_info {
1039 struct list_head tts;
1040 unsigned int num_active_tts;
1041 struct xhci_interval_bw_table bw_table;
1042};
1043
1044struct xhci_tt_bw_info {
1045 struct list_head tt_list;
1046 int slot_id;
1047 int ttport;
1048 struct xhci_interval_bw_table bw_table;
1049 int active_eps;
1050};
1051
1052
1053
1054
1055
1056
1057struct xhci_device_context_array {
1058
1059 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1060
1061 dma_addr_t dma;
1062};
1063
1064
1065
1066
1067
1068
1069
1070struct xhci_transfer_event {
1071
1072 __le64 buffer;
1073 __le32 transfer_len;
1074
1075 __le32 flags;
1076};
1077
1078
1079
1080#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1081
1082
1083#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1084
1085
1086#define COMP_CODE_MASK (0xff << 24)
1087#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1088#define COMP_INVALID 0
1089#define COMP_SUCCESS 1
1090#define COMP_DATA_BUFFER_ERROR 2
1091#define COMP_BABBLE_DETECTED_ERROR 3
1092#define COMP_USB_TRANSACTION_ERROR 4
1093#define COMP_TRB_ERROR 5
1094#define COMP_STALL_ERROR 6
1095#define COMP_RESOURCE_ERROR 7
1096#define COMP_BANDWIDTH_ERROR 8
1097#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1098#define COMP_INVALID_STREAM_TYPE_ERROR 10
1099#define COMP_SLOT_NOT_ENABLED_ERROR 11
1100#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1101#define COMP_SHORT_PACKET 13
1102#define COMP_RING_UNDERRUN 14
1103#define COMP_RING_OVERRUN 15
1104#define COMP_VF_EVENT_RING_FULL_ERROR 16
1105#define COMP_PARAMETER_ERROR 17
1106#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1107#define COMP_CONTEXT_STATE_ERROR 19
1108#define COMP_NO_PING_RESPONSE_ERROR 20
1109#define COMP_EVENT_RING_FULL_ERROR 21
1110#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1111#define COMP_MISSED_SERVICE_ERROR 23
1112#define COMP_COMMAND_RING_STOPPED 24
1113#define COMP_COMMAND_ABORTED 25
1114#define COMP_STOPPED 26
1115#define COMP_STOPPED_LENGTH_INVALID 27
1116#define COMP_STOPPED_SHORT_PACKET 28
1117#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1118#define COMP_ISOCH_BUFFER_OVERRUN 31
1119#define COMP_EVENT_LOST_ERROR 32
1120#define COMP_UNDEFINED_ERROR 33
1121#define COMP_INVALID_STREAM_ID_ERROR 34
1122#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1123#define COMP_SPLIT_TRANSACTION_ERROR 36
1124
1125static inline const char *xhci_trb_comp_code_string(u8 status)
1126{
1127 switch (status) {
1128 case COMP_INVALID:
1129 return "Invalid";
1130 case COMP_SUCCESS:
1131 return "Success";
1132 case COMP_DATA_BUFFER_ERROR:
1133 return "Data Buffer Error";
1134 case COMP_BABBLE_DETECTED_ERROR:
1135 return "Babble Detected";
1136 case COMP_USB_TRANSACTION_ERROR:
1137 return "USB Transaction Error";
1138 case COMP_TRB_ERROR:
1139 return "TRB Error";
1140 case COMP_STALL_ERROR:
1141 return "Stall Error";
1142 case COMP_RESOURCE_ERROR:
1143 return "Resource Error";
1144 case COMP_BANDWIDTH_ERROR:
1145 return "Bandwidth Error";
1146 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1147 return "No Slots Available Error";
1148 case COMP_INVALID_STREAM_TYPE_ERROR:
1149 return "Invalid Stream Type Error";
1150 case COMP_SLOT_NOT_ENABLED_ERROR:
1151 return "Slot Not Enabled Error";
1152 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1153 return "Endpoint Not Enabled Error";
1154 case COMP_SHORT_PACKET:
1155 return "Short Packet";
1156 case COMP_RING_UNDERRUN:
1157 return "Ring Underrun";
1158 case COMP_RING_OVERRUN:
1159 return "Ring Overrun";
1160 case COMP_VF_EVENT_RING_FULL_ERROR:
1161 return "VF Event Ring Full Error";
1162 case COMP_PARAMETER_ERROR:
1163 return "Parameter Error";
1164 case COMP_BANDWIDTH_OVERRUN_ERROR:
1165 return "Bandwidth Overrun Error";
1166 case COMP_CONTEXT_STATE_ERROR:
1167 return "Context State Error";
1168 case COMP_NO_PING_RESPONSE_ERROR:
1169 return "No Ping Response Error";
1170 case COMP_EVENT_RING_FULL_ERROR:
1171 return "Event Ring Full Error";
1172 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1173 return "Incompatible Device Error";
1174 case COMP_MISSED_SERVICE_ERROR:
1175 return "Missed Service Error";
1176 case COMP_COMMAND_RING_STOPPED:
1177 return "Command Ring Stopped";
1178 case COMP_COMMAND_ABORTED:
1179 return "Command Aborted";
1180 case COMP_STOPPED:
1181 return "Stopped";
1182 case COMP_STOPPED_LENGTH_INVALID:
1183 return "Stopped - Length Invalid";
1184 case COMP_STOPPED_SHORT_PACKET:
1185 return "Stopped - Short Packet";
1186 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1187 return "Max Exit Latency Too Large Error";
1188 case COMP_ISOCH_BUFFER_OVERRUN:
1189 return "Isoch Buffer Overrun";
1190 case COMP_EVENT_LOST_ERROR:
1191 return "Event Lost Error";
1192 case COMP_UNDEFINED_ERROR:
1193 return "Undefined Error";
1194 case COMP_INVALID_STREAM_ID_ERROR:
1195 return "Invalid Stream ID Error";
1196 case COMP_SECONDARY_BANDWIDTH_ERROR:
1197 return "Secondary Bandwidth Error";
1198 case COMP_SPLIT_TRANSACTION_ERROR:
1199 return "Split Transaction Error";
1200 default:
1201 return "Unknown!!";
1202 }
1203}
1204
1205struct xhci_link_trb {
1206
1207 __le64 segment_ptr;
1208 __le32 intr_target;
1209 __le32 control;
1210};
1211
1212
1213#define LINK_TOGGLE (0x1<<1)
1214
1215
1216struct xhci_event_cmd {
1217
1218 __le64 cmd_trb;
1219 __le32 status;
1220 __le32 flags;
1221};
1222
1223
1224
1225
1226#define TRB_BSR (1<<9)
1227
1228
1229#define TRB_DC (1<<9)
1230
1231
1232#define TRB_TSP (1<<9)
1233
1234enum xhci_ep_reset_type {
1235 EP_HARD_RESET,
1236 EP_SOFT_RESET,
1237};
1238
1239
1240#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1241#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1242
1243
1244#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1245
1246
1247#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1248
1249
1250#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1251#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1252
1253enum xhci_setup_dev {
1254 SETUP_CONTEXT_ONLY,
1255 SETUP_CONTEXT_ADDRESS,
1256};
1257
1258
1259
1260#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1261#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1262
1263
1264#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1265#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1266
1267#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1268#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1269#define LAST_EP_INDEX 30
1270
1271
1272#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1273#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1274#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1275
1276
1277#define TRB_TC (1<<1)
1278
1279
1280
1281#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1282
1283#define EVENT_DATA (1 << 2)
1284
1285
1286
1287#define TRB_LEN(p) ((p) & 0x1ffff)
1288
1289#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1290#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1291
1292#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1293
1294#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1295#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1296
1297#define TRB_TBC(p) (((p) & 0x3) << 7)
1298#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1299
1300
1301#define TRB_CYCLE (1<<0)
1302
1303
1304
1305
1306#define TRB_ENT (1<<1)
1307
1308#define TRB_ISP (1<<2)
1309
1310#define TRB_NO_SNOOP (1<<3)
1311
1312#define TRB_CHAIN (1<<4)
1313
1314#define TRB_IOC (1<<5)
1315
1316#define TRB_IDT (1<<6)
1317
1318#define TRB_IDT_MAX_SIZE 8
1319
1320
1321#define TRB_BEI (1<<9)
1322
1323
1324#define TRB_DIR_IN (1<<16)
1325#define TRB_TX_TYPE(p) ((p) << 16)
1326#define TRB_DATA_OUT 2
1327#define TRB_DATA_IN 3
1328
1329
1330#define TRB_SIA (1<<31)
1331#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1332
1333struct xhci_generic_trb {
1334 __le32 field[4];
1335};
1336
1337union xhci_trb {
1338 struct xhci_link_trb link;
1339 struct xhci_transfer_event trans_event;
1340 struct xhci_event_cmd event_cmd;
1341 struct xhci_generic_trb generic;
1342};
1343
1344
1345#define TRB_TYPE_BITMASK (0xfc00)
1346#define TRB_TYPE(p) ((p) << 10)
1347#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1348
1349
1350#define TRB_NORMAL 1
1351
1352#define TRB_SETUP 2
1353
1354#define TRB_DATA 3
1355
1356#define TRB_STATUS 4
1357
1358#define TRB_ISOC 5
1359
1360#define TRB_LINK 6
1361#define TRB_EVENT_DATA 7
1362
1363#define TRB_TR_NOOP 8
1364
1365
1366#define TRB_ENABLE_SLOT 9
1367
1368#define TRB_DISABLE_SLOT 10
1369
1370#define TRB_ADDR_DEV 11
1371
1372#define TRB_CONFIG_EP 12
1373
1374#define TRB_EVAL_CONTEXT 13
1375
1376#define TRB_RESET_EP 14
1377
1378#define TRB_STOP_RING 15
1379
1380#define TRB_SET_DEQ 16
1381
1382#define TRB_RESET_DEV 17
1383
1384#define TRB_FORCE_EVENT 18
1385
1386#define TRB_NEG_BANDWIDTH 19
1387
1388#define TRB_SET_LT 20
1389
1390#define TRB_GET_BW 21
1391
1392#define TRB_FORCE_HEADER 22
1393
1394#define TRB_CMD_NOOP 23
1395
1396
1397
1398#define TRB_TRANSFER 32
1399
1400#define TRB_COMPLETION 33
1401
1402#define TRB_PORT_STATUS 34
1403
1404#define TRB_BANDWIDTH_EVENT 35
1405
1406#define TRB_DOORBELL 36
1407
1408#define TRB_HC_EVENT 37
1409
1410#define TRB_DEV_NOTE 38
1411
1412#define TRB_MFINDEX_WRAP 39
1413
1414
1415
1416#define TRB_NEC_CMD_COMP 48
1417
1418#define TRB_NEC_GET_FW 49
1419
1420static inline const char *xhci_trb_type_string(u8 type)
1421{
1422 switch (type) {
1423 case TRB_NORMAL:
1424 return "Normal";
1425 case TRB_SETUP:
1426 return "Setup Stage";
1427 case TRB_DATA:
1428 return "Data Stage";
1429 case TRB_STATUS:
1430 return "Status Stage";
1431 case TRB_ISOC:
1432 return "Isoch";
1433 case TRB_LINK:
1434 return "Link";
1435 case TRB_EVENT_DATA:
1436 return "Event Data";
1437 case TRB_TR_NOOP:
1438 return "No-Op";
1439 case TRB_ENABLE_SLOT:
1440 return "Enable Slot Command";
1441 case TRB_DISABLE_SLOT:
1442 return "Disable Slot Command";
1443 case TRB_ADDR_DEV:
1444 return "Address Device Command";
1445 case TRB_CONFIG_EP:
1446 return "Configure Endpoint Command";
1447 case TRB_EVAL_CONTEXT:
1448 return "Evaluate Context Command";
1449 case TRB_RESET_EP:
1450 return "Reset Endpoint Command";
1451 case TRB_STOP_RING:
1452 return "Stop Ring Command";
1453 case TRB_SET_DEQ:
1454 return "Set TR Dequeue Pointer Command";
1455 case TRB_RESET_DEV:
1456 return "Reset Device Command";
1457 case TRB_FORCE_EVENT:
1458 return "Force Event Command";
1459 case TRB_NEG_BANDWIDTH:
1460 return "Negotiate Bandwidth Command";
1461 case TRB_SET_LT:
1462 return "Set Latency Tolerance Value Command";
1463 case TRB_GET_BW:
1464 return "Get Port Bandwidth Command";
1465 case TRB_FORCE_HEADER:
1466 return "Force Header Command";
1467 case TRB_CMD_NOOP:
1468 return "No-Op Command";
1469 case TRB_TRANSFER:
1470 return "Transfer Event";
1471 case TRB_COMPLETION:
1472 return "Command Completion Event";
1473 case TRB_PORT_STATUS:
1474 return "Port Status Change Event";
1475 case TRB_BANDWIDTH_EVENT:
1476 return "Bandwidth Request Event";
1477 case TRB_DOORBELL:
1478 return "Doorbell Event";
1479 case TRB_HC_EVENT:
1480 return "Host Controller Event";
1481 case TRB_DEV_NOTE:
1482 return "Device Notification Event";
1483 case TRB_MFINDEX_WRAP:
1484 return "MFINDEX Wrap Event";
1485 case TRB_NEC_CMD_COMP:
1486 return "NEC Command Completion Event";
1487 case TRB_NEC_GET_FW:
1488 return "NET Get Firmware Revision Command";
1489 default:
1490 return "UNKNOWN";
1491 }
1492}
1493
1494#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1495
1496#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1497 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1498#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1499 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1500
1501#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1502#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1503
1504
1505
1506
1507
1508
1509#define TRBS_PER_SEGMENT 256
1510
1511#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1512#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1513#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1514
1515#define TRB_MAX_BUFF_SHIFT 16
1516#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1517
1518#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1519 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1520#define MAX_SOFT_RETRY 3
1521
1522struct xhci_segment {
1523 union xhci_trb *trbs;
1524
1525 struct xhci_segment *next;
1526 dma_addr_t dma;
1527
1528 dma_addr_t bounce_dma;
1529 void *bounce_buf;
1530 unsigned int bounce_offs;
1531 unsigned int bounce_len;
1532};
1533
1534struct xhci_td {
1535 struct list_head td_list;
1536 struct list_head cancelled_td_list;
1537 struct urb *urb;
1538 struct xhci_segment *start_seg;
1539 union xhci_trb *first_trb;
1540 union xhci_trb *last_trb;
1541 struct xhci_segment *bounce_seg;
1542
1543 bool urb_length_set;
1544};
1545
1546
1547#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1548
1549
1550struct xhci_cd {
1551 struct xhci_command *command;
1552 union xhci_trb *cmd_trb;
1553};
1554
1555struct xhci_dequeue_state {
1556 struct xhci_segment *new_deq_seg;
1557 union xhci_trb *new_deq_ptr;
1558 int new_cycle_state;
1559 unsigned int stream_id;
1560};
1561
1562enum xhci_ring_type {
1563 TYPE_CTRL = 0,
1564 TYPE_ISOC,
1565 TYPE_BULK,
1566 TYPE_INTR,
1567 TYPE_STREAM,
1568 TYPE_COMMAND,
1569 TYPE_EVENT,
1570};
1571
1572static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1573{
1574 switch (type) {
1575 case TYPE_CTRL:
1576 return "CTRL";
1577 case TYPE_ISOC:
1578 return "ISOC";
1579 case TYPE_BULK:
1580 return "BULK";
1581 case TYPE_INTR:
1582 return "INTR";
1583 case TYPE_STREAM:
1584 return "STREAM";
1585 case TYPE_COMMAND:
1586 return "CMD";
1587 case TYPE_EVENT:
1588 return "EVENT";
1589 }
1590
1591 return "UNKNOWN";
1592}
1593
1594struct xhci_ring {
1595 struct xhci_segment *first_seg;
1596 struct xhci_segment *last_seg;
1597 union xhci_trb *enqueue;
1598 struct xhci_segment *enq_seg;
1599 union xhci_trb *dequeue;
1600 struct xhci_segment *deq_seg;
1601 struct list_head td_list;
1602
1603
1604
1605
1606
1607 u32 cycle_state;
1608 unsigned int err_count;
1609 unsigned int stream_id;
1610 unsigned int num_segs;
1611 unsigned int num_trbs_free;
1612 unsigned int num_trbs_free_temp;
1613 unsigned int bounce_buf_len;
1614 enum xhci_ring_type type;
1615 bool last_td_was_short;
1616 struct radix_tree_root *trb_address_map;
1617};
1618
1619struct xhci_erst_entry {
1620
1621 __le64 seg_addr;
1622 __le32 seg_size;
1623
1624 __le32 rsvd;
1625};
1626
1627struct xhci_erst {
1628 struct xhci_erst_entry *entries;
1629 unsigned int num_entries;
1630
1631 dma_addr_t erst_dma_addr;
1632
1633 unsigned int erst_size;
1634};
1635
1636struct xhci_scratchpad {
1637 u64 *sp_array;
1638 dma_addr_t sp_dma;
1639 void **sp_buffers;
1640};
1641
1642struct urb_priv {
1643 int num_tds;
1644 int num_tds_done;
1645 struct xhci_td td[0];
1646};
1647
1648
1649
1650
1651
1652
1653#define ERST_NUM_SEGS 1
1654
1655#define ERST_SIZE 64
1656
1657#define ERST_ENTRIES 1
1658
1659#define POLL_TIMEOUT 60
1660
1661#define XHCI_STOP_EP_CMD_TIMEOUT 5
1662
1663
1664struct s3_save {
1665 u32 command;
1666 u32 dev_nt;
1667 u64 dcbaa_ptr;
1668 u32 config_reg;
1669 u32 irq_pending;
1670 u32 irq_control;
1671 u32 erst_size;
1672 u64 erst_base;
1673 u64 erst_dequeue;
1674};
1675
1676
1677struct dev_info {
1678 u32 dev_id;
1679 struct list_head list;
1680};
1681
1682struct xhci_bus_state {
1683 unsigned long bus_suspended;
1684 unsigned long next_statechange;
1685
1686
1687
1688 u32 port_c_suspend;
1689 u32 suspended_ports;
1690 u32 port_remote_wakeup;
1691 unsigned long resume_done[USB_MAXCHILDREN];
1692
1693 unsigned long resuming_ports;
1694
1695 unsigned long rexit_ports;
1696 struct completion rexit_done[USB_MAXCHILDREN];
1697};
1698
1699
1700
1701
1702
1703
1704#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1705struct xhci_port_cap {
1706 u32 *psi;
1707 u8 psi_count;
1708 u8 psi_uid_count;
1709 u8 maj_rev;
1710 u8 min_rev;
1711};
1712
1713struct xhci_port {
1714 __le32 __iomem *addr;
1715 int hw_portnum;
1716 int hcd_portnum;
1717 struct xhci_hub *rhub;
1718 struct xhci_port_cap *port_cap;
1719};
1720
1721struct xhci_hub {
1722 struct xhci_port **ports;
1723 unsigned int num_ports;
1724 struct usb_hcd *hcd;
1725
1726 struct xhci_bus_state bus_state;
1727
1728 u8 maj_rev;
1729 u8 min_rev;
1730};
1731
1732
1733struct xhci_hcd {
1734 struct usb_hcd *main_hcd;
1735 struct usb_hcd *shared_hcd;
1736
1737 struct xhci_cap_regs __iomem *cap_regs;
1738 struct xhci_op_regs __iomem *op_regs;
1739 struct xhci_run_regs __iomem *run_regs;
1740 struct xhci_doorbell_array __iomem *dba;
1741
1742 struct xhci_intr_reg __iomem *ir_set;
1743
1744
1745 __u32 hcs_params1;
1746 __u32 hcs_params2;
1747 __u32 hcs_params3;
1748 __u32 hcc_params;
1749 __u32 hcc_params2;
1750
1751 spinlock_t lock;
1752
1753
1754 u8 sbrn;
1755 u16 hci_version;
1756 u8 max_slots;
1757 u8 max_interrupters;
1758 u8 max_ports;
1759 u8 isoc_threshold;
1760
1761 u32 imod_interval;
1762 int event_ring_max;
1763
1764 int page_size;
1765
1766 int page_shift;
1767
1768 int msix_count;
1769
1770 struct clk *clk;
1771 struct clk *reg_clk;
1772
1773 struct xhci_device_context_array *dcbaa;
1774 struct xhci_ring *cmd_ring;
1775 unsigned int cmd_ring_state;
1776#define CMD_RING_STATE_RUNNING (1 << 0)
1777#define CMD_RING_STATE_ABORTED (1 << 1)
1778#define CMD_RING_STATE_STOPPED (1 << 2)
1779 struct list_head cmd_list;
1780 unsigned int cmd_ring_reserved_trbs;
1781 struct delayed_work cmd_timer;
1782 struct completion cmd_ring_stop_completion;
1783 struct xhci_command *current_cmd;
1784 struct xhci_ring *event_ring;
1785 struct xhci_erst erst;
1786
1787 struct xhci_scratchpad *scratchpad;
1788
1789 struct list_head lpm_failed_devs;
1790
1791
1792
1793 struct mutex mutex;
1794
1795 struct xhci_command *lpm_command;
1796
1797 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1798
1799 struct xhci_root_port_bw_info *rh_bw;
1800
1801
1802 struct dma_pool *device_pool;
1803 struct dma_pool *segment_pool;
1804 struct dma_pool *small_streams_pool;
1805 struct dma_pool *medium_streams_pool;
1806
1807
1808 unsigned int xhc_state;
1809
1810 u32 command;
1811 struct s3_save s3;
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824#define XHCI_STATE_DYING (1 << 0)
1825#define XHCI_STATE_HALTED (1 << 1)
1826#define XHCI_STATE_REMOVING (1 << 2)
1827 unsigned long long quirks;
1828#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1829#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1830#define XHCI_NEC_HOST BIT_ULL(2)
1831#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1832#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1843#define XHCI_BROKEN_MSI BIT_ULL(6)
1844#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1845#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1846#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1847#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1848#define XHCI_LPM_SUPPORT BIT_ULL(11)
1849#define XHCI_INTEL_HOST BIT_ULL(12)
1850#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1851#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1852#define XHCI_AVOID_BEI BIT_ULL(15)
1853#define XHCI_PLAT BIT_ULL(16)
1854#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1855#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1856
1857#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1858#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1859#define XHCI_MTK_HOST BIT_ULL(21)
1860#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1861#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1862#define XHCI_MISSING_CAS BIT_ULL(24)
1863
1864#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1865#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1866#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1867#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1868#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1869#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1870#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1871#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1872#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1873#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1874#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1875
1876 unsigned int num_active_eps;
1877 unsigned int limit_active_eps;
1878 struct xhci_port *hw_ports;
1879 struct xhci_hub usb2_rhub;
1880 struct xhci_hub usb3_rhub;
1881
1882 unsigned hw_lpm_support:1;
1883
1884 unsigned broken_suspend:1;
1885
1886 u32 *ext_caps;
1887 unsigned int num_ext_caps;
1888
1889 struct xhci_port_cap *port_caps;
1890 unsigned int num_port_caps;
1891
1892 struct timer_list comp_mode_recovery_timer;
1893 u32 port_status_u0;
1894 u16 test_mode;
1895
1896#define COMP_MODE_RCVRY_MSECS 2000
1897
1898 struct dentry *debugfs_root;
1899 struct dentry *debugfs_slots;
1900 struct list_head regset_list;
1901
1902 void *dbc;
1903
1904 unsigned long priv[0] __aligned(sizeof(s64));
1905};
1906
1907
1908struct xhci_driver_overrides {
1909 size_t extra_priv_size;
1910 int (*reset)(struct usb_hcd *hcd);
1911 int (*start)(struct usb_hcd *hcd);
1912};
1913
1914#define XHCI_CFC_DELAY 10
1915
1916
1917static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1918{
1919 struct usb_hcd *primary_hcd;
1920
1921 if (usb_hcd_is_primary_hcd(hcd))
1922 primary_hcd = hcd;
1923 else
1924 primary_hcd = hcd->primary_hcd;
1925
1926 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1927}
1928
1929static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1930{
1931 return xhci->main_hcd;
1932}
1933
1934#define xhci_dbg(xhci, fmt, args...) \
1935 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1936#define xhci_err(xhci, fmt, args...) \
1937 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1938#define xhci_warn(xhci, fmt, args...) \
1939 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1940#define xhci_warn_ratelimited(xhci, fmt, args...) \
1941 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1942#define xhci_info(xhci, fmt, args...) \
1943 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1955 __le64 __iomem *regs)
1956{
1957 return lo_hi_readq(regs);
1958}
1959static inline void xhci_write_64(struct xhci_hcd *xhci,
1960 const u64 val, __le64 __iomem *regs)
1961{
1962 lo_hi_writeq(val, regs);
1963}
1964
1965static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1966{
1967 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1968}
1969
1970
1971char *xhci_get_slot_state(struct xhci_hcd *xhci,
1972 struct xhci_container_ctx *ctx);
1973void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1974 const char *fmt, ...);
1975
1976
1977void xhci_mem_cleanup(struct xhci_hcd *xhci);
1978int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1979void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1980int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1981int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1982void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1983 struct usb_device *udev);
1984unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1985unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1986unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1987void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1988void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1989 struct xhci_virt_device *virt_dev,
1990 int old_active_eps);
1991void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1992void xhci_update_bw_info(struct xhci_hcd *xhci,
1993 struct xhci_container_ctx *in_ctx,
1994 struct xhci_input_control_ctx *ctrl_ctx,
1995 struct xhci_virt_device *virt_dev);
1996void xhci_endpoint_copy(struct xhci_hcd *xhci,
1997 struct xhci_container_ctx *in_ctx,
1998 struct xhci_container_ctx *out_ctx,
1999 unsigned int ep_index);
2000void xhci_slot_copy(struct xhci_hcd *xhci,
2001 struct xhci_container_ctx *in_ctx,
2002 struct xhci_container_ctx *out_ctx);
2003int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2004 struct usb_device *udev, struct usb_host_endpoint *ep,
2005 gfp_t mem_flags);
2006struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2007 unsigned int num_segs, unsigned int cycle_state,
2008 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2009void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2010int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2011 unsigned int num_trbs, gfp_t flags);
2012int xhci_alloc_erst(struct xhci_hcd *xhci,
2013 struct xhci_ring *evt_ring,
2014 struct xhci_erst *erst,
2015 gfp_t flags);
2016void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2017void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2018 struct xhci_virt_device *virt_dev,
2019 unsigned int ep_index);
2020struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2021 unsigned int num_stream_ctxs,
2022 unsigned int num_streams,
2023 unsigned int max_packet, gfp_t flags);
2024void xhci_free_stream_info(struct xhci_hcd *xhci,
2025 struct xhci_stream_info *stream_info);
2026void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2027 struct xhci_ep_ctx *ep_ctx,
2028 struct xhci_stream_info *stream_info);
2029void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2030 struct xhci_virt_ep *ep);
2031void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2032 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2033struct xhci_ring *xhci_dma_to_transfer_ring(
2034 struct xhci_virt_ep *ep,
2035 u64 address);
2036struct xhci_ring *xhci_stream_id_to_ring(
2037 struct xhci_virt_device *dev,
2038 unsigned int ep_index,
2039 unsigned int stream_id);
2040struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2041 bool allocate_completion, gfp_t mem_flags);
2042struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2043 bool allocate_completion, gfp_t mem_flags);
2044void xhci_urb_free_priv(struct urb_priv *urb_priv);
2045void xhci_free_command(struct xhci_hcd *xhci,
2046 struct xhci_command *command);
2047struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2048 int type, gfp_t flags);
2049void xhci_free_container_ctx(struct xhci_hcd *xhci,
2050 struct xhci_container_ctx *ctx);
2051
2052
2053typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2054int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2055void xhci_quiesce(struct xhci_hcd *xhci);
2056int xhci_halt(struct xhci_hcd *xhci);
2057int xhci_start(struct xhci_hcd *xhci);
2058int xhci_reset(struct xhci_hcd *xhci);
2059int xhci_run(struct usb_hcd *hcd);
2060int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2061void xhci_shutdown(struct usb_hcd *hcd);
2062void xhci_init_driver(struct hc_driver *drv,
2063 const struct xhci_driver_overrides *over);
2064int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2065int xhci_ext_cap_init(struct xhci_hcd *xhci);
2066
2067int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2068int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2069
2070irqreturn_t xhci_irq(struct usb_hcd *hcd);
2071irqreturn_t xhci_msi_irq(int irq, void *hcd);
2072int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2073int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2074 struct xhci_virt_device *virt_dev,
2075 struct usb_device *hdev,
2076 struct usb_tt *tt, gfp_t mem_flags);
2077
2078
2079dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2080struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2081 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2082 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2083int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2084void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2085int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2086 u32 trb_type, u32 slot_id);
2087int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2088 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2089int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2090 u32 field1, u32 field2, u32 field3, u32 field4);
2091int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2092 int slot_id, unsigned int ep_index, int suspend);
2093int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2094 int slot_id, unsigned int ep_index);
2095int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2096 int slot_id, unsigned int ep_index);
2097int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2098 int slot_id, unsigned int ep_index);
2099int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2100 struct urb *urb, int slot_id, unsigned int ep_index);
2101int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2102 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2103 bool command_must_succeed);
2104int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2105 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2106int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2107 int slot_id, unsigned int ep_index,
2108 enum xhci_ep_reset_type reset_type);
2109int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2110 u32 slot_id);
2111void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2112 unsigned int slot_id, unsigned int ep_index,
2113 unsigned int stream_id, struct xhci_td *cur_td,
2114 struct xhci_dequeue_state *state);
2115void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2116 unsigned int slot_id, unsigned int ep_index,
2117 struct xhci_dequeue_state *deq_state);
2118void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2119 unsigned int stream_id, struct xhci_td *td);
2120void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2121void xhci_handle_command_timeout(struct work_struct *work);
2122
2123void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2124 unsigned int ep_index, unsigned int stream_id);
2125void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2126 unsigned int slot_id,
2127 unsigned int ep_index);
2128void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2129void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2130unsigned int count_trbs(u64 addr, u64 len);
2131
2132
2133void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2134 u32 link_state);
2135void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2136 u32 port_bit);
2137int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2138 char *buf, u16 wLength);
2139int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2140int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2141struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2142
2143void xhci_hc_died(struct xhci_hcd *xhci);
2144
2145#ifdef CONFIG_PM
2146int xhci_bus_suspend(struct usb_hcd *hcd);
2147int xhci_bus_resume(struct usb_hcd *hcd);
2148unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2149#else
2150#define xhci_bus_suspend NULL
2151#define xhci_bus_resume NULL
2152#define xhci_get_resuming_ports NULL
2153#endif
2154
2155u32 xhci_port_state_to_neutral(u32 state);
2156int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2157 u16 port);
2158void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2159
2160
2161struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2162struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2163struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2164
2165struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2166 unsigned int slot_id, unsigned int ep_index,
2167 unsigned int stream_id);
2168
2169static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2170 struct urb *urb)
2171{
2172 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2173 xhci_get_endpoint_index(&urb->ep->desc),
2174 urb->stream_id);
2175}
2176
2177
2178
2179
2180
2181
2182static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2183{
2184 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2185 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2186 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2187 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2188 !urb->num_sgs)
2189 return true;
2190
2191 return false;
2192}
2193
2194static inline char *xhci_slot_state_string(u32 state)
2195{
2196 switch (state) {
2197 case SLOT_STATE_ENABLED:
2198 return "enabled/disabled";
2199 case SLOT_STATE_DEFAULT:
2200 return "default";
2201 case SLOT_STATE_ADDRESSED:
2202 return "addressed";
2203 case SLOT_STATE_CONFIGURED:
2204 return "configured";
2205 default:
2206 return "reserved";
2207 }
2208}
2209
2210static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2211 u32 field3)
2212{
2213 static char str[256];
2214 int type = TRB_FIELD_TO_TYPE(field3);
2215
2216 switch (type) {
2217 case TRB_LINK:
2218 sprintf(str,
2219 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2220 field1, field0, GET_INTR_TARGET(field2),
2221 xhci_trb_type_string(type),
2222 field3 & TRB_IOC ? 'I' : 'i',
2223 field3 & TRB_CHAIN ? 'C' : 'c',
2224 field3 & TRB_TC ? 'T' : 't',
2225 field3 & TRB_CYCLE ? 'C' : 'c');
2226 break;
2227 case TRB_TRANSFER:
2228 case TRB_COMPLETION:
2229 case TRB_PORT_STATUS:
2230 case TRB_BANDWIDTH_EVENT:
2231 case TRB_DOORBELL:
2232 case TRB_HC_EVENT:
2233 case TRB_DEV_NOTE:
2234 case TRB_MFINDEX_WRAP:
2235 sprintf(str,
2236 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2237 field1, field0,
2238 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2239 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2240
2241 TRB_TO_EP_INDEX(field3) + 1,
2242 xhci_trb_type_string(type),
2243 field3 & EVENT_DATA ? 'E' : 'e',
2244 field3 & TRB_CYCLE ? 'C' : 'c');
2245
2246 break;
2247 case TRB_SETUP:
2248 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2249 field0 & 0xff,
2250 (field0 & 0xff00) >> 8,
2251 (field0 & 0xff000000) >> 24,
2252 (field0 & 0xff0000) >> 16,
2253 (field1 & 0xff00) >> 8,
2254 field1 & 0xff,
2255 (field1 & 0xff000000) >> 16 |
2256 (field1 & 0xff0000) >> 16,
2257 TRB_LEN(field2), GET_TD_SIZE(field2),
2258 GET_INTR_TARGET(field2),
2259 xhci_trb_type_string(type),
2260 field3 & TRB_IDT ? 'I' : 'i',
2261 field3 & TRB_IOC ? 'I' : 'i',
2262 field3 & TRB_CYCLE ? 'C' : 'c');
2263 break;
2264 case TRB_DATA:
2265 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2266 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2267 GET_INTR_TARGET(field2),
2268 xhci_trb_type_string(type),
2269 field3 & TRB_IDT ? 'I' : 'i',
2270 field3 & TRB_IOC ? 'I' : 'i',
2271 field3 & TRB_CHAIN ? 'C' : 'c',
2272 field3 & TRB_NO_SNOOP ? 'S' : 's',
2273 field3 & TRB_ISP ? 'I' : 'i',
2274 field3 & TRB_ENT ? 'E' : 'e',
2275 field3 & TRB_CYCLE ? 'C' : 'c');
2276 break;
2277 case TRB_STATUS:
2278 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2279 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2280 GET_INTR_TARGET(field2),
2281 xhci_trb_type_string(type),
2282 field3 & TRB_IOC ? 'I' : 'i',
2283 field3 & TRB_CHAIN ? 'C' : 'c',
2284 field3 & TRB_ENT ? 'E' : 'e',
2285 field3 & TRB_CYCLE ? 'C' : 'c');
2286 break;
2287 case TRB_NORMAL:
2288 case TRB_ISOC:
2289 case TRB_EVENT_DATA:
2290 case TRB_TR_NOOP:
2291 sprintf(str,
2292 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2293 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2294 GET_INTR_TARGET(field2),
2295 xhci_trb_type_string(type),
2296 field3 & TRB_BEI ? 'B' : 'b',
2297 field3 & TRB_IDT ? 'I' : 'i',
2298 field3 & TRB_IOC ? 'I' : 'i',
2299 field3 & TRB_CHAIN ? 'C' : 'c',
2300 field3 & TRB_NO_SNOOP ? 'S' : 's',
2301 field3 & TRB_ISP ? 'I' : 'i',
2302 field3 & TRB_ENT ? 'E' : 'e',
2303 field3 & TRB_CYCLE ? 'C' : 'c');
2304 break;
2305
2306 case TRB_CMD_NOOP:
2307 case TRB_ENABLE_SLOT:
2308 sprintf(str,
2309 "%s: flags %c",
2310 xhci_trb_type_string(type),
2311 field3 & TRB_CYCLE ? 'C' : 'c');
2312 break;
2313 case TRB_DISABLE_SLOT:
2314 case TRB_NEG_BANDWIDTH:
2315 sprintf(str,
2316 "%s: slot %d flags %c",
2317 xhci_trb_type_string(type),
2318 TRB_TO_SLOT_ID(field3),
2319 field3 & TRB_CYCLE ? 'C' : 'c');
2320 break;
2321 case TRB_ADDR_DEV:
2322 sprintf(str,
2323 "%s: ctx %08x%08x slot %d flags %c:%c",
2324 xhci_trb_type_string(type),
2325 field1, field0,
2326 TRB_TO_SLOT_ID(field3),
2327 field3 & TRB_BSR ? 'B' : 'b',
2328 field3 & TRB_CYCLE ? 'C' : 'c');
2329 break;
2330 case TRB_CONFIG_EP:
2331 sprintf(str,
2332 "%s: ctx %08x%08x slot %d flags %c:%c",
2333 xhci_trb_type_string(type),
2334 field1, field0,
2335 TRB_TO_SLOT_ID(field3),
2336 field3 & TRB_DC ? 'D' : 'd',
2337 field3 & TRB_CYCLE ? 'C' : 'c');
2338 break;
2339 case TRB_EVAL_CONTEXT:
2340 sprintf(str,
2341 "%s: ctx %08x%08x slot %d flags %c",
2342 xhci_trb_type_string(type),
2343 field1, field0,
2344 TRB_TO_SLOT_ID(field3),
2345 field3 & TRB_CYCLE ? 'C' : 'c');
2346 break;
2347 case TRB_RESET_EP:
2348 sprintf(str,
2349 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2350 xhci_trb_type_string(type),
2351 field1, field0,
2352 TRB_TO_SLOT_ID(field3),
2353
2354 TRB_TO_EP_INDEX(field3) + 1,
2355 field3 & TRB_TSP ? 'T' : 't',
2356 field3 & TRB_CYCLE ? 'C' : 'c');
2357 break;
2358 case TRB_STOP_RING:
2359 sprintf(str,
2360 "%s: slot %d sp %d ep %d flags %c",
2361 xhci_trb_type_string(type),
2362 TRB_TO_SLOT_ID(field3),
2363 TRB_TO_SUSPEND_PORT(field3),
2364
2365 TRB_TO_EP_INDEX(field3) + 1,
2366 field3 & TRB_CYCLE ? 'C' : 'c');
2367 break;
2368 case TRB_SET_DEQ:
2369 sprintf(str,
2370 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2371 xhci_trb_type_string(type),
2372 field1, field0,
2373 TRB_TO_STREAM_ID(field2),
2374 TRB_TO_SLOT_ID(field3),
2375
2376 TRB_TO_EP_INDEX(field3) + 1,
2377 field3 & TRB_CYCLE ? 'C' : 'c');
2378 break;
2379 case TRB_RESET_DEV:
2380 sprintf(str,
2381 "%s: slot %d flags %c",
2382 xhci_trb_type_string(type),
2383 TRB_TO_SLOT_ID(field3),
2384 field3 & TRB_CYCLE ? 'C' : 'c');
2385 break;
2386 case TRB_FORCE_EVENT:
2387 sprintf(str,
2388 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2389 xhci_trb_type_string(type),
2390 field1, field0,
2391 TRB_TO_VF_INTR_TARGET(field2),
2392 TRB_TO_VF_ID(field3),
2393 field3 & TRB_CYCLE ? 'C' : 'c');
2394 break;
2395 case TRB_SET_LT:
2396 sprintf(str,
2397 "%s: belt %d flags %c",
2398 xhci_trb_type_string(type),
2399 TRB_TO_BELT(field3),
2400 field3 & TRB_CYCLE ? 'C' : 'c');
2401 break;
2402 case TRB_GET_BW:
2403 sprintf(str,
2404 "%s: ctx %08x%08x slot %d speed %d flags %c",
2405 xhci_trb_type_string(type),
2406 field1, field0,
2407 TRB_TO_SLOT_ID(field3),
2408 TRB_TO_DEV_SPEED(field3),
2409 field3 & TRB_CYCLE ? 'C' : 'c');
2410 break;
2411 case TRB_FORCE_HEADER:
2412 sprintf(str,
2413 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2414 xhci_trb_type_string(type),
2415 field2, field1, field0 & 0xffffffe0,
2416 TRB_TO_PACKET_TYPE(field0),
2417 TRB_TO_ROOTHUB_PORT(field3),
2418 field3 & TRB_CYCLE ? 'C' : 'c');
2419 break;
2420 default:
2421 sprintf(str,
2422 "type '%s' -> raw %08x %08x %08x %08x",
2423 xhci_trb_type_string(type),
2424 field0, field1, field2, field3);
2425 }
2426
2427 return str;
2428}
2429
2430static inline const char *xhci_decode_ctrl_ctx(unsigned long drop,
2431 unsigned long add)
2432{
2433 static char str[1024];
2434 unsigned int bit;
2435 int ret = 0;
2436
2437 if (drop) {
2438 ret = sprintf(str, "Drop:");
2439 for_each_set_bit(bit, &drop, 32)
2440 ret += sprintf(str + ret, " %d%s",
2441 bit / 2,
2442 bit % 2 ? "in":"out");
2443 ret += sprintf(str + ret, ", ");
2444 }
2445
2446 if (add) {
2447 ret += sprintf(str + ret, "Add:%s%s",
2448 (add & SLOT_FLAG) ? " slot":"",
2449 (add & EP0_FLAG) ? " ep0":"");
2450 add &= ~(SLOT_FLAG | EP0_FLAG);
2451 for_each_set_bit(bit, &add, 32)
2452 ret += sprintf(str + ret, " %d%s",
2453 bit / 2,
2454 bit % 2 ? "in":"out");
2455 }
2456 return str;
2457}
2458
2459static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2460 u32 tt_info, u32 state)
2461{
2462 static char str[1024];
2463 u32 speed;
2464 u32 hub;
2465 u32 mtt;
2466 int ret = 0;
2467
2468 speed = info & DEV_SPEED;
2469 hub = info & DEV_HUB;
2470 mtt = info & DEV_MTT;
2471
2472 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2473 info & ROUTE_STRING_MASK,
2474 ({ char *s;
2475 switch (speed) {
2476 case SLOT_SPEED_FS:
2477 s = "full-speed";
2478 break;
2479 case SLOT_SPEED_LS:
2480 s = "low-speed";
2481 break;
2482 case SLOT_SPEED_HS:
2483 s = "high-speed";
2484 break;
2485 case SLOT_SPEED_SS:
2486 s = "super-speed";
2487 break;
2488 case SLOT_SPEED_SSP:
2489 s = "super-speed plus";
2490 break;
2491 default:
2492 s = "UNKNOWN speed";
2493 } s; }),
2494 mtt ? " multi-TT" : "",
2495 hub ? " Hub" : "",
2496 (info & LAST_CTX_MASK) >> 27,
2497 info2 & MAX_EXIT,
2498 DEVINFO_TO_ROOT_HUB_PORT(info2),
2499 DEVINFO_TO_MAX_PORTS(info2));
2500
2501 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2502 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2503 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2504 state & DEV_ADDR_MASK,
2505 xhci_slot_state_string(GET_SLOT_STATE(state)));
2506
2507 return str;
2508}
2509
2510
2511static inline const char *xhci_portsc_link_state_string(u32 portsc)
2512{
2513 switch (portsc & PORT_PLS_MASK) {
2514 case XDEV_U0:
2515 return "U0";
2516 case XDEV_U1:
2517 return "U1";
2518 case XDEV_U2:
2519 return "U2";
2520 case XDEV_U3:
2521 return "U3";
2522 case XDEV_DISABLED:
2523 return "Disabled";
2524 case XDEV_RXDETECT:
2525 return "RxDetect";
2526 case XDEV_INACTIVE:
2527 return "Inactive";
2528 case XDEV_POLLING:
2529 return "Polling";
2530 case XDEV_RECOVERY:
2531 return "Recovery";
2532 case XDEV_HOT_RESET:
2533 return "Hot Reset";
2534 case XDEV_COMP_MODE:
2535 return "Compliance mode";
2536 case XDEV_TEST_MODE:
2537 return "Test mode";
2538 case XDEV_RESUME:
2539 return "Resume";
2540 default:
2541 break;
2542 }
2543 return "Unknown";
2544}
2545
2546static inline const char *xhci_decode_portsc(u32 portsc)
2547{
2548 static char str[256];
2549 int ret;
2550
2551 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2552 portsc & PORT_POWER ? "Powered" : "Powered-off",
2553 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2554 portsc & PORT_PE ? "Enabled" : "Disabled",
2555 xhci_portsc_link_state_string(portsc),
2556 DEV_PORT_SPEED(portsc));
2557
2558 if (portsc & PORT_OC)
2559 ret += sprintf(str + ret, "OverCurrent ");
2560 if (portsc & PORT_RESET)
2561 ret += sprintf(str + ret, "In-Reset ");
2562
2563 ret += sprintf(str + ret, "Change: ");
2564 if (portsc & PORT_CSC)
2565 ret += sprintf(str + ret, "CSC ");
2566 if (portsc & PORT_PEC)
2567 ret += sprintf(str + ret, "PEC ");
2568 if (portsc & PORT_WRC)
2569 ret += sprintf(str + ret, "WRC ");
2570 if (portsc & PORT_OCC)
2571 ret += sprintf(str + ret, "OCC ");
2572 if (portsc & PORT_RC)
2573 ret += sprintf(str + ret, "PRC ");
2574 if (portsc & PORT_PLC)
2575 ret += sprintf(str + ret, "PLC ");
2576 if (portsc & PORT_CEC)
2577 ret += sprintf(str + ret, "CEC ");
2578 if (portsc & PORT_CAS)
2579 ret += sprintf(str + ret, "CAS ");
2580
2581 ret += sprintf(str + ret, "Wake: ");
2582 if (portsc & PORT_WKCONN_E)
2583 ret += sprintf(str + ret, "WCE ");
2584 if (portsc & PORT_WKDISC_E)
2585 ret += sprintf(str + ret, "WDE ");
2586 if (portsc & PORT_WKOC_E)
2587 ret += sprintf(str + ret, "WOE ");
2588
2589 return str;
2590}
2591
2592static inline const char *xhci_decode_doorbell(u32 slot, u32 doorbell)
2593{
2594 static char str[256];
2595 u8 ep;
2596 u16 stream;
2597 int ret;
2598
2599 ep = (doorbell & 0xff);
2600 stream = doorbell >> 16;
2601
2602 if (slot == 0) {
2603 sprintf(str, "Command Ring %d", doorbell);
2604 return str;
2605 }
2606 ret = sprintf(str, "Slot %d ", slot);
2607 if (ep > 0 && ep < 32)
2608 ret = sprintf(str + ret, "ep%d%s",
2609 ep / 2,
2610 ep % 2 ? "in" : "out");
2611 else if (ep == 0 || ep < 248)
2612 ret = sprintf(str + ret, "Reserved %d", ep);
2613 else
2614 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2615 if (stream)
2616 ret = sprintf(str + ret, " Stream %d", stream);
2617
2618 return str;
2619}
2620
2621static inline const char *xhci_ep_state_string(u8 state)
2622{
2623 switch (state) {
2624 case EP_STATE_DISABLED:
2625 return "disabled";
2626 case EP_STATE_RUNNING:
2627 return "running";
2628 case EP_STATE_HALTED:
2629 return "halted";
2630 case EP_STATE_STOPPED:
2631 return "stopped";
2632 case EP_STATE_ERROR:
2633 return "error";
2634 default:
2635 return "INVALID";
2636 }
2637}
2638
2639static inline const char *xhci_ep_type_string(u8 type)
2640{
2641 switch (type) {
2642 case ISOC_OUT_EP:
2643 return "Isoc OUT";
2644 case BULK_OUT_EP:
2645 return "Bulk OUT";
2646 case INT_OUT_EP:
2647 return "Int OUT";
2648 case CTRL_EP:
2649 return "Ctrl";
2650 case ISOC_IN_EP:
2651 return "Isoc IN";
2652 case BULK_IN_EP:
2653 return "Bulk IN";
2654 case INT_IN_EP:
2655 return "Int IN";
2656 default:
2657 return "INVALID";
2658 }
2659}
2660
2661static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2662 u32 tx_info)
2663{
2664 static char str[1024];
2665 int ret;
2666
2667 u32 esit;
2668 u16 maxp;
2669 u16 avg;
2670
2671 u8 max_pstr;
2672 u8 ep_state;
2673 u8 interval;
2674 u8 ep_type;
2675 u8 burst;
2676 u8 cerr;
2677 u8 mult;
2678
2679 bool lsa;
2680 bool hid;
2681
2682 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2683 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2684
2685 ep_state = info & EP_STATE_MASK;
2686 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2687 interval = CTX_TO_EP_INTERVAL(info);
2688 mult = CTX_TO_EP_MULT(info) + 1;
2689 lsa = !!(info & EP_HAS_LSA);
2690
2691 cerr = (info2 & (3 << 1)) >> 1;
2692 ep_type = CTX_TO_EP_TYPE(info2);
2693 hid = !!(info2 & (1 << 7));
2694 burst = CTX_TO_MAX_BURST(info2);
2695 maxp = MAX_PACKET_DECODED(info2);
2696
2697 avg = EP_AVG_TRB_LENGTH(tx_info);
2698
2699 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2700 xhci_ep_state_string(ep_state), mult,
2701 max_pstr, lsa ? "LSA " : "");
2702
2703 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2704 (1 << interval) * 125, esit, cerr);
2705
2706 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2707 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2708 burst, maxp, deq);
2709
2710 ret += sprintf(str + ret, "avg trb len %d", avg);
2711
2712 return str;
2713}
2714
2715#endif
2716