LXR linux/include/linux/perf/arm

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 *  linux/arch/arm/include/asm/pmu.h
   4 *
   5 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
   6 */
   7
   8#ifndef __ARM_PMU_H__
   9#define __ARM_PMU_H__
  10
  11#include <linux/interrupt.h>
  12#include <linux/perf_event.h>
  13#include <linux/platform_device.h>
  14#include <linux/sysfs.h>
  15#include <asm/cputype.h>
  16
  17#ifdef CONFIG_ARM_PMU
  18
  19/*
  20 * The ARMv7 CPU PMU supports up to 32 event counters.
  21 */
  22#define ARMPMU_MAX_HWEVENTS             32
  23
  24/*
  25 * ARM PMU hw_event flags
  26 */
  27/* Event uses a 64bit counter */
  28#define ARMPMU_EVT_64BIT                1
  29
  30#define HW_OP_UNSUPPORTED               0xFFFF
  31#define C(_x)                           PERF_COUNT_HW_CACHE_##_x
  32#define CACHE_OP_UNSUPPORTED            0xFFFF
  33
  34#define PERF_MAP_ALL_UNSUPPORTED                                        \
  35        [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
  36
  37#define PERF_CACHE_MAP_ALL_UNSUPPORTED                                  \
  38[0 ... C(MAX) - 1] = {                                                  \
  39        [0 ... C(OP_MAX) - 1] = {                                       \
  40                [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,       \
  41        },                                                              \
  42}
  43
  44/* The events for a given PMU register set. */
  45struct pmu_hw_events {
  46        /*
  47         * The events that are active on the PMU for the given index.
  48         */
  49        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  50
  51        /*
  52         * A 1 bit for an index indicates that the counter is being used for
  53         * an event. A 0 means that the counter can be used.
  54         */
  55        DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
  56
  57        /*
  58         * Hardware lock to serialize accesses to PMU registers. Needed for the
  59         * read/modify/write sequences.
  60         */
  61        raw_spinlock_t          pmu_lock;
  62
  63        /*
  64         * When using percpu IRQs, we need a percpu dev_id. Place it here as we
  65         * already have to allocate this struct per cpu.
  66         */
  67        struct arm_pmu          *percpu_pmu;
  68
  69        int irq;
  70};
  71
  72enum armpmu_attr_groups {
  73        ARMPMU_ATTR_GROUP_COMMON,
  74        ARMPMU_ATTR_GROUP_EVENTS,
  75        ARMPMU_ATTR_GROUP_FORMATS,
  76        ARMPMU_NR_ATTR_GROUPS
  77};
  78
  79struct arm_pmu {
  80        struct pmu      pmu;
  81        cpumask_t       supported_cpus;
  82        char            *name;
  83        irqreturn_t     (*handle_irq)(struct arm_pmu *pmu);
  84        void            (*enable)(struct perf_event *event);
  85        void            (*disable)(struct perf_event *event);
  86        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
  87                                         struct perf_event *event);
  88        void            (*clear_event_idx)(struct pmu_hw_events *hw_events,
  89                                         struct perf_event *event);
  90        int             (*set_event_filter)(struct hw_perf_event *evt,
  91                                            struct perf_event_attr *attr);
  92        u64             (*read_counter)(struct perf_event *event);
  93        void            (*write_counter)(struct perf_event *event, u64 val);
  94        void            (*start)(struct arm_pmu *);
  95        void            (*stop)(struct arm_pmu *);
  96        void            (*reset)(void *);
  97        int             (*map_event)(struct perf_event *event);
  98        int             (*filter_match)(struct perf_event *event);
  99        int             num_events;
 100        bool            secure_access; /* 32-bit ARM only */
 101#define ARMV8_PMUV3_MAX_COMMON_EVENTS           0x40
 102        DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 103#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE       0x4000
 104        DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 105        struct platform_device  *plat_device;
 106        struct pmu_hw_events    __percpu *hw_events;
 107        struct hlist_node       node;
 108        struct notifier_block   cpu_pm_nb;
 109        /* the attr_groups array must be NULL-terminated */
 110        const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
 111
 112        /* Only to be used by ACPI probing code */
 113        unsigned long acpi_cpuid;
 114};
 115
 116#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 117
 118u64 armpmu_event_update(struct perf_event *event);
 119
 120int armpmu_event_set_period(struct perf_event *event);
 121
 122int armpmu_map_event(struct perf_event *event,
 123                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 124                     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
 125                                                [PERF_COUNT_HW_CACHE_OP_MAX]
 126                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
 127                     u32 raw_event_mask);
 128
 129typedef int (*armpmu_init_fn)(struct arm_pmu *);
 130
 131struct pmu_probe_info {
 132        unsigned int cpuid;
 133        unsigned int mask;
 134        armpmu_init_fn init;
 135};
 136
 137#define PMU_PROBE(_cpuid, _mask, _fn)   \
 138{                                       \
 139        .cpuid = (_cpuid),              \
 140        .mask = (_mask),                \
 141        .init = (_fn),                  \
 142}
 143
 144#define ARM_PMU_PROBE(_cpuid, _fn) \
 145        PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
 146
 147#define ARM_PMU_XSCALE_MASK     ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
 148
 149#define XSCALE_PMU_PROBE(_version, _fn) \
 150        PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
 151
 152int arm_pmu_device_probe(struct platform_device *pdev,
 153                         const struct of_device_id *of_table,
 154                         const struct pmu_probe_info *probe_table);
 155
 156#ifdef CONFIG_ACPI
 157int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
 158#else
 159static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
 160#endif
 161
 162/* Internal functions only for core arm_pmu code */
 163struct arm_pmu *armpmu_alloc(void);
 164struct arm_pmu *armpmu_alloc_atomic(void);
 165void armpmu_free(struct arm_pmu *pmu);
 166int armpmu_register(struct arm_pmu *pmu);
 167int armpmu_request_irq(int irq, int cpu);
 168void armpmu_free_irq(int irq, int cpu);
 169
 170#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
 171
 172#endif /* CONFIG_ARM_PMU */
 173
 174#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
 175
 176#endif /* __ARM_PMU_H__ */
 177