linux/include/media/h264-ctrls.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * These are the H.264 state controls for use with stateless H.264
   4 * codec drivers.
   5 *
   6 * It turns out that these structs are not stable yet and will undergo
   7 * more changes. So keep them private until they are stable and ready to
   8 * become part of the official public API.
   9 */
  10
  11#ifndef _H264_CTRLS_H_
  12#define _H264_CTRLS_H_
  13
  14#include <linux/videodev2.h>
  15
  16/* Our pixel format isn't stable at the moment */
  17#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */
  18
  19/*
  20 * This is put insanely high to avoid conflicting with controls that
  21 * would be added during the phase where those controls are not
  22 * stable. It should be fixed eventually.
  23 */
  24#define V4L2_CID_MPEG_VIDEO_H264_SPS            (V4L2_CID_MPEG_BASE+1000)
  25#define V4L2_CID_MPEG_VIDEO_H264_PPS            (V4L2_CID_MPEG_BASE+1001)
  26#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002)
  27#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS   (V4L2_CID_MPEG_BASE+1003)
  28#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS  (V4L2_CID_MPEG_BASE+1004)
  29#define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE    (V4L2_CID_MPEG_BASE+1005)
  30#define V4L2_CID_MPEG_VIDEO_H264_START_CODE     (V4L2_CID_MPEG_BASE+1006)
  31
  32/* enum v4l2_ctrl_type type values */
  33#define V4L2_CTRL_TYPE_H264_SPS                 0x0110
  34#define V4L2_CTRL_TYPE_H264_PPS                 0x0111
  35#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX      0x0112
  36#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS        0x0113
  37#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS       0x0114
  38
  39enum v4l2_mpeg_video_h264_decode_mode {
  40        V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED,
  41        V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED,
  42};
  43
  44enum v4l2_mpeg_video_h264_start_code {
  45        V4L2_MPEG_VIDEO_H264_START_CODE_NONE,
  46        V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B,
  47};
  48
  49#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG                      0x01
  50#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG                      0x02
  51#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG                      0x04
  52#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG                      0x08
  53#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG                      0x10
  54#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG                      0x20
  55
  56#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE                0x01
  57#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS      0x02
  58#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO          0x04
  59#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED      0x08
  60#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY                       0x10
  61#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD              0x20
  62#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE                 0x40
  63
  64struct v4l2_ctrl_h264_sps {
  65        __u8 profile_idc;
  66        __u8 constraint_set_flags;
  67        __u8 level_idc;
  68        __u8 seq_parameter_set_id;
  69        __u8 chroma_format_idc;
  70        __u8 bit_depth_luma_minus8;
  71        __u8 bit_depth_chroma_minus8;
  72        __u8 log2_max_frame_num_minus4;
  73        __u8 pic_order_cnt_type;
  74        __u8 log2_max_pic_order_cnt_lsb_minus4;
  75        __u8 max_num_ref_frames;
  76        __u8 num_ref_frames_in_pic_order_cnt_cycle;
  77        __s32 offset_for_ref_frame[255];
  78        __s32 offset_for_non_ref_pic;
  79        __s32 offset_for_top_to_bottom_field;
  80        __u16 pic_width_in_mbs_minus1;
  81        __u16 pic_height_in_map_units_minus1;
  82        __u32 flags;
  83};
  84
  85#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE                          0x0001
  86#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT      0x0002
  87#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED                                0x0004
  88#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT            0x0008
  89#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED                       0x0010
  90#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT                    0x0020
  91#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE                           0x0040
  92#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT                   0x0080
  93
  94struct v4l2_ctrl_h264_pps {
  95        __u8 pic_parameter_set_id;
  96        __u8 seq_parameter_set_id;
  97        __u8 num_slice_groups_minus1;
  98        __u8 num_ref_idx_l0_default_active_minus1;
  99        __u8 num_ref_idx_l1_default_active_minus1;
 100        __u8 weighted_bipred_idc;
 101        __s8 pic_init_qp_minus26;
 102        __s8 pic_init_qs_minus26;
 103        __s8 chroma_qp_index_offset;
 104        __s8 second_chroma_qp_index_offset;
 105        __u16 flags;
 106};
 107
 108struct v4l2_ctrl_h264_scaling_matrix {
 109        __u8 scaling_list_4x4[6][16];
 110        __u8 scaling_list_8x8[6][64];
 111};
 112
 113struct v4l2_h264_weight_factors {
 114        __s16 luma_weight[32];
 115        __s16 luma_offset[32];
 116        __s16 chroma_weight[32][2];
 117        __s16 chroma_offset[32][2];
 118};
 119
 120struct v4l2_h264_pred_weight_table {
 121        __u16 luma_log2_weight_denom;
 122        __u16 chroma_log2_weight_denom;
 123        struct v4l2_h264_weight_factors weight_factors[2];
 124};
 125
 126#define V4L2_H264_SLICE_TYPE_P                          0
 127#define V4L2_H264_SLICE_TYPE_B                          1
 128#define V4L2_H264_SLICE_TYPE_I                          2
 129#define V4L2_H264_SLICE_TYPE_SP                         3
 130#define V4L2_H264_SLICE_TYPE_SI                         4
 131
 132#define V4L2_H264_SLICE_FLAG_FIELD_PIC                  0x01
 133#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD               0x02
 134#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED     0x04
 135#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH              0x08
 136
 137struct v4l2_ctrl_h264_slice_params {
 138        /* Size in bytes, including header */
 139        __u32 size;
 140
 141        /* Offset in bytes to the start of slice in the OUTPUT buffer. */
 142        __u32 start_byte_offset;
 143
 144        /* Offset in bits to slice_data() from the beginning of this slice. */
 145        __u32 header_bit_size;
 146
 147        __u16 first_mb_in_slice;
 148        __u8 slice_type;
 149        __u8 pic_parameter_set_id;
 150        __u8 colour_plane_id;
 151        __u8 redundant_pic_cnt;
 152        __u16 frame_num;
 153        __u16 idr_pic_id;
 154        __u16 pic_order_cnt_lsb;
 155        __s32 delta_pic_order_cnt_bottom;
 156        __s32 delta_pic_order_cnt0;
 157        __s32 delta_pic_order_cnt1;
 158
 159        struct v4l2_h264_pred_weight_table pred_weight_table;
 160        /* Size in bits of dec_ref_pic_marking() syntax element. */
 161        __u32 dec_ref_pic_marking_bit_size;
 162        /* Size in bits of pic order count syntax. */
 163        __u32 pic_order_cnt_bit_size;
 164
 165        __u8 cabac_init_idc;
 166        __s8 slice_qp_delta;
 167        __s8 slice_qs_delta;
 168        __u8 disable_deblocking_filter_idc;
 169        __s8 slice_alpha_c0_offset_div2;
 170        __s8 slice_beta_offset_div2;
 171        __u8 num_ref_idx_l0_active_minus1;
 172        __u8 num_ref_idx_l1_active_minus1;
 173        __u32 slice_group_change_cycle;
 174
 175        /*
 176         * Entries on each list are indices into
 177         * v4l2_ctrl_h264_decode_params.dpb[].
 178         */
 179        __u8 ref_pic_list0[32];
 180        __u8 ref_pic_list1[32];
 181
 182        __u32 flags;
 183};
 184
 185#define V4L2_H264_DPB_ENTRY_FLAG_VALID          0x01
 186#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE         0x02
 187#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM      0x04
 188
 189struct v4l2_h264_dpb_entry {
 190        __u64 reference_ts;
 191        __u16 frame_num;
 192        __u16 pic_num;
 193        /* Note that field is indicated by v4l2_buffer.field */
 194        __s32 top_field_order_cnt;
 195        __s32 bottom_field_order_cnt;
 196        __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */
 197};
 198
 199#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC     0x01
 200
 201struct v4l2_ctrl_h264_decode_params {
 202        struct v4l2_h264_dpb_entry dpb[16];
 203        __u16 num_slices;
 204        __u16 nal_ref_idc;
 205        __s32 top_field_order_cnt;
 206        __s32 bottom_field_order_cnt;
 207        __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */
 208};
 209
 210#endif
 211