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12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/log2.h>
19
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23
24#define SUN8I_SYSCLK_CTL 0x00c
25#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
26#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9
27#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8
28#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
29#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
30#define SUN8I_MOD_CLK_ENA 0x010
31#define SUN8I_MOD_CLK_ENA_AIF1 15
32#define SUN8I_MOD_CLK_ENA_ADC 3
33#define SUN8I_MOD_CLK_ENA_DAC 2
34#define SUN8I_MOD_RST_CTL 0x014
35#define SUN8I_MOD_RST_CTL_AIF1 15
36#define SUN8I_MOD_RST_CTL_ADC 3
37#define SUN8I_MOD_RST_CTL_DAC 2
38#define SUN8I_SYS_SR_CTRL 0x018
39#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
40#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
41#define SUN8I_AIF1CLK_CTRL 0x040
42#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
43#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
44#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
45#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
46#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
47#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
48#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
49#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
50#define SUN8I_AIF1_ADCDAT_CTRL 0x044
51#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA 15
52#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA 14
53#define SUN8I_AIF1_DACDAT_CTRL 0x048
54#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
55#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
56#define SUN8I_AIF1_MXR_SRC 0x04c
57#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L 15
58#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL 14
59#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL 13
60#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR 12
61#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11
62#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10
63#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9
64#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8
65#define SUN8I_ADC_DIG_CTRL 0x100
66#define SUN8I_ADC_DIG_CTRL_ENDA 15
67#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2
68#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1
69#define SUN8I_DAC_DIG_CTRL 0x120
70#define SUN8I_DAC_DIG_CTRL_ENDA 15
71#define SUN8I_DAC_MXR_SRC 0x130
72#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
73#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
74#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
75#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
76#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
77#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
78#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
79#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
80
81#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
82#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
83#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
84#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
85#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
86#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
87
88struct sun8i_codec {
89 struct device *dev;
90 struct regmap *regmap;
91 struct clk *clk_module;
92 struct clk *clk_bus;
93};
94
95static int sun8i_codec_runtime_resume(struct device *dev)
96{
97 struct sun8i_codec *scodec = dev_get_drvdata(dev);
98 int ret;
99
100 ret = clk_prepare_enable(scodec->clk_module);
101 if (ret) {
102 dev_err(dev, "Failed to enable the module clock\n");
103 return ret;
104 }
105
106 ret = clk_prepare_enable(scodec->clk_bus);
107 if (ret) {
108 dev_err(dev, "Failed to enable the bus clock\n");
109 goto err_disable_modclk;
110 }
111
112 regcache_cache_only(scodec->regmap, false);
113
114 ret = regcache_sync(scodec->regmap);
115 if (ret) {
116 dev_err(dev, "Failed to sync regmap cache\n");
117 goto err_disable_clk;
118 }
119
120 return 0;
121
122err_disable_clk:
123 clk_disable_unprepare(scodec->clk_bus);
124
125err_disable_modclk:
126 clk_disable_unprepare(scodec->clk_module);
127
128 return ret;
129}
130
131static int sun8i_codec_runtime_suspend(struct device *dev)
132{
133 struct sun8i_codec *scodec = dev_get_drvdata(dev);
134
135 regcache_cache_only(scodec->regmap, true);
136 regcache_mark_dirty(scodec->regmap);
137
138 clk_disable_unprepare(scodec->clk_module);
139 clk_disable_unprepare(scodec->clk_bus);
140
141 return 0;
142}
143
144static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
145{
146 unsigned int rate = params_rate(params);
147
148 switch (rate) {
149 case 8000:
150 case 7350:
151 return 0x0;
152 case 11025:
153 return 0x1;
154 case 12000:
155 return 0x2;
156 case 16000:
157 return 0x3;
158 case 22050:
159 return 0x4;
160 case 24000:
161 return 0x5;
162 case 32000:
163 return 0x6;
164 case 44100:
165 return 0x7;
166 case 48000:
167 return 0x8;
168 case 96000:
169 return 0x9;
170 case 192000:
171 return 0xa;
172 default:
173 return -EINVAL;
174 }
175}
176
177static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
178{
179 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component);
180 u32 value;
181
182
183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
184 case SND_SOC_DAIFMT_CBS_CFS:
185 value = 0x1;
186 break;
187 case SND_SOC_DAIFMT_CBM_CFM:
188 value = 0x0;
189 break;
190 default:
191 return -EINVAL;
192 }
193 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
194 BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
195 value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
196
197
198 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
199 case SND_SOC_DAIFMT_NB_NF:
200 value = 0x0;
201 break;
202 case SND_SOC_DAIFMT_IB_IF:
203 value = 0x1;
204 break;
205 default:
206 return -EINVAL;
207 }
208 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
209 BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
210 value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
211
212
213
214
215
216
217
218
219
220
221
222 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
223 BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
224 !value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
225
226
227 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
228 case SND_SOC_DAIFMT_I2S:
229 value = 0x0;
230 break;
231 case SND_SOC_DAIFMT_LEFT_J:
232 value = 0x1;
233 break;
234 case SND_SOC_DAIFMT_RIGHT_J:
235 value = 0x2;
236 break;
237 case SND_SOC_DAIFMT_DSP_A:
238 case SND_SOC_DAIFMT_DSP_B:
239 value = 0x3;
240 break;
241 default:
242 return -EINVAL;
243 }
244 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
245 SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK,
246 value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
247
248 return 0;
249}
250
251struct sun8i_codec_clk_div {
252 u8 div;
253 u8 val;
254};
255
256static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = {
257 { .div = 1, .val = 0 },
258 { .div = 2, .val = 1 },
259 { .div = 4, .val = 2 },
260 { .div = 6, .val = 3 },
261 { .div = 8, .val = 4 },
262 { .div = 12, .val = 5 },
263 { .div = 16, .val = 6 },
264 { .div = 24, .val = 7 },
265 { .div = 32, .val = 8 },
266 { .div = 48, .val = 9 },
267 { .div = 64, .val = 10 },
268 { .div = 96, .val = 11 },
269 { .div = 128, .val = 12 },
270 { .div = 192, .val = 13 },
271};
272
273static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec,
274 unsigned int rate,
275 unsigned int word_size)
276{
277 unsigned long clk_rate = clk_get_rate(scodec->clk_module);
278 unsigned int div = clk_rate / rate / word_size / 2;
279 unsigned int best_val = 0, best_diff = ~0;
280 int i;
281
282 for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) {
283 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i];
284 unsigned int diff = abs(bdiv->div - div);
285
286 if (diff < best_diff) {
287 best_diff = diff;
288 best_val = bdiv->val;
289 }
290 }
291
292 return best_val;
293}
294
295static int sun8i_codec_get_lrck_div(unsigned int channels,
296 unsigned int word_size)
297{
298 unsigned int div = word_size * channels;
299
300 if (div < 16 || div > 256)
301 return -EINVAL;
302
303 return ilog2(div) - 4;
304}
305
306static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
307 struct snd_pcm_hw_params *params,
308 struct snd_soc_dai *dai)
309{
310 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component);
311 int sample_rate, lrck_div;
312 u8 bclk_div;
313
314
315
316
317
318 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
319 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
320 SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
321
322 bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16);
323 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
324 SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK,
325 bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV);
326
327 lrck_div = sun8i_codec_get_lrck_div(params_channels(params),
328 params_physical_width(params));
329 if (lrck_div < 0)
330 return lrck_div;
331
332 regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
333 SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
334 lrck_div << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV);
335
336 sample_rate = sun8i_codec_get_hw_rate(params);
337 if (sample_rate < 0)
338 return sample_rate;
339
340 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
341 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
342 sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
343 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
344 SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
345 sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
346
347 return 0;
348}
349
350static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
351 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
352 SUN8I_DAC_MXR_SRC,
353 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
354 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
355 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
356 SUN8I_DAC_MXR_SRC,
357 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
358 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
359 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
360 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
361 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
362 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
363 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
364 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
365};
366
367static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {
368 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
369 SUN8I_AIF1_MXR_SRC,
370 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
371 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
372 SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,
373 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,
374 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
375 SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
376 SUN8I_AIF1_MXR_SRC,
377 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,
378 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
379 SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
380 SUN8I_AIF1_MXR_SRC,
381 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,
382 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
383};
384
385static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
386
387 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
388 0, NULL, 0),
389 SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA,
390 0, NULL, 0),
391
392
393 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
394 SUN8I_AIF1_DACDAT_CTRL,
395 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
396 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
397 SUN8I_AIF1_DACDAT_CTRL,
398 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
399
400
401 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left ADC", "Capture", 0,
402 SUN8I_AIF1_ADCDAT_CTRL,
403 SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),
404 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right ADC", "Capture", 0,
405 SUN8I_AIF1_ADCDAT_CTRL,
406 SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
407
408
409 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
410 sun8i_dac_mixer_controls),
411 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
412 sun8i_dac_mixer_controls),
413 SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
414 sun8i_input_mixer_controls),
415 SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
416 sun8i_input_mixer_controls),
417
418
419 SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
420 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
421 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
422 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
423 SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA,
424 SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
425 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
426 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
427 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
428 SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
429
430 SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
431 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
432
433 SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
434 SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
435
436
437 SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
438 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
439 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
440 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
441 SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL,
442 SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
443
444 SND_SOC_DAPM_MIC("Headset Mic", NULL),
445 SND_SOC_DAPM_MIC("Mic", NULL),
446
447};
448
449static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
450
451 { "AIF1", NULL, "SYSCLK AIF1" },
452 { "AIF1 PLL", NULL, "AIF1" },
453 { "RST AIF1", NULL, "AIF1 PLL" },
454 { "MODCLK AFI1", NULL, "RST AIF1" },
455 { "DAC", NULL, "MODCLK AFI1" },
456 { "ADC", NULL, "MODCLK AFI1" },
457
458 { "RST DAC", NULL, "SYSCLK" },
459 { "MODCLK DAC", NULL, "RST DAC" },
460 { "DAC", NULL, "MODCLK DAC" },
461
462 { "RST ADC", NULL, "SYSCLK" },
463 { "MODCLK ADC", NULL, "RST ADC" },
464 { "ADC", NULL, "MODCLK ADC" },
465
466
467 { "AIF1 Slot 0 Right", NULL, "DAC" },
468 { "AIF1 Slot 0 Left", NULL, "DAC" },
469
470
471 { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
472 "AIF1 Slot 0 Left"},
473 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
474 "AIF1 Slot 0 Right"},
475
476
477 { "AIF1 Slot 0 Right ADC", NULL, "ADC" },
478 { "AIF1 Slot 0 Left ADC", NULL, "ADC" },
479
480
481 { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
482 "AIF1 Slot 0 Left ADC" },
483 { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
484 "AIF1 Slot 0 Right ADC" },
485};
486
487static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
488 .hw_params = sun8i_codec_hw_params,
489 .set_fmt = sun8i_set_fmt,
490};
491
492static struct snd_soc_dai_driver sun8i_codec_dai = {
493 .name = "sun8i",
494
495 .playback = {
496 .stream_name = "Playback",
497 .channels_min = 1,
498 .channels_max = 2,
499 .rates = SNDRV_PCM_RATE_8000_192000,
500 .formats = SNDRV_PCM_FMTBIT_S16_LE,
501 },
502
503 .capture = {
504 .stream_name = "Capture",
505 .channels_min = 1,
506 .channels_max = 2,
507 .rates = SNDRV_PCM_RATE_8000_192000,
508 .formats = SNDRV_PCM_FMTBIT_S16_LE,
509 .sig_bits = 24,
510 },
511
512 .ops = &sun8i_codec_dai_ops,
513};
514
515static const struct snd_soc_component_driver sun8i_soc_component = {
516 .dapm_widgets = sun8i_codec_dapm_widgets,
517 .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
518 .dapm_routes = sun8i_codec_dapm_routes,
519 .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
520 .idle_bias_on = 1,
521 .use_pmdown_time = 1,
522 .endianness = 1,
523 .non_legacy_dai_naming = 1,
524};
525
526static const struct regmap_config sun8i_codec_regmap_config = {
527 .reg_bits = 32,
528 .reg_stride = 4,
529 .val_bits = 32,
530 .max_register = SUN8I_DAC_MXR_SRC,
531
532 .cache_type = REGCACHE_FLAT,
533};
534
535static int sun8i_codec_probe(struct platform_device *pdev)
536{
537 struct sun8i_codec *scodec;
538 void __iomem *base;
539 int ret;
540
541 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
542 if (!scodec)
543 return -ENOMEM;
544
545 scodec->dev = &pdev->dev;
546
547 scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
548 if (IS_ERR(scodec->clk_module)) {
549 dev_err(&pdev->dev, "Failed to get the module clock\n");
550 return PTR_ERR(scodec->clk_module);
551 }
552
553 scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
554 if (IS_ERR(scodec->clk_bus)) {
555 dev_err(&pdev->dev, "Failed to get the bus clock\n");
556 return PTR_ERR(scodec->clk_bus);
557 }
558
559 base = devm_platform_ioremap_resource(pdev, 0);
560 if (IS_ERR(base)) {
561 dev_err(&pdev->dev, "Failed to map the registers\n");
562 return PTR_ERR(base);
563 }
564
565 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
566 &sun8i_codec_regmap_config);
567 if (IS_ERR(scodec->regmap)) {
568 dev_err(&pdev->dev, "Failed to create our regmap\n");
569 return PTR_ERR(scodec->regmap);
570 }
571
572 platform_set_drvdata(pdev, scodec);
573
574 pm_runtime_enable(&pdev->dev);
575 if (!pm_runtime_enabled(&pdev->dev)) {
576 ret = sun8i_codec_runtime_resume(&pdev->dev);
577 if (ret)
578 goto err_pm_disable;
579 }
580
581 ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component,
582 &sun8i_codec_dai, 1);
583 if (ret) {
584 dev_err(&pdev->dev, "Failed to register codec\n");
585 goto err_suspend;
586 }
587
588 return ret;
589
590err_suspend:
591 if (!pm_runtime_status_suspended(&pdev->dev))
592 sun8i_codec_runtime_suspend(&pdev->dev);
593
594err_pm_disable:
595 pm_runtime_disable(&pdev->dev);
596
597 return ret;
598}
599
600static int sun8i_codec_remove(struct platform_device *pdev)
601{
602 pm_runtime_disable(&pdev->dev);
603 if (!pm_runtime_status_suspended(&pdev->dev))
604 sun8i_codec_runtime_suspend(&pdev->dev);
605
606 return 0;
607}
608
609static const struct of_device_id sun8i_codec_of_match[] = {
610 { .compatible = "allwinner,sun8i-a33-codec" },
611 {}
612};
613MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
614
615static const struct dev_pm_ops sun8i_codec_pm_ops = {
616 SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
617 sun8i_codec_runtime_resume, NULL)
618};
619
620static struct platform_driver sun8i_codec_driver = {
621 .driver = {
622 .name = "sun8i-codec",
623 .of_match_table = sun8i_codec_of_match,
624 .pm = &sun8i_codec_pm_ops,
625 },
626 .probe = sun8i_codec_probe,
627 .remove = sun8i_codec_remove,
628};
629module_platform_driver(sun8i_codec_driver);
630
631MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
632MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>");
633MODULE_LICENSE("GPL");
634MODULE_ALIAS("platform:sun8i-codec");
635
