1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15#ifndef _UAPI_LINUX_PERF_EVENT_H 16#define _UAPI_LINUX_PERF_EVENT_H 17 18#include <linux/types.h> 19#include <linux/ioctl.h> 20#include <asm/byteorder.h> 21 22/* 23 * User-space ABI bits: 24 */ 25 26/* 27 * attr.type 28 */ 29enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38}; 39 40/* 41 * Generalized performance event event_id types, used by the 42 * attr.event_id parameter of the sys_perf_event_open() 43 * syscall: 44 */ 45enum perf_hw_id { 46 /* 47 * Common hardware events, generalized by the kernel: 48 */ 49 PERF_COUNT_HW_CPU_CYCLES = 0, 50 PERF_COUNT_HW_INSTRUCTIONS = 1, 51 PERF_COUNT_HW_CACHE_REFERENCES = 2, 52 PERF_COUNT_HW_CACHE_MISSES = 3, 53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 54 PERF_COUNT_HW_BRANCH_MISSES = 5, 55 PERF_COUNT_HW_BUS_CYCLES = 6, 56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 58 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 59 60 PERF_COUNT_HW_MAX, /* non-ABI */ 61}; 62 63/* 64 * Generalized hardware cache events: 65 * 66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 67 * { read, write, prefetch } x 68 * { accesses, misses } 69 */ 70enum perf_hw_cache_id { 71 PERF_COUNT_HW_CACHE_L1D = 0, 72 PERF_COUNT_HW_CACHE_L1I = 1, 73 PERF_COUNT_HW_CACHE_LL = 2, 74 PERF_COUNT_HW_CACHE_DTLB = 3, 75 PERF_COUNT_HW_CACHE_ITLB = 4, 76 PERF_COUNT_HW_CACHE_BPU = 5, 77 PERF_COUNT_HW_CACHE_NODE = 6, 78 79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 80}; 81 82enum perf_hw_cache_op_id { 83 PERF_COUNT_HW_CACHE_OP_READ = 0, 84 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 86 87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 88}; 89 90enum perf_hw_cache_op_result_id { 91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 93 94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 95}; 96 97/* 98 * Special "software" events provided by the kernel, even if the hardware 99 * does not support performance events. These events measure various 100 * physical and sw events of the kernel (and allow the profiling of them as 101 * well): 102 */ 103enum perf_sw_ids { 104 PERF_COUNT_SW_CPU_CLOCK = 0, 105 PERF_COUNT_SW_TASK_CLOCK = 1, 106 PERF_COUNT_SW_PAGE_FAULTS = 2, 107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 108 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 112 PERF_COUNT_SW_EMULATION_FAULTS = 8, 113 PERF_COUNT_SW_DUMMY = 9, 114 PERF_COUNT_SW_BPF_OUTPUT = 10, 115 116 PERF_COUNT_SW_MAX, /* non-ABI */ 117}; 118 119/* 120 * Bits that can be set in attr.sample_type to request information 121 * in the overflow packets. 122 */ 123enum perf_event_sample_format { 124 PERF_SAMPLE_IP = 1U << 0, 125 PERF_SAMPLE_TID = 1U << 1, 126 PERF_SAMPLE_TIME = 1U << 2, 127 PERF_SAMPLE_ADDR = 1U << 3, 128 PERF_SAMPLE_READ = 1U << 4, 129 PERF_SAMPLE_CALLCHAIN = 1U << 5, 130 PERF_SAMPLE_ID = 1U << 6, 131 PERF_SAMPLE_CPU = 1U << 7, 132 PERF_SAMPLE_PERIOD = 1U << 8, 133 PERF_SAMPLE_STREAM_ID = 1U << 9, 134 PERF_SAMPLE_RAW = 1U << 10, 135 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 136 PERF_SAMPLE_REGS_USER = 1U << 12, 137 PERF_SAMPLE_STACK_USER = 1U << 13, 138 PERF_SAMPLE_WEIGHT = 1U << 14, 139 PERF_SAMPLE_DATA_SRC = 1U << 15, 140 PERF_SAMPLE_IDENTIFIER = 1U << 16, 141 PERF_SAMPLE_TRANSACTION = 1U << 17, 142 PERF_SAMPLE_REGS_INTR = 1U << 18, 143 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 144 PERF_SAMPLE_AUX = 1U << 20, 145 146 PERF_SAMPLE_MAX = 1U << 21, /* non-ABI */ 147 148 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 149}; 150 151/* 152 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 153 * 154 * If the user does not pass priv level information via branch_sample_type, 155 * the kernel uses the event's priv level. Branch and event priv levels do 156 * not have to match. Branch priv level is checked for permissions. 157 * 158 * The branch types can be combined, however BRANCH_ANY covers all types 159 * of branches and therefore it supersedes all the other types. 160 */ 161enum perf_branch_sample_type_shift { 162 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 163 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 164 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 165 166 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 167 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 168 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 169 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 170 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 171 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 172 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 173 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 174 175 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 176 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 177 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 178 179 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 180 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 181 182 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 183 184 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 185}; 186 187enum perf_branch_sample_type { 188 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 189 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 190 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 191 192 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 193 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 194 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 195 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 196 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 197 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 198 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 199 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 200 201 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 202 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 203 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 204 205 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 206 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 207 208 PERF_SAMPLE_BRANCH_TYPE_SAVE = 209 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 210 211 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 212}; 213 214/* 215 * Common flow change classification 216 */ 217enum { 218 PERF_BR_UNKNOWN = 0, /* unknown */ 219 PERF_BR_COND = 1, /* conditional */ 220 PERF_BR_UNCOND = 2, /* unconditional */ 221 PERF_BR_IND = 3, /* indirect */ 222 PERF_BR_CALL = 4, /* function call */ 223 PERF_BR_IND_CALL = 5, /* indirect function call */ 224 PERF_BR_RET = 6, /* function return */ 225 PERF_BR_SYSCALL = 7, /* syscall */ 226 PERF_BR_SYSRET = 8, /* syscall return */ 227 PERF_BR_COND_CALL = 9, /* conditional function call */ 228 PERF_BR_COND_RET = 10, /* conditional function return */ 229 PERF_BR_MAX, 230}; 231 232#define PERF_SAMPLE_BRANCH_PLM_ALL \ 233 (PERF_SAMPLE_BRANCH_USER|\ 234 PERF_SAMPLE_BRANCH_KERNEL|\ 235 PERF_SAMPLE_BRANCH_HV) 236 237/* 238 * Values to determine ABI of the registers dump. 239 */ 240enum perf_sample_regs_abi { 241 PERF_SAMPLE_REGS_ABI_NONE = 0, 242 PERF_SAMPLE_REGS_ABI_32 = 1, 243 PERF_SAMPLE_REGS_ABI_64 = 2, 244}; 245 246/* 247 * Values for the memory transaction event qualifier, mostly for 248 * abort events. Multiple bits can be set. 249 */ 250enum { 251 PERF_TXN_ELISION = (1 << 0), /* From elision */ 252 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 253 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 254 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 255 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 256 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 257 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 258 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 259 260 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 261 262 /* bits 32..63 are reserved for the abort code */ 263 264 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 265 PERF_TXN_ABORT_SHIFT = 32, 266}; 267 268/* 269 * The format of the data returned by read() on a perf event fd, 270 * as specified by attr.read_format: 271 * 272 * struct read_format { 273 * { u64 value; 274 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 275 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 276 * { u64 id; } && PERF_FORMAT_ID 277 * } && !PERF_FORMAT_GROUP 278 * 279 * { u64 nr; 280 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 281 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 282 * { u64 value; 283 * { u64 id; } && PERF_FORMAT_ID 284 * } cntr[nr]; 285 * } && PERF_FORMAT_GROUP 286 * }; 287 */ 288enum perf_event_read_format { 289 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 290 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 291 PERF_FORMAT_ID = 1U << 2, 292 PERF_FORMAT_GROUP = 1U << 3, 293 294 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 295}; 296 297#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 298#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 299#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 300#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 301 /* add: sample_stack_user */ 302#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 303#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 304#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 305 306/* 307 * Hardware event_id to monitor via a performance monitoring event: 308 * 309 * @sample_max_stack: Max number of frame pointers in a callchain, 310 * should be < /proc/sys/kernel/perf_event_max_stack 311 */ 312struct perf_event_attr { 313 314 /* 315 * Major type: hardware/software/tracepoint/etc. 316 */ 317 __u32 type; 318 319 /* 320 * Size of the attr structure, for fwd/bwd compat. 321 */ 322 __u32 size; 323 324 /* 325 * Type specific configuration information. 326 */ 327 __u64 config; 328 329 union { 330 __u64 sample_period; 331 __u64 sample_freq; 332 }; 333 334 __u64 sample_type; 335 __u64 read_format; 336 337 __u64 disabled : 1, /* off by default */ 338 inherit : 1, /* children inherit it */ 339 pinned : 1, /* must always be on PMU */ 340 exclusive : 1, /* only group on PMU */ 341 exclude_user : 1, /* don't count user */ 342 exclude_kernel : 1, /* ditto kernel */ 343 exclude_hv : 1, /* ditto hypervisor */ 344 exclude_idle : 1, /* don't count when idle */ 345 mmap : 1, /* include mmap data */ 346 comm : 1, /* include comm data */ 347 freq : 1, /* use freq, not period */ 348 inherit_stat : 1, /* per task counts */ 349 enable_on_exec : 1, /* next exec enables */ 350 task : 1, /* trace fork/exit */ 351 watermark : 1, /* wakeup_watermark */ 352 /* 353 * precise_ip: 354 * 355 * 0 - SAMPLE_IP can have arbitrary skid 356 * 1 - SAMPLE_IP must have constant skid 357 * 2 - SAMPLE_IP requested to have 0 skid 358 * 3 - SAMPLE_IP must have 0 skid 359 * 360 * See also PERF_RECORD_MISC_EXACT_IP 361 */ 362 precise_ip : 2, /* skid constraint */ 363 mmap_data : 1, /* non-exec mmap data */ 364 sample_id_all : 1, /* sample_type all events */ 365 366 exclude_host : 1, /* don't count in host */ 367 exclude_guest : 1, /* don't count in guest */ 368 369 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 370 exclude_callchain_user : 1, /* exclude user callchains */ 371 mmap2 : 1, /* include mmap with inode data */ 372 comm_exec : 1, /* flag comm events that are due to an exec */ 373 use_clockid : 1, /* use @clockid for time fields */ 374 context_switch : 1, /* context switch data */ 375 write_backward : 1, /* Write ring buffer from end to beginning */ 376 namespaces : 1, /* include namespaces data */ 377 ksymbol : 1, /* include ksymbol events */ 378 bpf_event : 1, /* include bpf events */ 379 aux_output : 1, /* generate AUX records instead of events */ 380 __reserved_1 : 32; 381 382 union { 383 __u32 wakeup_events; /* wakeup every n events */ 384 __u32 wakeup_watermark; /* bytes before wakeup */ 385 }; 386 387 __u32 bp_type; 388 union { 389 __u64 bp_addr; 390 __u64 kprobe_func; /* for perf_kprobe */ 391 __u64 uprobe_path; /* for perf_uprobe */ 392 __u64 config1; /* extension of config */ 393 }; 394 union { 395 __u64 bp_len; 396 __u64 kprobe_addr; /* when kprobe_func == NULL */ 397 __u64 probe_offset; /* for perf_[k,u]probe */ 398 __u64 config2; /* extension of config1 */ 399 }; 400 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 401 402 /* 403 * Defines set of user regs to dump on samples. 404 * See asm/perf_regs.h for details. 405 */ 406 __u64 sample_regs_user; 407 408 /* 409 * Defines size of the user stack to dump on samples. 410 */ 411 __u32 sample_stack_user; 412 413 __s32 clockid; 414 /* 415 * Defines set of regs to dump for each sample 416 * state captured on: 417 * - precise = 0: PMU interrupt 418 * - precise > 0: sampled instruction 419 * 420 * See asm/perf_regs.h for details. 421 */ 422 __u64 sample_regs_intr; 423 424 /* 425 * Wakeup watermark for AUX area 426 */ 427 __u32 aux_watermark; 428 __u16 sample_max_stack; 429 __u16 __reserved_2; 430 __u32 aux_sample_size; 431 __u32 __reserved_3; 432}; 433 434/* 435 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 436 * to query bpf programs attached to the same perf tracepoint 437 * as the given perf event. 438 */ 439struct perf_event_query_bpf { 440 /* 441 * The below ids array length 442 */ 443 __u32 ids_len; 444 /* 445 * Set by the kernel to indicate the number of 446 * available programs 447 */ 448 __u32 prog_cnt; 449 /* 450 * User provided buffer to store program ids 451 */ 452 __u32 ids[0]; 453}; 454 455/* 456 * Ioctls that can be done on a perf event fd: 457 */ 458#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 459#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 460#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 461#define PERF_EVENT_IOC_RESET _IO ('$', 3) 462#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 463#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 464#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 465#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 466#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 467#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 468#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 469#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 470 471enum perf_event_ioc_flags { 472 PERF_IOC_FLAG_GROUP = 1U << 0, 473}; 474 475/* 476 * Structure of the page that can be mapped via mmap 477 */ 478struct perf_event_mmap_page { 479 __u32 version; /* version number of this structure */ 480 __u32 compat_version; /* lowest version this is compat with */ 481 482 /* 483 * Bits needed to read the hw events in user-space. 484 * 485 * u32 seq, time_mult, time_shift, index, width; 486 * u64 count, enabled, running; 487 * u64 cyc, time_offset; 488 * s64 pmc = 0; 489 * 490 * do { 491 * seq = pc->lock; 492 * barrier() 493 * 494 * enabled = pc->time_enabled; 495 * running = pc->time_running; 496 * 497 * if (pc->cap_usr_time && enabled != running) { 498 * cyc = rdtsc(); 499 * time_offset = pc->time_offset; 500 * time_mult = pc->time_mult; 501 * time_shift = pc->time_shift; 502 * } 503 * 504 * index = pc->index; 505 * count = pc->offset; 506 * if (pc->cap_user_rdpmc && index) { 507 * width = pc->pmc_width; 508 * pmc = rdpmc(index - 1); 509 * } 510 * 511 * barrier(); 512 * } while (pc->lock != seq); 513 * 514 * NOTE: for obvious reason this only works on self-monitoring 515 * processes. 516 */ 517 __u32 lock; /* seqlock for synchronization */ 518 __u32 index; /* hardware event identifier */ 519 __s64 offset; /* add to hardware event value */ 520 __u64 time_enabled; /* time event active */ 521 __u64 time_running; /* time event on cpu */ 522 union { 523 __u64 capabilities; 524 struct { 525 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 526 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 527 528 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 529 cap_user_time : 1, /* The time_* fields are used */ 530 cap_user_time_zero : 1, /* The time_zero field is used */ 531 cap_____res : 59; 532 }; 533 }; 534 535 /* 536 * If cap_user_rdpmc this field provides the bit-width of the value 537 * read using the rdpmc() or equivalent instruction. This can be used 538 * to sign extend the result like: 539 * 540 * pmc <<= 64 - width; 541 * pmc >>= 64 - width; // signed shift right 542 * count += pmc; 543 */ 544 __u16 pmc_width; 545 546 /* 547 * If cap_usr_time the below fields can be used to compute the time 548 * delta since time_enabled (in ns) using rdtsc or similar. 549 * 550 * u64 quot, rem; 551 * u64 delta; 552 * 553 * quot = (cyc >> time_shift); 554 * rem = cyc & (((u64)1 << time_shift) - 1); 555 * delta = time_offset + quot * time_mult + 556 * ((rem * time_mult) >> time_shift); 557 * 558 * Where time_offset,time_mult,time_shift and cyc are read in the 559 * seqcount loop described above. This delta can then be added to 560 * enabled and possible running (if index), improving the scaling: 561 * 562 * enabled += delta; 563 * if (index) 564 * running += delta; 565 * 566 * quot = count / running; 567 * rem = count % running; 568 * count = quot * enabled + (rem * enabled) / running; 569 */ 570 __u16 time_shift; 571 __u32 time_mult; 572 __u64 time_offset; 573 /* 574 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 575 * from sample timestamps. 576 * 577 * time = timestamp - time_zero; 578 * quot = time / time_mult; 579 * rem = time % time_mult; 580 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 581 * 582 * And vice versa: 583 * 584 * quot = cyc >> time_shift; 585 * rem = cyc & (((u64)1 << time_shift) - 1); 586 * timestamp = time_zero + quot * time_mult + 587 * ((rem * time_mult) >> time_shift); 588 */ 589 __u64 time_zero; 590 __u32 size; /* Header size up to __reserved[] fields. */ 591 592 /* 593 * Hole for extension of the self monitor capabilities 594 */ 595 596 __u8 __reserved[118*8+4]; /* align to 1k. */ 597 598 /* 599 * Control data for the mmap() data buffer. 600 * 601 * User-space reading the @data_head value should issue an smp_rmb(), 602 * after reading this value. 603 * 604 * When the mapping is PROT_WRITE the @data_tail value should be 605 * written by userspace to reflect the last read data, after issueing 606 * an smp_mb() to separate the data read from the ->data_tail store. 607 * In this case the kernel will not over-write unread data. 608 * 609 * See perf_output_put_handle() for the data ordering. 610 * 611 * data_{offset,size} indicate the location and size of the perf record 612 * buffer within the mmapped area. 613 */ 614 __u64 data_head; /* head in the data section */ 615 __u64 data_tail; /* user-space written tail */ 616 __u64 data_offset; /* where the buffer starts */ 617 __u64 data_size; /* data buffer size */ 618 619 /* 620 * AUX area is defined by aux_{offset,size} fields that should be set 621 * by the userspace, so that 622 * 623 * aux_offset >= data_offset + data_size 624 * 625 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 626 * 627 * Ring buffer pointers aux_{head,tail} have the same semantics as 628 * data_{head,tail} and same ordering rules apply. 629 */ 630 __u64 aux_head; 631 __u64 aux_tail; 632 __u64 aux_offset; 633 __u64 aux_size; 634}; 635 636#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 637#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 638#define PERF_RECORD_MISC_KERNEL (1 << 0) 639#define PERF_RECORD_MISC_USER (2 << 0) 640#define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 641#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 642#define PERF_RECORD_MISC_GUEST_USER (5 << 0) 643 644/* 645 * Indicates that /proc/PID/maps parsing are truncated by time out. 646 */ 647#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 648/* 649 * Following PERF_RECORD_MISC_* are used on different 650 * events, so can reuse the same bit position: 651 * 652 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 653 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 654 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 655 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 656 */ 657#define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 658#define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 659#define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 660#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 661/* 662 * These PERF_RECORD_MISC_* flags below are safely reused 663 * for the following events: 664 * 665 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 666 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 667 * 668 * 669 * PERF_RECORD_MISC_EXACT_IP: 670 * Indicates that the content of PERF_SAMPLE_IP points to 671 * the actual instruction that triggered the event. See also 672 * perf_event_attr::precise_ip. 673 * 674 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 675 * Indicates that thread was preempted in TASK_RUNNING state. 676 */ 677#define PERF_RECORD_MISC_EXACT_IP (1 << 14) 678#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 679/* 680 * Reserve the last bit to indicate some extended misc field 681 */ 682#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 683 684struct perf_event_header { 685 __u32 type; 686 __u16 misc; 687 __u16 size; 688}; 689 690struct perf_ns_link_info { 691 __u64 dev; 692 __u64 ino; 693}; 694 695enum { 696 NET_NS_INDEX = 0, 697 UTS_NS_INDEX = 1, 698 IPC_NS_INDEX = 2, 699 PID_NS_INDEX = 3, 700 USER_NS_INDEX = 4, 701 MNT_NS_INDEX = 5, 702 CGROUP_NS_INDEX = 6, 703 704 NR_NAMESPACES, /* number of available namespaces */ 705}; 706 707enum perf_event_type { 708 709 /* 710 * If perf_event_attr.sample_id_all is set then all event types will 711 * have the sample_type selected fields related to where/when 712 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 713 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 714 * just after the perf_event_header and the fields already present for 715 * the existing fields, i.e. at the end of the payload. That way a newer 716 * perf.data file will be supported by older perf tools, with these new 717 * optional fields being ignored. 718 * 719 * struct sample_id { 720 * { u32 pid, tid; } && PERF_SAMPLE_TID 721 * { u64 time; } && PERF_SAMPLE_TIME 722 * { u64 id; } && PERF_SAMPLE_ID 723 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 724 * { u32 cpu, res; } && PERF_SAMPLE_CPU 725 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 726 * } && perf_event_attr::sample_id_all 727 * 728 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 729 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 730 * relative to header.size. 731 */ 732 733 /* 734 * The MMAP events record the PROT_EXEC mappings so that we can 735 * correlate userspace IPs to code. They have the following structure: 736 * 737 * struct { 738 * struct perf_event_header header; 739 * 740 * u32 pid, tid; 741 * u64 addr; 742 * u64 len; 743 * u64 pgoff; 744 * char filename[]; 745 * struct sample_id sample_id; 746 * }; 747 */ 748 PERF_RECORD_MMAP = 1, 749 750 /* 751 * struct { 752 * struct perf_event_header header; 753 * u64 id; 754 * u64 lost; 755 * struct sample_id sample_id; 756 * }; 757 */ 758 PERF_RECORD_LOST = 2, 759 760 /* 761 * struct { 762 * struct perf_event_header header; 763 * 764 * u32 pid, tid; 765 * char comm[]; 766 * struct sample_id sample_id; 767 * }; 768 */ 769 PERF_RECORD_COMM = 3, 770 771 /* 772 * struct { 773 * struct perf_event_header header; 774 * u32 pid, ppid; 775 * u32 tid, ptid; 776 * u64 time; 777 * struct sample_id sample_id; 778 * }; 779 */ 780 PERF_RECORD_EXIT = 4, 781 782 /* 783 * struct { 784 * struct perf_event_header header; 785 * u64 time; 786 * u64 id; 787 * u64 stream_id; 788 * struct sample_id sample_id; 789 * }; 790 */ 791 PERF_RECORD_THROTTLE = 5, 792 PERF_RECORD_UNTHROTTLE = 6, 793 794 /* 795 * struct { 796 * struct perf_event_header header; 797 * u32 pid, ppid; 798 * u32 tid, ptid; 799 * u64 time; 800 * struct sample_id sample_id; 801 * }; 802 */ 803 PERF_RECORD_FORK = 7, 804 805 /* 806 * struct { 807 * struct perf_event_header header; 808 * u32 pid, tid; 809 * 810 * struct read_format values; 811 * struct sample_id sample_id; 812 * }; 813 */ 814 PERF_RECORD_READ = 8, 815 816 /* 817 * struct { 818 * struct perf_event_header header; 819 * 820 * # 821 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 822 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 823 * # is fixed relative to header. 824 * # 825 * 826 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 827 * { u64 ip; } && PERF_SAMPLE_IP 828 * { u32 pid, tid; } && PERF_SAMPLE_TID 829 * { u64 time; } && PERF_SAMPLE_TIME 830 * { u64 addr; } && PERF_SAMPLE_ADDR 831 * { u64 id; } && PERF_SAMPLE_ID 832 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 833 * { u32 cpu, res; } && PERF_SAMPLE_CPU 834 * { u64 period; } && PERF_SAMPLE_PERIOD 835 * 836 * { struct read_format values; } && PERF_SAMPLE_READ 837 * 838 * { u64 nr, 839 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 840 * 841 * # 842 * # The RAW record below is opaque data wrt the ABI 843 * # 844 * # That is, the ABI doesn't make any promises wrt to 845 * # the stability of its content, it may vary depending 846 * # on event, hardware, kernel version and phase of 847 * # the moon. 848 * # 849 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 850 * # 851 * 852 * { u32 size; 853 * char data[size];}&& PERF_SAMPLE_RAW 854 * 855 * { u64 nr; 856 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 857 * 858 * { u64 abi; # enum perf_sample_regs_abi 859 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 860 * 861 * { u64 size; 862 * char data[size]; 863 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 864 * 865 * { u64 weight; } && PERF_SAMPLE_WEIGHT 866 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 867 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 868 * { u64 abi; # enum perf_sample_regs_abi 869 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 870 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 871 * { u64 size; 872 * char data[size]; } && PERF_SAMPLE_AUX 873 * }; 874 */ 875 PERF_RECORD_SAMPLE = 9, 876 877 /* 878 * The MMAP2 records are an augmented version of MMAP, they add 879 * maj, min, ino numbers to be used to uniquely identify each mapping 880 * 881 * struct { 882 * struct perf_event_header header; 883 * 884 * u32 pid, tid; 885 * u64 addr; 886 * u64 len; 887 * u64 pgoff; 888 * u32 maj; 889 * u32 min; 890 * u64 ino; 891 * u64 ino_generation; 892 * u32 prot, flags; 893 * char filename[]; 894 * struct sample_id sample_id; 895 * }; 896 */ 897 PERF_RECORD_MMAP2 = 10, 898 899 /* 900 * Records that new data landed in the AUX buffer part. 901 * 902 * struct { 903 * struct perf_event_header header; 904 * 905 * u64 aux_offset; 906 * u64 aux_size; 907 * u64 flags; 908 * struct sample_id sample_id; 909 * }; 910 */ 911 PERF_RECORD_AUX = 11, 912 913 /* 914 * Indicates that instruction trace has started 915 * 916 * struct { 917 * struct perf_event_header header; 918 * u32 pid; 919 * u32 tid; 920 * struct sample_id sample_id; 921 * }; 922 */ 923 PERF_RECORD_ITRACE_START = 12, 924 925 /* 926 * Records the dropped/lost sample number. 927 * 928 * struct { 929 * struct perf_event_header header; 930 * 931 * u64 lost; 932 * struct sample_id sample_id; 933 * }; 934 */ 935 PERF_RECORD_LOST_SAMPLES = 13, 936 937 /* 938 * Records a context switch in or out (flagged by 939 * PERF_RECORD_MISC_SWITCH_OUT). See also 940 * PERF_RECORD_SWITCH_CPU_WIDE. 941 * 942 * struct { 943 * struct perf_event_header header; 944 * struct sample_id sample_id; 945 * }; 946 */ 947 PERF_RECORD_SWITCH = 14, 948 949 /* 950 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 951 * next_prev_tid that are the next (switching out) or previous 952 * (switching in) pid/tid. 953 * 954 * struct { 955 * struct perf_event_header header; 956 * u32 next_prev_pid; 957 * u32 next_prev_tid; 958 * struct sample_id sample_id; 959 * }; 960 */ 961 PERF_RECORD_SWITCH_CPU_WIDE = 15, 962 963 /* 964 * struct { 965 * struct perf_event_header header; 966 * u32 pid; 967 * u32 tid; 968 * u64 nr_namespaces; 969 * { u64 dev, inode; } [nr_namespaces]; 970 * struct sample_id sample_id; 971 * }; 972 */ 973 PERF_RECORD_NAMESPACES = 16, 974 975 /* 976 * Record ksymbol register/unregister events: 977 * 978 * struct { 979 * struct perf_event_header header; 980 * u64 addr; 981 * u32 len; 982 * u16 ksym_type; 983 * u16 flags; 984 * char name[]; 985 * struct sample_id sample_id; 986 * }; 987 */ 988 PERF_RECORD_KSYMBOL = 17, 989 990 /* 991 * Record bpf events: 992 * enum perf_bpf_event_type { 993 * PERF_BPF_EVENT_UNKNOWN = 0, 994 * PERF_BPF_EVENT_PROG_LOAD = 1, 995 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 996 * }; 997 * 998 * struct { 999 * struct perf_event_header header; 1000 * u16 type;
1001 * u16 flags; 1002 * u32 id; 1003 * u8 tag[BPF_TAG_SIZE]; 1004 * struct sample_id sample_id; 1005 * }; 1006 */ 1007 PERF_RECORD_BPF_EVENT = 18, 1008 1009 PERF_RECORD_MAX, /* non-ABI */ 1010}; 1011 1012enum perf_record_ksymbol_type { 1013 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1014 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1015 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1016}; 1017 1018#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1019 1020enum perf_bpf_event_type { 1021 PERF_BPF_EVENT_UNKNOWN = 0, 1022 PERF_BPF_EVENT_PROG_LOAD = 1, 1023 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1024 PERF_BPF_EVENT_MAX, /* non-ABI */ 1025}; 1026 1027#define PERF_MAX_STACK_DEPTH 127 1028#define PERF_MAX_CONTEXTS_PER_STACK 8 1029 1030enum perf_callchain_context { 1031 PERF_CONTEXT_HV = (__u64)-32, 1032 PERF_CONTEXT_KERNEL = (__u64)-128, 1033 PERF_CONTEXT_USER = (__u64)-512, 1034 1035 PERF_CONTEXT_GUEST = (__u64)-2048, 1036 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1037 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1038 1039 PERF_CONTEXT_MAX = (__u64)-4095, 1040}; 1041 1042/** 1043 * PERF_RECORD_AUX::flags bits 1044 */ 1045#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1046#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1047#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1048#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1049 1050#define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1051#define PERF_FLAG_FD_OUTPUT (1UL << 1) 1052#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1053#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1054 1055#if defined(__LITTLE_ENDIAN_BITFIELD) 1056union perf_mem_data_src { 1057 __u64 val; 1058 struct { 1059 __u64 mem_op:5, /* type of opcode */ 1060 mem_lvl:14, /* memory hierarchy level */ 1061 mem_snoop:5, /* snoop mode */ 1062 mem_lock:2, /* lock instr */ 1063 mem_dtlb:7, /* tlb access */ 1064 mem_lvl_num:4, /* memory hierarchy level number */ 1065 mem_remote:1, /* remote */ 1066 mem_snoopx:2, /* snoop mode, ext */ 1067 mem_rsvd:24; 1068 }; 1069}; 1070#elif defined(__BIG_ENDIAN_BITFIELD) 1071union perf_mem_data_src { 1072 __u64 val; 1073 struct { 1074 __u64 mem_rsvd:24, 1075 mem_snoopx:2, /* snoop mode, ext */ 1076 mem_remote:1, /* remote */ 1077 mem_lvl_num:4, /* memory hierarchy level number */ 1078 mem_dtlb:7, /* tlb access */ 1079 mem_lock:2, /* lock instr */ 1080 mem_snoop:5, /* snoop mode */ 1081 mem_lvl:14, /* memory hierarchy level */ 1082 mem_op:5; /* type of opcode */ 1083 }; 1084}; 1085#else 1086#error "Unknown endianness" 1087#endif 1088 1089/* type of opcode (load/store/prefetch,code) */ 1090#define PERF_MEM_OP_NA 0x01 /* not available */ 1091#define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1092#define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1093#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1094#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1095#define PERF_MEM_OP_SHIFT 0 1096 1097/* memory hierarchy (memory level, hit or miss) */ 1098#define PERF_MEM_LVL_NA 0x01 /* not available */ 1099#define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1100#define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1101#define PERF_MEM_LVL_L1 0x08 /* L1 */ 1102#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1103#define PERF_MEM_LVL_L2 0x20 /* L2 */ 1104#define PERF_MEM_LVL_L3 0x40 /* L3 */ 1105#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1106#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1107#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1108#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1109#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1110#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1111#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1112#define PERF_MEM_LVL_SHIFT 5 1113 1114#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1115#define PERF_MEM_REMOTE_SHIFT 37 1116 1117#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1118#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1119#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1120#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1121/* 5-0xa available */ 1122#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1123#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1124#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1125#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1126#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1127 1128#define PERF_MEM_LVLNUM_SHIFT 33 1129 1130/* snoop mode */ 1131#define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1132#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1133#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1134#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1135#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1136#define PERF_MEM_SNOOP_SHIFT 19 1137 1138#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1139/* 1 free */ 1140#define PERF_MEM_SNOOPX_SHIFT 37 1141 1142/* locked instruction */ 1143#define PERF_MEM_LOCK_NA 0x01 /* not available */ 1144#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1145#define PERF_MEM_LOCK_SHIFT 24 1146 1147/* TLB access */ 1148#define PERF_MEM_TLB_NA 0x01 /* not available */ 1149#define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1150#define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1151#define PERF_MEM_TLB_L1 0x08 /* L1 */ 1152#define PERF_MEM_TLB_L2 0x10 /* L2 */ 1153#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1154#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1155#define PERF_MEM_TLB_SHIFT 26 1156 1157#define PERF_MEM_S(a, s) \ 1158 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1159 1160/* 1161 * single taken branch record layout: 1162 * 1163 * from: source instruction (may not always be a branch insn) 1164 * to: branch target 1165 * mispred: branch target was mispredicted 1166 * predicted: branch target was predicted 1167 * 1168 * support for mispred, predicted is optional. In case it 1169 * is not supported mispred = predicted = 0. 1170 * 1171 * in_tx: running in a hardware transaction 1172 * abort: aborting a hardware transaction 1173 * cycles: cycles from last branch (or 0 if not supported) 1174 * type: branch type 1175 */ 1176struct perf_branch_entry { 1177 __u64 from; 1178 __u64 to; 1179 __u64 mispred:1, /* target mispredicted */ 1180 predicted:1,/* target predicted */ 1181 in_tx:1, /* in transaction */ 1182 abort:1, /* transaction abort */ 1183 cycles:16, /* cycle count to last branch */ 1184 type:4, /* branch type */ 1185 reserved:40; 1186}; 1187 1188#endif /* _UAPI_LINUX_PERF_EVENT_H */ 1189