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8
9#include <linux/cpu.h>
10#include <linux/kvm.h>
11#include <linux/kvm_host.h>
12#include <linux/interrupt.h>
13#include <linux/list.h>
14#include <linux/uaccess.h>
15#include <linux/list_sort.h>
16
17#include <linux/irqchip/arm-gic-v3.h>
18
19#include <asm/kvm_emulate.h>
20#include <asm/kvm_arm.h>
21#include <asm/kvm_mmu.h>
22
23#include "vgic.h"
24#include "vgic-mmio.h"
25
26static int vgic_its_save_tables_v0(struct vgic_its *its);
27static int vgic_its_restore_tables_v0(struct vgic_its *its);
28static int vgic_its_commit_v0(struct vgic_its *its);
29static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
30 struct kvm_vcpu *filter_vcpu, bool needs_inv);
31
32
33
34
35
36
37
38
39static struct vgic_irq *vgic_add_lpi(struct kvm *kvm, u32 intid,
40 struct kvm_vcpu *vcpu)
41{
42 struct vgic_dist *dist = &kvm->arch.vgic;
43 struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
44 unsigned long flags;
45 int ret;
46
47
48 if (irq)
49 return irq;
50
51 irq = kzalloc(sizeof(struct vgic_irq), GFP_KERNEL);
52 if (!irq)
53 return ERR_PTR(-ENOMEM);
54
55 INIT_LIST_HEAD(&irq->lpi_list);
56 INIT_LIST_HEAD(&irq->ap_list);
57 raw_spin_lock_init(&irq->irq_lock);
58
59 irq->config = VGIC_CONFIG_EDGE;
60 kref_init(&irq->refcount);
61 irq->intid = intid;
62 irq->target_vcpu = vcpu;
63 irq->group = 1;
64
65 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
66
67
68
69
70
71 list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list) {
72 if (oldirq->intid != intid)
73 continue;
74
75
76 kfree(irq);
77 irq = oldirq;
78
79
80
81
82
83
84 vgic_get_irq_kref(irq);
85
86 goto out_unlock;
87 }
88
89 list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
90 dist->lpi_list_count++;
91
92out_unlock:
93 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
94
95
96
97
98
99
100 ret = update_lpi_config(kvm, irq, NULL, false);
101 if (ret)
102 return ERR_PTR(ret);
103
104 ret = vgic_v3_lpi_sync_pending_status(kvm, irq);
105 if (ret)
106 return ERR_PTR(ret);
107
108 return irq;
109}
110
111struct its_device {
112 struct list_head dev_list;
113
114
115 struct list_head itt_head;
116 u32 num_eventid_bits;
117 gpa_t itt_addr;
118 u32 device_id;
119};
120
121#define COLLECTION_NOT_MAPPED ((u32)~0)
122
123struct its_collection {
124 struct list_head coll_list;
125
126 u32 collection_id;
127 u32 target_addr;
128};
129
130#define its_is_collection_mapped(coll) ((coll) && \
131 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
132
133struct its_ite {
134 struct list_head ite_list;
135
136 struct vgic_irq *irq;
137 struct its_collection *collection;
138 u32 event_id;
139};
140
141struct vgic_translation_cache_entry {
142 struct list_head entry;
143 phys_addr_t db;
144 u32 devid;
145 u32 eventid;
146 struct vgic_irq *irq;
147};
148
149
150
151
152
153
154
155
156
157
158
159
160struct vgic_its_abi {
161 int cte_esz;
162 int dte_esz;
163 int ite_esz;
164 int (*save_tables)(struct vgic_its *its);
165 int (*restore_tables)(struct vgic_its *its);
166 int (*commit)(struct vgic_its *its);
167};
168
169#define ABI_0_ESZ 8
170#define ESZ_MAX ABI_0_ESZ
171
172static const struct vgic_its_abi its_table_abi_versions[] = {
173 [0] = {
174 .cte_esz = ABI_0_ESZ,
175 .dte_esz = ABI_0_ESZ,
176 .ite_esz = ABI_0_ESZ,
177 .save_tables = vgic_its_save_tables_v0,
178 .restore_tables = vgic_its_restore_tables_v0,
179 .commit = vgic_its_commit_v0,
180 },
181};
182
183#define NR_ITS_ABIS ARRAY_SIZE(its_table_abi_versions)
184
185inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
186{
187 return &its_table_abi_versions[its->abi_rev];
188}
189
190static int vgic_its_set_abi(struct vgic_its *its, u32 rev)
191{
192 const struct vgic_its_abi *abi;
193
194 its->abi_rev = rev;
195 abi = vgic_its_get_abi(its);
196 return abi->commit(its);
197}
198
199
200
201
202
203static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
204{
205 struct its_device *device;
206
207 list_for_each_entry(device, &its->device_list, dev_list)
208 if (device_id == device->device_id)
209 return device;
210
211 return NULL;
212}
213
214
215
216
217
218
219static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
220 u32 event_id)
221{
222 struct its_device *device;
223 struct its_ite *ite;
224
225 device = find_its_device(its, device_id);
226 if (device == NULL)
227 return NULL;
228
229 list_for_each_entry(ite, &device->itt_head, ite_list)
230 if (ite->event_id == event_id)
231 return ite;
232
233 return NULL;
234}
235
236
237#define for_each_lpi_its(dev, ite, its) \
238 list_for_each_entry(dev, &(its)->device_list, dev_list) \
239 list_for_each_entry(ite, &(dev)->itt_head, ite_list)
240
241#define GIC_LPI_OFFSET 8192
242
243#define VITS_TYPER_IDBITS 16
244#define VITS_TYPER_DEVBITS 16
245#define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1)
246#define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1)
247
248
249
250
251
252static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
253{
254 struct its_collection *collection;
255
256 list_for_each_entry(collection, &its->collection_list, coll_list) {
257 if (coll_id == collection->collection_id)
258 return collection;
259 }
260
261 return NULL;
262}
263
264#define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED)
265#define LPI_PROP_PRIORITY(p) ((p) & 0xfc)
266
267
268
269
270
271
272
273static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
274 struct kvm_vcpu *filter_vcpu, bool needs_inv)
275{
276 u64 propbase = GICR_PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
277 u8 prop;
278 int ret;
279 unsigned long flags;
280
281 ret = kvm_read_guest_lock(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
282 &prop, 1);
283
284 if (ret)
285 return ret;
286
287 raw_spin_lock_irqsave(&irq->irq_lock, flags);
288
289 if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
290 irq->priority = LPI_PROP_PRIORITY(prop);
291 irq->enabled = LPI_PROP_ENABLE_BIT(prop);
292
293 if (!irq->hw) {
294 vgic_queue_irq_unlock(kvm, irq, flags);
295 return 0;
296 }
297 }
298
299 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
300
301 if (irq->hw)
302 return its_prop_update_vlpi(irq->host_irq, prop, needs_inv);
303
304 return 0;
305}
306
307
308
309
310
311
312int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr)
313{
314 struct vgic_dist *dist = &kvm->arch.vgic;
315 struct vgic_irq *irq;
316 unsigned long flags;
317 u32 *intids;
318 int irq_count, i = 0;
319
320
321
322
323
324
325
326
327 irq_count = READ_ONCE(dist->lpi_list_count);
328 intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
329 if (!intids)
330 return -ENOMEM;
331
332 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
333 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
334 if (i == irq_count)
335 break;
336
337 if (vcpu && irq->target_vcpu != vcpu)
338 continue;
339 intids[i++] = irq->intid;
340 }
341 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
342
343 *intid_ptr = intids;
344 return i;
345}
346
347static int update_affinity(struct vgic_irq *irq, struct kvm_vcpu *vcpu)
348{
349 int ret = 0;
350 unsigned long flags;
351
352 raw_spin_lock_irqsave(&irq->irq_lock, flags);
353 irq->target_vcpu = vcpu;
354 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
355
356 if (irq->hw) {
357 struct its_vlpi_map map;
358
359 ret = its_get_vlpi(irq->host_irq, &map);
360 if (ret)
361 return ret;
362
363 if (map.vpe)
364 atomic_dec(&map.vpe->vlpi_count);
365 map.vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
366 atomic_inc(&map.vpe->vlpi_count);
367
368 ret = its_map_vlpi(irq->host_irq, &map);
369 }
370
371 return ret;
372}
373
374
375
376
377
378
379
380static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
381{
382 struct kvm_vcpu *vcpu;
383
384 if (!its_is_collection_mapped(ite->collection))
385 return;
386
387 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
388 update_affinity(ite->irq, vcpu);
389}
390
391
392
393
394
395static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
396 struct its_collection *coll)
397{
398 struct its_device *device;
399 struct its_ite *ite;
400
401 for_each_lpi_its(device, ite, its) {
402 if (!ite->collection || coll != ite->collection)
403 continue;
404
405 update_affinity_ite(kvm, ite);
406 }
407}
408
409static u32 max_lpis_propbaser(u64 propbaser)
410{
411 int nr_idbits = (propbaser & 0x1f) + 1;
412
413 return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
414}
415
416
417
418
419
420
421static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
422{
423 gpa_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
424 struct vgic_irq *irq;
425 int last_byte_offset = -1;
426 int ret = 0;
427 u32 *intids;
428 int nr_irqs, i;
429 unsigned long flags;
430 u8 pendmask;
431
432 nr_irqs = vgic_copy_lpi_list(vcpu->kvm, vcpu, &intids);
433 if (nr_irqs < 0)
434 return nr_irqs;
435
436 for (i = 0; i < nr_irqs; i++) {
437 int byte_offset, bit_nr;
438
439 byte_offset = intids[i] / BITS_PER_BYTE;
440 bit_nr = intids[i] % BITS_PER_BYTE;
441
442
443
444
445
446 if (byte_offset != last_byte_offset) {
447 ret = kvm_read_guest_lock(vcpu->kvm,
448 pendbase + byte_offset,
449 &pendmask, 1);
450 if (ret) {
451 kfree(intids);
452 return ret;
453 }
454 last_byte_offset = byte_offset;
455 }
456
457 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
458 raw_spin_lock_irqsave(&irq->irq_lock, flags);
459 irq->pending_latch = pendmask & (1U << bit_nr);
460 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
461 vgic_put_irq(vcpu->kvm, irq);
462 }
463
464 kfree(intids);
465
466 return ret;
467}
468
469static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
470 struct vgic_its *its,
471 gpa_t addr, unsigned int len)
472{
473 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
474 u64 reg = GITS_TYPER_PLPIS;
475
476
477
478
479
480
481
482
483
484 reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
485 reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
486 reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
487
488 return extract_bytes(reg, addr & 7, len);
489}
490
491static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
492 struct vgic_its *its,
493 gpa_t addr, unsigned int len)
494{
495 u32 val;
496
497 val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
498 val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
499 return val;
500}
501
502static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
503 struct vgic_its *its,
504 gpa_t addr, unsigned int len,
505 unsigned long val)
506{
507 u32 rev = GITS_IIDR_REV(val);
508
509 if (rev >= NR_ITS_ABIS)
510 return -EINVAL;
511 return vgic_its_set_abi(its, rev);
512}
513
514static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
515 struct vgic_its *its,
516 gpa_t addr, unsigned int len)
517{
518 switch (addr & 0xffff) {
519 case GITS_PIDR0:
520 return 0x92;
521 case GITS_PIDR1:
522 return 0xb4;
523 case GITS_PIDR2:
524 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
525 case GITS_PIDR4:
526 return 0x40;
527
528 case GITS_CIDR0:
529 return 0x0d;
530 case GITS_CIDR1:
531 return 0xf0;
532 case GITS_CIDR2:
533 return 0x05;
534 case GITS_CIDR3:
535 return 0xb1;
536 }
537
538 return 0;
539}
540
541static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist,
542 phys_addr_t db,
543 u32 devid, u32 eventid)
544{
545 struct vgic_translation_cache_entry *cte;
546
547 list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
548
549
550
551
552 if (!cte->irq)
553 break;
554
555 if (cte->db != db || cte->devid != devid ||
556 cte->eventid != eventid)
557 continue;
558
559
560
561
562
563 if (!list_is_first(&cte->entry, &dist->lpi_translation_cache))
564 list_move(&cte->entry, &dist->lpi_translation_cache);
565
566 return cte->irq;
567 }
568
569 return NULL;
570}
571
572static struct vgic_irq *vgic_its_check_cache(struct kvm *kvm, phys_addr_t db,
573 u32 devid, u32 eventid)
574{
575 struct vgic_dist *dist = &kvm->arch.vgic;
576 struct vgic_irq *irq;
577 unsigned long flags;
578
579 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
580 irq = __vgic_its_check_cache(dist, db, devid, eventid);
581 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
582
583 return irq;
584}
585
586static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its,
587 u32 devid, u32 eventid,
588 struct vgic_irq *irq)
589{
590 struct vgic_dist *dist = &kvm->arch.vgic;
591 struct vgic_translation_cache_entry *cte;
592 unsigned long flags;
593 phys_addr_t db;
594
595
596 if (irq->hw)
597 return;
598
599 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
600
601 if (unlikely(list_empty(&dist->lpi_translation_cache)))
602 goto out;
603
604
605
606
607
608
609 db = its->vgic_its_base + GITS_TRANSLATER;
610 if (__vgic_its_check_cache(dist, db, devid, eventid))
611 goto out;
612
613
614 cte = list_last_entry(&dist->lpi_translation_cache,
615 typeof(*cte), entry);
616
617
618
619
620
621
622 if (cte->irq)
623 __vgic_put_lpi_locked(kvm, cte->irq);
624
625 vgic_get_irq_kref(irq);
626
627 cte->db = db;
628 cte->devid = devid;
629 cte->eventid = eventid;
630 cte->irq = irq;
631
632
633 list_move(&cte->entry, &dist->lpi_translation_cache);
634
635out:
636 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
637}
638
639void vgic_its_invalidate_cache(struct kvm *kvm)
640{
641 struct vgic_dist *dist = &kvm->arch.vgic;
642 struct vgic_translation_cache_entry *cte;
643 unsigned long flags;
644
645 raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
646
647 list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
648
649
650
651
652 if (!cte->irq)
653 break;
654
655 __vgic_put_lpi_locked(kvm, cte->irq);
656 cte->irq = NULL;
657 }
658
659 raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
660}
661
662int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
663 u32 devid, u32 eventid, struct vgic_irq **irq)
664{
665 struct kvm_vcpu *vcpu;
666 struct its_ite *ite;
667
668 if (!its->enabled)
669 return -EBUSY;
670
671 ite = find_ite(its, devid, eventid);
672 if (!ite || !its_is_collection_mapped(ite->collection))
673 return E_ITS_INT_UNMAPPED_INTERRUPT;
674
675 vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
676 if (!vcpu)
677 return E_ITS_INT_UNMAPPED_INTERRUPT;
678
679 if (!vcpu->arch.vgic_cpu.lpis_enabled)
680 return -EBUSY;
681
682 vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq);
683
684 *irq = ite->irq;
685 return 0;
686}
687
688struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi)
689{
690 u64 address;
691 struct kvm_io_device *kvm_io_dev;
692 struct vgic_io_device *iodev;
693
694 if (!vgic_has_its(kvm))
695 return ERR_PTR(-ENODEV);
696
697 if (!(msi->flags & KVM_MSI_VALID_DEVID))
698 return ERR_PTR(-EINVAL);
699
700 address = (u64)msi->address_hi << 32 | msi->address_lo;
701
702 kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
703 if (!kvm_io_dev)
704 return ERR_PTR(-EINVAL);
705
706 if (kvm_io_dev->ops != &kvm_io_gic_ops)
707 return ERR_PTR(-EINVAL);
708
709 iodev = container_of(kvm_io_dev, struct vgic_io_device, dev);
710 if (iodev->iodev_type != IODEV_ITS)
711 return ERR_PTR(-EINVAL);
712
713 return iodev->its;
714}
715
716
717
718
719
720
721
722
723static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
724 u32 devid, u32 eventid)
725{
726 struct vgic_irq *irq = NULL;
727 unsigned long flags;
728 int err;
729
730 err = vgic_its_resolve_lpi(kvm, its, devid, eventid, &irq);
731 if (err)
732 return err;
733
734 if (irq->hw)
735 return irq_set_irqchip_state(irq->host_irq,
736 IRQCHIP_STATE_PENDING, true);
737
738 raw_spin_lock_irqsave(&irq->irq_lock, flags);
739 irq->pending_latch = true;
740 vgic_queue_irq_unlock(kvm, irq, flags);
741
742 return 0;
743}
744
745int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi)
746{
747 struct vgic_irq *irq;
748 unsigned long flags;
749 phys_addr_t db;
750
751 db = (u64)msi->address_hi << 32 | msi->address_lo;
752 irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data);
753
754 if (!irq)
755 return -1;
756
757 raw_spin_lock_irqsave(&irq->irq_lock, flags);
758 irq->pending_latch = true;
759 vgic_queue_irq_unlock(kvm, irq, flags);
760
761 return 0;
762}
763
764
765
766
767
768
769
770int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
771{
772 struct vgic_its *its;
773 int ret;
774
775 if (!vgic_its_inject_cached_translation(kvm, msi))
776 return 1;
777
778 its = vgic_msi_to_its(kvm, msi);
779 if (IS_ERR(its))
780 return PTR_ERR(its);
781
782 mutex_lock(&its->its_lock);
783 ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data);
784 mutex_unlock(&its->its_lock);
785
786 if (ret < 0)
787 return ret;
788
789
790
791
792
793
794 if (ret)
795 return 0;
796 else
797 return 1;
798}
799
800
801static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
802{
803 list_del(&ite->ite_list);
804
805
806 if (ite->irq) {
807 if (ite->irq->hw)
808 WARN_ON(its_unmap_vlpi(ite->irq->host_irq));
809
810 vgic_put_irq(kvm, ite->irq);
811 }
812
813 kfree(ite);
814}
815
816static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
817{
818 return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1);
819}
820
821#define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
822#define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
823#define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
824#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
825#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
826#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
827#define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8)
828#define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
829#define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
830
831
832
833
834
835static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
836 u64 *its_cmd)
837{
838 u32 device_id = its_cmd_get_deviceid(its_cmd);
839 u32 event_id = its_cmd_get_id(its_cmd);
840 struct its_ite *ite;
841
842 ite = find_ite(its, device_id, event_id);
843 if (ite && its_is_collection_mapped(ite->collection)) {
844
845
846
847
848
849 vgic_its_invalidate_cache(kvm);
850
851 its_free_ite(kvm, ite);
852 return 0;
853 }
854
855 return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
856}
857
858
859
860
861
862static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
863 u64 *its_cmd)
864{
865 u32 device_id = its_cmd_get_deviceid(its_cmd);
866 u32 event_id = its_cmd_get_id(its_cmd);
867 u32 coll_id = its_cmd_get_collection(its_cmd);
868 struct kvm_vcpu *vcpu;
869 struct its_ite *ite;
870 struct its_collection *collection;
871
872 ite = find_ite(its, device_id, event_id);
873 if (!ite)
874 return E_ITS_MOVI_UNMAPPED_INTERRUPT;
875
876 if (!its_is_collection_mapped(ite->collection))
877 return E_ITS_MOVI_UNMAPPED_COLLECTION;
878
879 collection = find_collection(its, coll_id);
880 if (!its_is_collection_mapped(collection))
881 return E_ITS_MOVI_UNMAPPED_COLLECTION;
882
883 ite->collection = collection;
884 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
885
886 vgic_its_invalidate_cache(kvm);
887
888 return update_affinity(ite->irq, vcpu);
889}
890
891
892
893
894
895
896
897
898static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
899 gpa_t *eaddr)
900{
901 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
902 u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
903 phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser);
904 int esz = GITS_BASER_ENTRY_SIZE(baser);
905 int index, idx;
906 gfn_t gfn;
907 bool ret;
908
909 switch (type) {
910 case GITS_BASER_TYPE_DEVICE:
911 if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
912 return false;
913 break;
914 case GITS_BASER_TYPE_COLLECTION:
915
916 if (id >= BIT_ULL(16))
917 return false;
918 break;
919 default:
920 return false;
921 }
922
923 if (!(baser & GITS_BASER_INDIRECT)) {
924 phys_addr_t addr;
925
926 if (id >= (l1_tbl_size / esz))
927 return false;
928
929 addr = base + id * esz;
930 gfn = addr >> PAGE_SHIFT;
931
932 if (eaddr)
933 *eaddr = addr;
934
935 goto out;
936 }
937
938
939 index = id / (SZ_64K / esz);
940 if (index >= (l1_tbl_size / sizeof(u64)))
941 return false;
942
943
944 if (kvm_read_guest_lock(its->dev->kvm,
945 base + index * sizeof(indirect_ptr),
946 &indirect_ptr, sizeof(indirect_ptr)))
947 return false;
948
949 indirect_ptr = le64_to_cpu(indirect_ptr);
950
951
952 if (!(indirect_ptr & BIT_ULL(63)))
953 return false;
954
955
956 indirect_ptr &= GENMASK_ULL(51, 16);
957
958
959 index = id % (SZ_64K / esz);
960 indirect_ptr += index * esz;
961 gfn = indirect_ptr >> PAGE_SHIFT;
962
963 if (eaddr)
964 *eaddr = indirect_ptr;
965
966out:
967 idx = srcu_read_lock(&its->dev->kvm->srcu);
968 ret = kvm_is_visible_gfn(its->dev->kvm, gfn);
969 srcu_read_unlock(&its->dev->kvm->srcu, idx);
970 return ret;
971}
972
973static int vgic_its_alloc_collection(struct vgic_its *its,
974 struct its_collection **colp,
975 u32 coll_id)
976{
977 struct its_collection *collection;
978
979 if (!vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL))
980 return E_ITS_MAPC_COLLECTION_OOR;
981
982 collection = kzalloc(sizeof(*collection), GFP_KERNEL);
983 if (!collection)
984 return -ENOMEM;
985
986 collection->collection_id = coll_id;
987 collection->target_addr = COLLECTION_NOT_MAPPED;
988
989 list_add_tail(&collection->coll_list, &its->collection_list);
990 *colp = collection;
991
992 return 0;
993}
994
995static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
996{
997 struct its_collection *collection;
998 struct its_device *device;
999 struct its_ite *ite;
1000
1001
1002
1003
1004
1005
1006 collection = find_collection(its, coll_id);
1007 if (!collection)
1008 return;
1009
1010 for_each_lpi_its(device, ite, its)
1011 if (ite->collection &&
1012 ite->collection->collection_id == coll_id)
1013 ite->collection = NULL;
1014
1015 list_del(&collection->coll_list);
1016 kfree(collection);
1017}
1018
1019
1020static struct its_ite *vgic_its_alloc_ite(struct its_device *device,
1021 struct its_collection *collection,
1022 u32 event_id)
1023{
1024 struct its_ite *ite;
1025
1026 ite = kzalloc(sizeof(*ite), GFP_KERNEL);
1027 if (!ite)
1028 return ERR_PTR(-ENOMEM);
1029
1030 ite->event_id = event_id;
1031 ite->collection = collection;
1032
1033 list_add_tail(&ite->ite_list, &device->itt_head);
1034 return ite;
1035}
1036
1037
1038
1039
1040
1041static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
1042 u64 *its_cmd)
1043{
1044 u32 device_id = its_cmd_get_deviceid(its_cmd);
1045 u32 event_id = its_cmd_get_id(its_cmd);
1046 u32 coll_id = its_cmd_get_collection(its_cmd);
1047 struct its_ite *ite;
1048 struct kvm_vcpu *vcpu = NULL;
1049 struct its_device *device;
1050 struct its_collection *collection, *new_coll = NULL;
1051 struct vgic_irq *irq;
1052 int lpi_nr;
1053
1054 device = find_its_device(its, device_id);
1055 if (!device)
1056 return E_ITS_MAPTI_UNMAPPED_DEVICE;
1057
1058 if (event_id >= BIT_ULL(device->num_eventid_bits))
1059 return E_ITS_MAPTI_ID_OOR;
1060
1061 if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
1062 lpi_nr = its_cmd_get_physical_id(its_cmd);
1063 else
1064 lpi_nr = event_id;
1065 if (lpi_nr < GIC_LPI_OFFSET ||
1066 lpi_nr >= max_lpis_propbaser(kvm->arch.vgic.propbaser))
1067 return E_ITS_MAPTI_PHYSICALID_OOR;
1068
1069
1070 if (find_ite(its, device_id, event_id))
1071 return 0;
1072
1073 collection = find_collection(its, coll_id);
1074 if (!collection) {
1075 int ret = vgic_its_alloc_collection(its, &collection, coll_id);
1076 if (ret)
1077 return ret;
1078 new_coll = collection;
1079 }
1080
1081 ite = vgic_its_alloc_ite(device, collection, event_id);
1082 if (IS_ERR(ite)) {
1083 if (new_coll)
1084 vgic_its_free_collection(its, coll_id);
1085 return PTR_ERR(ite);
1086 }
1087
1088 if (its_is_collection_mapped(collection))
1089 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1090
1091 irq = vgic_add_lpi(kvm, lpi_nr, vcpu);
1092 if (IS_ERR(irq)) {
1093 if (new_coll)
1094 vgic_its_free_collection(its, coll_id);
1095 its_free_ite(kvm, ite);
1096 return PTR_ERR(irq);
1097 }
1098 ite->irq = irq;
1099
1100 return 0;
1101}
1102
1103
1104static void vgic_its_free_device(struct kvm *kvm, struct its_device *device)
1105{
1106 struct its_ite *ite, *temp;
1107
1108
1109
1110
1111
1112
1113 list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
1114 its_free_ite(kvm, ite);
1115
1116 vgic_its_invalidate_cache(kvm);
1117
1118 list_del(&device->dev_list);
1119 kfree(device);
1120}
1121
1122
1123static void vgic_its_free_device_list(struct kvm *kvm, struct vgic_its *its)
1124{
1125 struct its_device *cur, *temp;
1126
1127 list_for_each_entry_safe(cur, temp, &its->device_list, dev_list)
1128 vgic_its_free_device(kvm, cur);
1129}
1130
1131
1132static void vgic_its_free_collection_list(struct kvm *kvm, struct vgic_its *its)
1133{
1134 struct its_collection *cur, *temp;
1135
1136 list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
1137 vgic_its_free_collection(its, cur->collection_id);
1138}
1139
1140
1141static struct its_device *vgic_its_alloc_device(struct vgic_its *its,
1142 u32 device_id, gpa_t itt_addr,
1143 u8 num_eventid_bits)
1144{
1145 struct its_device *device;
1146
1147 device = kzalloc(sizeof(*device), GFP_KERNEL);
1148 if (!device)
1149 return ERR_PTR(-ENOMEM);
1150
1151 device->device_id = device_id;
1152 device->itt_addr = itt_addr;
1153 device->num_eventid_bits = num_eventid_bits;
1154 INIT_LIST_HEAD(&device->itt_head);
1155
1156 list_add_tail(&device->dev_list, &its->device_list);
1157 return device;
1158}
1159
1160
1161
1162
1163
1164static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
1165 u64 *its_cmd)
1166{
1167 u32 device_id = its_cmd_get_deviceid(its_cmd);
1168 bool valid = its_cmd_get_validbit(its_cmd);
1169 u8 num_eventid_bits = its_cmd_get_size(its_cmd);
1170 gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
1171 struct its_device *device;
1172
1173 if (!vgic_its_check_id(its, its->baser_device_table, device_id, NULL))
1174 return E_ITS_MAPD_DEVICE_OOR;
1175
1176 if (valid && num_eventid_bits > VITS_TYPER_IDBITS)
1177 return E_ITS_MAPD_ITTSIZE_OOR;
1178
1179 device = find_its_device(its, device_id);
1180
1181
1182
1183
1184
1185
1186 if (device)
1187 vgic_its_free_device(kvm, device);
1188
1189
1190
1191
1192
1193 if (!valid)
1194 return 0;
1195
1196 device = vgic_its_alloc_device(its, device_id, itt_addr,
1197 num_eventid_bits);
1198
1199 return PTR_ERR_OR_ZERO(device);
1200}
1201
1202
1203
1204
1205
1206static int vgic_its_cmd_handle_mapc(struct kvm *kvm, struct vgic_its *its,
1207 u64 *its_cmd)
1208{
1209 u16 coll_id;
1210 u32 target_addr;
1211 struct its_collection *collection;
1212 bool valid;
1213
1214 valid = its_cmd_get_validbit(its_cmd);
1215 coll_id = its_cmd_get_collection(its_cmd);
1216 target_addr = its_cmd_get_target_addr(its_cmd);
1217
1218 if (target_addr >= atomic_read(&kvm->online_vcpus))
1219 return E_ITS_MAPC_PROCNUM_OOR;
1220
1221 if (!valid) {
1222 vgic_its_free_collection(its, coll_id);
1223 vgic_its_invalidate_cache(kvm);
1224 } else {
1225 collection = find_collection(its, coll_id);
1226
1227 if (!collection) {
1228 int ret;
1229
1230 ret = vgic_its_alloc_collection(its, &collection,
1231 coll_id);
1232 if (ret)
1233 return ret;
1234 collection->target_addr = target_addr;
1235 } else {
1236 collection->target_addr = target_addr;
1237 update_affinity_collection(kvm, its, collection);
1238 }
1239 }
1240
1241 return 0;
1242}
1243
1244
1245
1246
1247
1248static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
1249 u64 *its_cmd)
1250{
1251 u32 device_id = its_cmd_get_deviceid(its_cmd);
1252 u32 event_id = its_cmd_get_id(its_cmd);
1253 struct its_ite *ite;
1254
1255
1256 ite = find_ite(its, device_id, event_id);
1257 if (!ite)
1258 return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
1259
1260 ite->irq->pending_latch = false;
1261
1262 if (ite->irq->hw)
1263 return irq_set_irqchip_state(ite->irq->host_irq,
1264 IRQCHIP_STATE_PENDING, false);
1265
1266 return 0;
1267}
1268
1269
1270
1271
1272
1273static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
1274 u64 *its_cmd)
1275{
1276 u32 device_id = its_cmd_get_deviceid(its_cmd);
1277 u32 event_id = its_cmd_get_id(its_cmd);
1278 struct its_ite *ite;
1279
1280
1281 ite = find_ite(its, device_id, event_id);
1282 if (!ite)
1283 return E_ITS_INV_UNMAPPED_INTERRUPT;
1284
1285 return update_lpi_config(kvm, ite->irq, NULL, true);
1286}
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296static int vgic_its_cmd_handle_invall(struct kvm *kvm, struct vgic_its *its,
1297 u64 *its_cmd)
1298{
1299 u32 coll_id = its_cmd_get_collection(its_cmd);
1300 struct its_collection *collection;
1301 struct kvm_vcpu *vcpu;
1302 struct vgic_irq *irq;
1303 u32 *intids;
1304 int irq_count, i;
1305
1306 collection = find_collection(its, coll_id);
1307 if (!its_is_collection_mapped(collection))
1308 return E_ITS_INVALL_UNMAPPED_COLLECTION;
1309
1310 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
1311
1312 irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids);
1313 if (irq_count < 0)
1314 return irq_count;
1315
1316 for (i = 0; i < irq_count; i++) {
1317 irq = vgic_get_irq(kvm, NULL, intids[i]);
1318 if (!irq)
1319 continue;
1320 update_lpi_config(kvm, irq, vcpu, false);
1321 vgic_put_irq(kvm, irq);
1322 }
1323
1324 kfree(intids);
1325
1326 if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm)
1327 its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe);
1328
1329 return 0;
1330}
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340static int vgic_its_cmd_handle_movall(struct kvm *kvm, struct vgic_its *its,
1341 u64 *its_cmd)
1342{
1343 u32 target1_addr = its_cmd_get_target_addr(its_cmd);
1344 u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
1345 struct kvm_vcpu *vcpu1, *vcpu2;
1346 struct vgic_irq *irq;
1347 u32 *intids;
1348 int irq_count, i;
1349
1350 if (target1_addr >= atomic_read(&kvm->online_vcpus) ||
1351 target2_addr >= atomic_read(&kvm->online_vcpus))
1352 return E_ITS_MOVALL_PROCNUM_OOR;
1353
1354 if (target1_addr == target2_addr)
1355 return 0;
1356
1357 vcpu1 = kvm_get_vcpu(kvm, target1_addr);
1358 vcpu2 = kvm_get_vcpu(kvm, target2_addr);
1359
1360 irq_count = vgic_copy_lpi_list(kvm, vcpu1, &intids);
1361 if (irq_count < 0)
1362 return irq_count;
1363
1364 for (i = 0; i < irq_count; i++) {
1365 irq = vgic_get_irq(kvm, NULL, intids[i]);
1366
1367 update_affinity(irq, vcpu2);
1368
1369 vgic_put_irq(kvm, irq);
1370 }
1371
1372 vgic_its_invalidate_cache(kvm);
1373
1374 kfree(intids);
1375 return 0;
1376}
1377
1378
1379
1380
1381
1382static int vgic_its_cmd_handle_int(struct kvm *kvm, struct vgic_its *its,
1383 u64 *its_cmd)
1384{
1385 u32 msi_data = its_cmd_get_id(its_cmd);
1386 u64 msi_devid = its_cmd_get_deviceid(its_cmd);
1387
1388 return vgic_its_trigger_msi(kvm, its, msi_devid, msi_data);
1389}
1390
1391
1392
1393
1394
1395static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
1396 u64 *its_cmd)
1397{
1398 int ret = -ENODEV;
1399
1400 mutex_lock(&its->its_lock);
1401 switch (its_cmd_get_command(its_cmd)) {
1402 case GITS_CMD_MAPD:
1403 ret = vgic_its_cmd_handle_mapd(kvm, its, its_cmd);
1404 break;
1405 case GITS_CMD_MAPC:
1406 ret = vgic_its_cmd_handle_mapc(kvm, its, its_cmd);
1407 break;
1408 case GITS_CMD_MAPI:
1409 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1410 break;
1411 case GITS_CMD_MAPTI:
1412 ret = vgic_its_cmd_handle_mapi(kvm, its, its_cmd);
1413 break;
1414 case GITS_CMD_MOVI:
1415 ret = vgic_its_cmd_handle_movi(kvm, its, its_cmd);
1416 break;
1417 case GITS_CMD_DISCARD:
1418 ret = vgic_its_cmd_handle_discard(kvm, its, its_cmd);
1419 break;
1420 case GITS_CMD_CLEAR:
1421 ret = vgic_its_cmd_handle_clear(kvm, its, its_cmd);
1422 break;
1423 case GITS_CMD_MOVALL:
1424 ret = vgic_its_cmd_handle_movall(kvm, its, its_cmd);
1425 break;
1426 case GITS_CMD_INT:
1427 ret = vgic_its_cmd_handle_int(kvm, its, its_cmd);
1428 break;
1429 case GITS_CMD_INV:
1430 ret = vgic_its_cmd_handle_inv(kvm, its, its_cmd);
1431 break;
1432 case GITS_CMD_INVALL:
1433 ret = vgic_its_cmd_handle_invall(kvm, its, its_cmd);
1434 break;
1435 case GITS_CMD_SYNC:
1436
1437 ret = 0;
1438 break;
1439 }
1440 mutex_unlock(&its->its_lock);
1441
1442 return ret;
1443}
1444
1445static u64 vgic_sanitise_its_baser(u64 reg)
1446{
1447 reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
1448 GITS_BASER_SHAREABILITY_SHIFT,
1449 vgic_sanitise_shareability);
1450 reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
1451 GITS_BASER_INNER_CACHEABILITY_SHIFT,
1452 vgic_sanitise_inner_cacheability);
1453 reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
1454 GITS_BASER_OUTER_CACHEABILITY_SHIFT,
1455 vgic_sanitise_outer_cacheability);
1456
1457
1458 reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
1459
1460 return reg;
1461}
1462
1463static u64 vgic_sanitise_its_cbaser(u64 reg)
1464{
1465 reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
1466 GITS_CBASER_SHAREABILITY_SHIFT,
1467 vgic_sanitise_shareability);
1468 reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
1469 GITS_CBASER_INNER_CACHEABILITY_SHIFT,
1470 vgic_sanitise_inner_cacheability);
1471 reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
1472 GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
1473 vgic_sanitise_outer_cacheability);
1474
1475
1476 reg &= ~GENMASK_ULL(15, 12);
1477
1478 return reg;
1479}
1480
1481static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
1482 struct vgic_its *its,
1483 gpa_t addr, unsigned int len)
1484{
1485 return extract_bytes(its->cbaser, addr & 7, len);
1486}
1487
1488static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
1489 gpa_t addr, unsigned int len,
1490 unsigned long val)
1491{
1492
1493 if (its->enabled)
1494 return;
1495
1496 mutex_lock(&its->cmd_lock);
1497 its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
1498 its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
1499 its->creadr = 0;
1500
1501
1502
1503
1504 its->cwriter = its->creadr;
1505 mutex_unlock(&its->cmd_lock);
1506}
1507
1508#define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
1509#define ITS_CMD_SIZE 32
1510#define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
1511
1512
1513static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its)
1514{
1515 gpa_t cbaser;
1516 u64 cmd_buf[4];
1517
1518
1519 if (!its->enabled)
1520 return;
1521
1522 cbaser = GITS_CBASER_ADDRESS(its->cbaser);
1523
1524 while (its->cwriter != its->creadr) {
1525 int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr,
1526 cmd_buf, ITS_CMD_SIZE);
1527
1528
1529
1530
1531
1532
1533
1534 if (!ret)
1535 vgic_its_handle_command(kvm, its, cmd_buf);
1536
1537 its->creadr += ITS_CMD_SIZE;
1538 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
1539 its->creadr = 0;
1540 }
1541}
1542
1543
1544
1545
1546
1547
1548
1549static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
1550 gpa_t addr, unsigned int len,
1551 unsigned long val)
1552{
1553 u64 reg;
1554
1555 if (!its)
1556 return;
1557
1558 mutex_lock(&its->cmd_lock);
1559
1560 reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
1561 reg = ITS_CMD_OFFSET(reg);
1562 if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1563 mutex_unlock(&its->cmd_lock);
1564 return;
1565 }
1566 its->cwriter = reg;
1567
1568 vgic_its_process_commands(kvm, its);
1569
1570 mutex_unlock(&its->cmd_lock);
1571}
1572
1573static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
1574 struct vgic_its *its,
1575 gpa_t addr, unsigned int len)
1576{
1577 return extract_bytes(its->cwriter, addr & 0x7, len);
1578}
1579
1580static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
1581 struct vgic_its *its,
1582 gpa_t addr, unsigned int len)
1583{
1584 return extract_bytes(its->creadr, addr & 0x7, len);
1585}
1586
1587static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
1588 struct vgic_its *its,
1589 gpa_t addr, unsigned int len,
1590 unsigned long val)
1591{
1592 u32 cmd_offset;
1593 int ret = 0;
1594
1595 mutex_lock(&its->cmd_lock);
1596
1597 if (its->enabled) {
1598 ret = -EBUSY;
1599 goto out;
1600 }
1601
1602 cmd_offset = ITS_CMD_OFFSET(val);
1603 if (cmd_offset >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
1604 ret = -EINVAL;
1605 goto out;
1606 }
1607
1608 its->creadr = cmd_offset;
1609out:
1610 mutex_unlock(&its->cmd_lock);
1611 return ret;
1612}
1613
1614#define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
1615static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
1616 struct vgic_its *its,
1617 gpa_t addr, unsigned int len)
1618{
1619 u64 reg;
1620
1621 switch (BASER_INDEX(addr)) {
1622 case 0:
1623 reg = its->baser_device_table;
1624 break;
1625 case 1:
1626 reg = its->baser_coll_table;
1627 break;
1628 default:
1629 reg = 0;
1630 break;
1631 }
1632
1633 return extract_bytes(reg, addr & 7, len);
1634}
1635
1636#define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
1637static void vgic_mmio_write_its_baser(struct kvm *kvm,
1638 struct vgic_its *its,
1639 gpa_t addr, unsigned int len,
1640 unsigned long val)
1641{
1642 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
1643 u64 entry_size, table_type;
1644 u64 reg, *regptr, clearbits = 0;
1645
1646
1647 if (its->enabled)
1648 return;
1649
1650 switch (BASER_INDEX(addr)) {
1651 case 0:
1652 regptr = &its->baser_device_table;
1653 entry_size = abi->dte_esz;
1654 table_type = GITS_BASER_TYPE_DEVICE;
1655 break;
1656 case 1:
1657 regptr = &its->baser_coll_table;
1658 entry_size = abi->cte_esz;
1659 table_type = GITS_BASER_TYPE_COLLECTION;
1660 clearbits = GITS_BASER_INDIRECT;
1661 break;
1662 default:
1663 return;
1664 }
1665
1666 reg = update_64bit_reg(*regptr, addr & 7, len, val);
1667 reg &= ~GITS_BASER_RO_MASK;
1668 reg &= ~clearbits;
1669
1670 reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
1671 reg |= table_type << GITS_BASER_TYPE_SHIFT;
1672 reg = vgic_sanitise_its_baser(reg);
1673
1674 *regptr = reg;
1675
1676 if (!(reg & GITS_BASER_VALID)) {
1677
1678 mutex_lock(&its->its_lock);
1679 switch (table_type) {
1680 case GITS_BASER_TYPE_DEVICE:
1681 vgic_its_free_device_list(kvm, its);
1682 break;
1683 case GITS_BASER_TYPE_COLLECTION:
1684 vgic_its_free_collection_list(kvm, its);
1685 break;
1686 }
1687 mutex_unlock(&its->its_lock);
1688 }
1689}
1690
1691static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
1692 struct vgic_its *its,
1693 gpa_t addr, unsigned int len)
1694{
1695 u32 reg = 0;
1696
1697 mutex_lock(&its->cmd_lock);
1698 if (its->creadr == its->cwriter)
1699 reg |= GITS_CTLR_QUIESCENT;
1700 if (its->enabled)
1701 reg |= GITS_CTLR_ENABLE;
1702 mutex_unlock(&its->cmd_lock);
1703
1704 return reg;
1705}
1706
1707static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
1708 gpa_t addr, unsigned int len,
1709 unsigned long val)
1710{
1711 mutex_lock(&its->cmd_lock);
1712
1713
1714
1715
1716
1717 if (!its->enabled && (val & GITS_CTLR_ENABLE) &&
1718 (!(its->baser_device_table & GITS_BASER_VALID) ||
1719 !(its->baser_coll_table & GITS_BASER_VALID) ||
1720 !(its->cbaser & GITS_CBASER_VALID)))
1721 goto out;
1722
1723 its->enabled = !!(val & GITS_CTLR_ENABLE);
1724 if (!its->enabled)
1725 vgic_its_invalidate_cache(kvm);
1726
1727
1728
1729
1730
1731 vgic_its_process_commands(kvm, its);
1732
1733out:
1734 mutex_unlock(&its->cmd_lock);
1735}
1736
1737#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
1738{ \
1739 .reg_offset = off, \
1740 .len = length, \
1741 .access_flags = acc, \
1742 .its_read = rd, \
1743 .its_write = wr, \
1744}
1745
1746#define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
1747{ \
1748 .reg_offset = off, \
1749 .len = length, \
1750 .access_flags = acc, \
1751 .its_read = rd, \
1752 .its_write = wr, \
1753 .uaccess_its_write = uwr, \
1754}
1755
1756static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
1757 gpa_t addr, unsigned int len, unsigned long val)
1758{
1759
1760}
1761
1762static struct vgic_register_region its_registers[] = {
1763 REGISTER_ITS_DESC(GITS_CTLR,
1764 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
1765 VGIC_ACCESS_32bit),
1766 REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
1767 vgic_mmio_read_its_iidr, its_mmio_write_wi,
1768 vgic_mmio_uaccess_write_its_iidr, 4,
1769 VGIC_ACCESS_32bit),
1770 REGISTER_ITS_DESC(GITS_TYPER,
1771 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
1772 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1773 REGISTER_ITS_DESC(GITS_CBASER,
1774 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
1775 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1776 REGISTER_ITS_DESC(GITS_CWRITER,
1777 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
1778 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1779 REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
1780 vgic_mmio_read_its_creadr, its_mmio_write_wi,
1781 vgic_mmio_uaccess_write_its_creadr, 8,
1782 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1783 REGISTER_ITS_DESC(GITS_BASER,
1784 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
1785 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
1786 REGISTER_ITS_DESC(GITS_IDREGS_BASE,
1787 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
1788 VGIC_ACCESS_32bit),
1789};
1790
1791
1792void vgic_enable_lpis(struct kvm_vcpu *vcpu)
1793{
1794 if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
1795 its_sync_lpi_pending_table(vcpu);
1796}
1797
1798static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its,
1799 u64 addr)
1800{
1801 struct vgic_io_device *iodev = &its->iodev;
1802 int ret;
1803
1804 mutex_lock(&kvm->slots_lock);
1805 if (!IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1806 ret = -EBUSY;
1807 goto out;
1808 }
1809
1810 its->vgic_its_base = addr;
1811 iodev->regions = its_registers;
1812 iodev->nr_regions = ARRAY_SIZE(its_registers);
1813 kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
1814
1815 iodev->base_addr = its->vgic_its_base;
1816 iodev->iodev_type = IODEV_ITS;
1817 iodev->its = its;
1818 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
1819 KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
1820out:
1821 mutex_unlock(&kvm->slots_lock);
1822
1823 return ret;
1824}
1825
1826
1827#define LPI_DEFAULT_PCPU_CACHE_SIZE 16
1828
1829void vgic_lpi_translation_cache_init(struct kvm *kvm)
1830{
1831 struct vgic_dist *dist = &kvm->arch.vgic;
1832 unsigned int sz;
1833 int i;
1834
1835 if (!list_empty(&dist->lpi_translation_cache))
1836 return;
1837
1838 sz = atomic_read(&kvm->online_vcpus) * LPI_DEFAULT_PCPU_CACHE_SIZE;
1839
1840 for (i = 0; i < sz; i++) {
1841 struct vgic_translation_cache_entry *cte;
1842
1843
1844 cte = kzalloc(sizeof(*cte), GFP_KERNEL);
1845 if (WARN_ON(!cte))
1846 break;
1847
1848 INIT_LIST_HEAD(&cte->entry);
1849 list_add(&cte->entry, &dist->lpi_translation_cache);
1850 }
1851}
1852
1853void vgic_lpi_translation_cache_destroy(struct kvm *kvm)
1854{
1855 struct vgic_dist *dist = &kvm->arch.vgic;
1856 struct vgic_translation_cache_entry *cte, *tmp;
1857
1858 vgic_its_invalidate_cache(kvm);
1859
1860 list_for_each_entry_safe(cte, tmp,
1861 &dist->lpi_translation_cache, entry) {
1862 list_del(&cte->entry);
1863 kfree(cte);
1864 }
1865}
1866
1867#define INITIAL_BASER_VALUE \
1868 (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
1869 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
1870 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
1871 GITS_BASER_PAGE_SIZE_64K)
1872
1873#define INITIAL_PROPBASER_VALUE \
1874 (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
1875 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
1876 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
1877
1878static int vgic_its_create(struct kvm_device *dev, u32 type)
1879{
1880 struct vgic_its *its;
1881
1882 if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
1883 return -ENODEV;
1884
1885 its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
1886 if (!its)
1887 return -ENOMEM;
1888
1889 if (vgic_initialized(dev->kvm)) {
1890 int ret = vgic_v4_init(dev->kvm);
1891 if (ret < 0) {
1892 kfree(its);
1893 return ret;
1894 }
1895
1896 vgic_lpi_translation_cache_init(dev->kvm);
1897 }
1898
1899 mutex_init(&its->its_lock);
1900 mutex_init(&its->cmd_lock);
1901
1902 its->vgic_its_base = VGIC_ADDR_UNDEF;
1903
1904 INIT_LIST_HEAD(&its->device_list);
1905 INIT_LIST_HEAD(&its->collection_list);
1906
1907 dev->kvm->arch.vgic.msis_require_devid = true;
1908 dev->kvm->arch.vgic.has_its = true;
1909 its->enabled = false;
1910 its->dev = dev;
1911
1912 its->baser_device_table = INITIAL_BASER_VALUE |
1913 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
1914 its->baser_coll_table = INITIAL_BASER_VALUE |
1915 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
1916 dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
1917
1918 dev->private = its;
1919
1920 return vgic_its_set_abi(its, NR_ITS_ABIS - 1);
1921}
1922
1923static void vgic_its_destroy(struct kvm_device *kvm_dev)
1924{
1925 struct kvm *kvm = kvm_dev->kvm;
1926 struct vgic_its *its = kvm_dev->private;
1927
1928 mutex_lock(&its->its_lock);
1929
1930 vgic_its_free_device_list(kvm, its);
1931 vgic_its_free_collection_list(kvm, its);
1932
1933 mutex_unlock(&its->its_lock);
1934 kfree(its);
1935 kfree(kvm_dev);
1936}
1937
1938static int vgic_its_has_attr_regs(struct kvm_device *dev,
1939 struct kvm_device_attr *attr)
1940{
1941 const struct vgic_register_region *region;
1942 gpa_t offset = attr->attr;
1943 int align;
1944
1945 align = (offset < GITS_TYPER) || (offset >= GITS_PIDR4) ? 0x3 : 0x7;
1946
1947 if (offset & align)
1948 return -EINVAL;
1949
1950 region = vgic_find_mmio_region(its_registers,
1951 ARRAY_SIZE(its_registers),
1952 offset);
1953 if (!region)
1954 return -ENXIO;
1955
1956 return 0;
1957}
1958
1959static int vgic_its_attr_regs_access(struct kvm_device *dev,
1960 struct kvm_device_attr *attr,
1961 u64 *reg, bool is_write)
1962{
1963 const struct vgic_register_region *region;
1964 struct vgic_its *its;
1965 gpa_t addr, offset;
1966 unsigned int len;
1967 int align, ret = 0;
1968
1969 its = dev->private;
1970 offset = attr->attr;
1971
1972
1973
1974
1975
1976
1977
1978
1979 if ((offset < GITS_TYPER) || (offset >= GITS_PIDR4))
1980 align = 0x3;
1981 else
1982 align = 0x7;
1983
1984 if (offset & align)
1985 return -EINVAL;
1986
1987 mutex_lock(&dev->kvm->lock);
1988
1989 if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
1990 ret = -ENXIO;
1991 goto out;
1992 }
1993
1994 region = vgic_find_mmio_region(its_registers,
1995 ARRAY_SIZE(its_registers),
1996 offset);
1997 if (!region) {
1998 ret = -ENXIO;
1999 goto out;
2000 }
2001
2002 if (!lock_all_vcpus(dev->kvm)) {
2003 ret = -EBUSY;
2004 goto out;
2005 }
2006
2007 addr = its->vgic_its_base + offset;
2008
2009 len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
2010
2011 if (is_write) {
2012 if (region->uaccess_its_write)
2013 ret = region->uaccess_its_write(dev->kvm, its, addr,
2014 len, *reg);
2015 else
2016 region->its_write(dev->kvm, its, addr, len, *reg);
2017 } else {
2018 *reg = region->its_read(dev->kvm, its, addr, len);
2019 }
2020 unlock_all_vcpus(dev->kvm);
2021out:
2022 mutex_unlock(&dev->kvm->lock);
2023 return ret;
2024}
2025
2026static u32 compute_next_devid_offset(struct list_head *h,
2027 struct its_device *dev)
2028{
2029 struct its_device *next;
2030 u32 next_offset;
2031
2032 if (list_is_last(&dev->dev_list, h))
2033 return 0;
2034 next = list_next_entry(dev, dev_list);
2035 next_offset = next->device_id - dev->device_id;
2036
2037 return min_t(u32, next_offset, VITS_DTE_MAX_DEVID_OFFSET);
2038}
2039
2040static u32 compute_next_eventid_offset(struct list_head *h, struct its_ite *ite)
2041{
2042 struct its_ite *next;
2043 u32 next_offset;
2044
2045 if (list_is_last(&ite->ite_list, h))
2046 return 0;
2047 next = list_next_entry(ite, ite_list);
2048 next_offset = next->event_id - ite->event_id;
2049
2050 return min_t(u32, next_offset, VITS_ITE_MAX_EVENTID_OFFSET);
2051}
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063typedef int (*entry_fn_t)(struct vgic_its *its, u32 id, void *entry,
2064 void *opaque);
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz,
2082 int start_id, entry_fn_t fn, void *opaque)
2083{
2084 struct kvm *kvm = its->dev->kvm;
2085 unsigned long len = size;
2086 int id = start_id;
2087 gpa_t gpa = base;
2088 char entry[ESZ_MAX];
2089 int ret;
2090
2091 memset(entry, 0, esz);
2092
2093 while (len > 0) {
2094 int next_offset;
2095 size_t byte_offset;
2096
2097 ret = kvm_read_guest_lock(kvm, gpa, entry, esz);
2098 if (ret)
2099 return ret;
2100
2101 next_offset = fn(its, id, entry, opaque);
2102 if (next_offset <= 0)
2103 return next_offset;
2104
2105 byte_offset = next_offset * esz;
2106 id += next_offset;
2107 gpa += byte_offset;
2108 len -= byte_offset;
2109 }
2110 return 1;
2111}
2112
2113
2114
2115
2116static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
2117 struct its_ite *ite, gpa_t gpa, int ite_esz)
2118{
2119 struct kvm *kvm = its->dev->kvm;
2120 u32 next_offset;
2121 u64 val;
2122
2123 next_offset = compute_next_eventid_offset(&dev->itt_head, ite);
2124 val = ((u64)next_offset << KVM_ITS_ITE_NEXT_SHIFT) |
2125 ((u64)ite->irq->intid << KVM_ITS_ITE_PINTID_SHIFT) |
2126 ite->collection->collection_id;
2127 val = cpu_to_le64(val);
2128 return kvm_write_guest_lock(kvm, gpa, &val, ite_esz);
2129}
2130
2131
2132
2133
2134
2135
2136
2137static int vgic_its_restore_ite(struct vgic_its *its, u32 event_id,
2138 void *ptr, void *opaque)
2139{
2140 struct its_device *dev = (struct its_device *)opaque;
2141 struct its_collection *collection;
2142 struct kvm *kvm = its->dev->kvm;
2143 struct kvm_vcpu *vcpu = NULL;
2144 u64 val;
2145 u64 *p = (u64 *)ptr;
2146 struct vgic_irq *irq;
2147 u32 coll_id, lpi_id;
2148 struct its_ite *ite;
2149 u32 offset;
2150
2151 val = *p;
2152
2153 val = le64_to_cpu(val);
2154
2155 coll_id = val & KVM_ITS_ITE_ICID_MASK;
2156 lpi_id = (val & KVM_ITS_ITE_PINTID_MASK) >> KVM_ITS_ITE_PINTID_SHIFT;
2157
2158 if (!lpi_id)
2159 return 1;
2160
2161 if (lpi_id < VGIC_MIN_LPI)
2162 return -EINVAL;
2163
2164 offset = val >> KVM_ITS_ITE_NEXT_SHIFT;
2165 if (event_id + offset >= BIT_ULL(dev->num_eventid_bits))
2166 return -EINVAL;
2167
2168 collection = find_collection(its, coll_id);
2169 if (!collection)
2170 return -EINVAL;
2171
2172 ite = vgic_its_alloc_ite(dev, collection, event_id);
2173 if (IS_ERR(ite))
2174 return PTR_ERR(ite);
2175
2176 if (its_is_collection_mapped(collection))
2177 vcpu = kvm_get_vcpu(kvm, collection->target_addr);
2178
2179 irq = vgic_add_lpi(kvm, lpi_id, vcpu);
2180 if (IS_ERR(irq))
2181 return PTR_ERR(irq);
2182 ite->irq = irq;
2183
2184 return offset;
2185}
2186
2187static int vgic_its_ite_cmp(void *priv, struct list_head *a,
2188 struct list_head *b)
2189{
2190 struct its_ite *itea = container_of(a, struct its_ite, ite_list);
2191 struct its_ite *iteb = container_of(b, struct its_ite, ite_list);
2192
2193 if (itea->event_id < iteb->event_id)
2194 return -1;
2195 else
2196 return 1;
2197}
2198
2199static int vgic_its_save_itt(struct vgic_its *its, struct its_device *device)
2200{
2201 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2202 gpa_t base = device->itt_addr;
2203 struct its_ite *ite;
2204 int ret;
2205 int ite_esz = abi->ite_esz;
2206
2207 list_sort(NULL, &device->itt_head, vgic_its_ite_cmp);
2208
2209 list_for_each_entry(ite, &device->itt_head, ite_list) {
2210 gpa_t gpa = base + ite->event_id * ite_esz;
2211
2212
2213
2214
2215
2216
2217
2218 if (ite->irq->hw)
2219 return -EACCES;
2220
2221 ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz);
2222 if (ret)
2223 return ret;
2224 }
2225 return 0;
2226}
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236static int vgic_its_restore_itt(struct vgic_its *its, struct its_device *dev)
2237{
2238 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2239 gpa_t base = dev->itt_addr;
2240 int ret;
2241 int ite_esz = abi->ite_esz;
2242 size_t max_size = BIT_ULL(dev->num_eventid_bits) * ite_esz;
2243
2244 ret = scan_its_table(its, base, max_size, ite_esz, 0,
2245 vgic_its_restore_ite, dev);
2246
2247
2248 if (ret > 0)
2249 ret = 0;
2250
2251 return ret;
2252}
2253
2254
2255
2256
2257
2258
2259
2260
2261static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
2262 gpa_t ptr, int dte_esz)
2263{
2264 struct kvm *kvm = its->dev->kvm;
2265 u64 val, itt_addr_field;
2266 u32 next_offset;
2267
2268 itt_addr_field = dev->itt_addr >> 8;
2269 next_offset = compute_next_devid_offset(&its->device_list, dev);
2270 val = (1ULL << KVM_ITS_DTE_VALID_SHIFT |
2271 ((u64)next_offset << KVM_ITS_DTE_NEXT_SHIFT) |
2272 (itt_addr_field << KVM_ITS_DTE_ITTADDR_SHIFT) |
2273 (dev->num_eventid_bits - 1));
2274 val = cpu_to_le64(val);
2275 return kvm_write_guest_lock(kvm, ptr, &val, dte_esz);
2276}
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289static int vgic_its_restore_dte(struct vgic_its *its, u32 id,
2290 void *ptr, void *opaque)
2291{
2292 struct its_device *dev;
2293 gpa_t itt_addr;
2294 u8 num_eventid_bits;
2295 u64 entry = *(u64 *)ptr;
2296 bool valid;
2297 u32 offset;
2298 int ret;
2299
2300 entry = le64_to_cpu(entry);
2301
2302 valid = entry >> KVM_ITS_DTE_VALID_SHIFT;
2303 num_eventid_bits = (entry & KVM_ITS_DTE_SIZE_MASK) + 1;
2304 itt_addr = ((entry & KVM_ITS_DTE_ITTADDR_MASK)
2305 >> KVM_ITS_DTE_ITTADDR_SHIFT) << 8;
2306
2307 if (!valid)
2308 return 1;
2309
2310
2311 offset = (entry & KVM_ITS_DTE_NEXT_MASK) >> KVM_ITS_DTE_NEXT_SHIFT;
2312
2313 dev = vgic_its_alloc_device(its, id, itt_addr, num_eventid_bits);
2314 if (IS_ERR(dev))
2315 return PTR_ERR(dev);
2316
2317 ret = vgic_its_restore_itt(its, dev);
2318 if (ret) {
2319 vgic_its_free_device(its->dev->kvm, dev);
2320 return ret;
2321 }
2322
2323 return offset;
2324}
2325
2326static int vgic_its_device_cmp(void *priv, struct list_head *a,
2327 struct list_head *b)
2328{
2329 struct its_device *deva = container_of(a, struct its_device, dev_list);
2330 struct its_device *devb = container_of(b, struct its_device, dev_list);
2331
2332 if (deva->device_id < devb->device_id)
2333 return -1;
2334 else
2335 return 1;
2336}
2337
2338
2339
2340
2341
2342
2343
2344
2345static int vgic_its_save_device_tables(struct vgic_its *its)
2346{
2347 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2348 u64 baser = its->baser_device_table;
2349 struct its_device *dev;
2350 int dte_esz = abi->dte_esz;
2351
2352 if (!(baser & GITS_BASER_VALID))
2353 return 0;
2354
2355 list_sort(NULL, &its->device_list, vgic_its_device_cmp);
2356
2357 list_for_each_entry(dev, &its->device_list, dev_list) {
2358 int ret;
2359 gpa_t eaddr;
2360
2361 if (!vgic_its_check_id(its, baser,
2362 dev->device_id, &eaddr))
2363 return -EINVAL;
2364
2365 ret = vgic_its_save_itt(its, dev);
2366 if (ret)
2367 return ret;
2368
2369 ret = vgic_its_save_dte(its, dev, eaddr, dte_esz);
2370 if (ret)
2371 return ret;
2372 }
2373 return 0;
2374}
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388static int handle_l1_dte(struct vgic_its *its, u32 id, void *addr,
2389 void *opaque)
2390{
2391 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2392 int l2_start_id = id * (SZ_64K / abi->dte_esz);
2393 u64 entry = *(u64 *)addr;
2394 int dte_esz = abi->dte_esz;
2395 gpa_t gpa;
2396 int ret;
2397
2398 entry = le64_to_cpu(entry);
2399
2400 if (!(entry & KVM_ITS_L1E_VALID_MASK))
2401 return 1;
2402
2403 gpa = entry & KVM_ITS_L1E_ADDR_MASK;
2404
2405 ret = scan_its_table(its, gpa, SZ_64K, dte_esz,
2406 l2_start_id, vgic_its_restore_dte, NULL);
2407
2408 return ret;
2409}
2410
2411
2412
2413
2414
2415static int vgic_its_restore_device_tables(struct vgic_its *its)
2416{
2417 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2418 u64 baser = its->baser_device_table;
2419 int l1_esz, ret;
2420 int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2421 gpa_t l1_gpa;
2422
2423 if (!(baser & GITS_BASER_VALID))
2424 return 0;
2425
2426 l1_gpa = GITS_BASER_ADDR_48_to_52(baser);
2427
2428 if (baser & GITS_BASER_INDIRECT) {
2429 l1_esz = GITS_LVL1_ENTRY_SIZE;
2430 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2431 handle_l1_dte, NULL);
2432 } else {
2433 l1_esz = abi->dte_esz;
2434 ret = scan_its_table(its, l1_gpa, l1_tbl_size, l1_esz, 0,
2435 vgic_its_restore_dte, NULL);
2436 }
2437
2438
2439 if (ret > 0)
2440 ret = 0;
2441
2442 return ret;
2443}
2444
2445static int vgic_its_save_cte(struct vgic_its *its,
2446 struct its_collection *collection,
2447 gpa_t gpa, int esz)
2448{
2449 u64 val;
2450
2451 val = (1ULL << KVM_ITS_CTE_VALID_SHIFT |
2452 ((u64)collection->target_addr << KVM_ITS_CTE_RDBASE_SHIFT) |
2453 collection->collection_id);
2454 val = cpu_to_le64(val);
2455 return kvm_write_guest_lock(its->dev->kvm, gpa, &val, esz);
2456}
2457
2458static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
2459{
2460 struct its_collection *collection;
2461 struct kvm *kvm = its->dev->kvm;
2462 u32 target_addr, coll_id;
2463 u64 val;
2464 int ret;
2465
2466 BUG_ON(esz > sizeof(val));
2467 ret = kvm_read_guest_lock(kvm, gpa, &val, esz);
2468 if (ret)
2469 return ret;
2470 val = le64_to_cpu(val);
2471 if (!(val & KVM_ITS_CTE_VALID_MASK))
2472 return 0;
2473
2474 target_addr = (u32)(val >> KVM_ITS_CTE_RDBASE_SHIFT);
2475 coll_id = val & KVM_ITS_CTE_ICID_MASK;
2476
2477 if (target_addr != COLLECTION_NOT_MAPPED &&
2478 target_addr >= atomic_read(&kvm->online_vcpus))
2479 return -EINVAL;
2480
2481 collection = find_collection(its, coll_id);
2482 if (collection)
2483 return -EEXIST;
2484 ret = vgic_its_alloc_collection(its, &collection, coll_id);
2485 if (ret)
2486 return ret;
2487 collection->target_addr = target_addr;
2488 return 1;
2489}
2490
2491
2492
2493
2494
2495static int vgic_its_save_collection_table(struct vgic_its *its)
2496{
2497 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2498 u64 baser = its->baser_coll_table;
2499 gpa_t gpa = GITS_BASER_ADDR_48_to_52(baser);
2500 struct its_collection *collection;
2501 u64 val;
2502 size_t max_size, filled = 0;
2503 int ret, cte_esz = abi->cte_esz;
2504
2505 if (!(baser & GITS_BASER_VALID))
2506 return 0;
2507
2508 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2509
2510 list_for_each_entry(collection, &its->collection_list, coll_list) {
2511 ret = vgic_its_save_cte(its, collection, gpa, cte_esz);
2512 if (ret)
2513 return ret;
2514 gpa += cte_esz;
2515 filled += cte_esz;
2516 }
2517
2518 if (filled == max_size)
2519 return 0;
2520
2521
2522
2523
2524
2525 val = 0;
2526 BUG_ON(cte_esz > sizeof(val));
2527 ret = kvm_write_guest_lock(its->dev->kvm, gpa, &val, cte_esz);
2528 return ret;
2529}
2530
2531
2532
2533
2534
2535
2536static int vgic_its_restore_collection_table(struct vgic_its *its)
2537{
2538 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2539 u64 baser = its->baser_coll_table;
2540 int cte_esz = abi->cte_esz;
2541 size_t max_size, read = 0;
2542 gpa_t gpa;
2543 int ret;
2544
2545 if (!(baser & GITS_BASER_VALID))
2546 return 0;
2547
2548 gpa = GITS_BASER_ADDR_48_to_52(baser);
2549
2550 max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2551
2552 while (read < max_size) {
2553 ret = vgic_its_restore_cte(its, gpa, cte_esz);
2554 if (ret <= 0)
2555 break;
2556 gpa += cte_esz;
2557 read += cte_esz;
2558 }
2559
2560 if (ret > 0)
2561 return 0;
2562
2563 return ret;
2564}
2565
2566
2567
2568
2569
2570static int vgic_its_save_tables_v0(struct vgic_its *its)
2571{
2572 int ret;
2573
2574 ret = vgic_its_save_device_tables(its);
2575 if (ret)
2576 return ret;
2577
2578 return vgic_its_save_collection_table(its);
2579}
2580
2581
2582
2583
2584
2585
2586static int vgic_its_restore_tables_v0(struct vgic_its *its)
2587{
2588 int ret;
2589
2590 ret = vgic_its_restore_collection_table(its);
2591 if (ret)
2592 return ret;
2593
2594 return vgic_its_restore_device_tables(its);
2595}
2596
2597static int vgic_its_commit_v0(struct vgic_its *its)
2598{
2599 const struct vgic_its_abi *abi;
2600
2601 abi = vgic_its_get_abi(its);
2602 its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2603 its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
2604
2605 its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
2606 << GITS_BASER_ENTRY_SIZE_SHIFT);
2607
2608 its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
2609 << GITS_BASER_ENTRY_SIZE_SHIFT);
2610 return 0;
2611}
2612
2613static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
2614{
2615
2616 its->baser_coll_table &= ~GITS_BASER_VALID;
2617 its->baser_device_table &= ~GITS_BASER_VALID;
2618 its->cbaser = 0;
2619 its->creadr = 0;
2620 its->cwriter = 0;
2621 its->enabled = 0;
2622 vgic_its_free_device_list(kvm, its);
2623 vgic_its_free_collection_list(kvm, its);
2624}
2625
2626static int vgic_its_has_attr(struct kvm_device *dev,
2627 struct kvm_device_attr *attr)
2628{
2629 switch (attr->group) {
2630 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2631 switch (attr->attr) {
2632 case KVM_VGIC_ITS_ADDR_TYPE:
2633 return 0;
2634 }
2635 break;
2636 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2637 switch (attr->attr) {
2638 case KVM_DEV_ARM_VGIC_CTRL_INIT:
2639 return 0;
2640 case KVM_DEV_ARM_ITS_CTRL_RESET:
2641 return 0;
2642 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2643 return 0;
2644 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2645 return 0;
2646 }
2647 break;
2648 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
2649 return vgic_its_has_attr_regs(dev, attr);
2650 }
2651 return -ENXIO;
2652}
2653
2654static int vgic_its_ctrl(struct kvm *kvm, struct vgic_its *its, u64 attr)
2655{
2656 const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2657 int ret = 0;
2658
2659 if (attr == KVM_DEV_ARM_VGIC_CTRL_INIT)
2660 return 0;
2661
2662 mutex_lock(&kvm->lock);
2663 mutex_lock(&its->its_lock);
2664
2665 if (!lock_all_vcpus(kvm)) {
2666 mutex_unlock(&its->its_lock);
2667 mutex_unlock(&kvm->lock);
2668 return -EBUSY;
2669 }
2670
2671 switch (attr) {
2672 case KVM_DEV_ARM_ITS_CTRL_RESET:
2673 vgic_its_reset(kvm, its);
2674 break;
2675 case KVM_DEV_ARM_ITS_SAVE_TABLES:
2676 ret = abi->save_tables(its);
2677 break;
2678 case KVM_DEV_ARM_ITS_RESTORE_TABLES:
2679 ret = abi->restore_tables(its);
2680 break;
2681 }
2682
2683 unlock_all_vcpus(kvm);
2684 mutex_unlock(&its->its_lock);
2685 mutex_unlock(&kvm->lock);
2686 return ret;
2687}
2688
2689static int vgic_its_set_attr(struct kvm_device *dev,
2690 struct kvm_device_attr *attr)
2691{
2692 struct vgic_its *its = dev->private;
2693 int ret;
2694
2695 switch (attr->group) {
2696 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2697 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2698 unsigned long type = (unsigned long)attr->attr;
2699 u64 addr;
2700
2701 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2702 return -ENODEV;
2703
2704 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2705 return -EFAULT;
2706
2707 ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
2708 addr, SZ_64K);
2709 if (ret)
2710 return ret;
2711
2712 return vgic_register_its_iodev(dev->kvm, its, addr);
2713 }
2714 case KVM_DEV_ARM_VGIC_GRP_CTRL:
2715 return vgic_its_ctrl(dev->kvm, its, attr->attr);
2716 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2717 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2718 u64 reg;
2719
2720 if (get_user(reg, uaddr))
2721 return -EFAULT;
2722
2723 return vgic_its_attr_regs_access(dev, attr, ®, true);
2724 }
2725 }
2726 return -ENXIO;
2727}
2728
2729static int vgic_its_get_attr(struct kvm_device *dev,
2730 struct kvm_device_attr *attr)
2731{
2732 switch (attr->group) {
2733 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2734 struct vgic_its *its = dev->private;
2735 u64 addr = its->vgic_its_base;
2736 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2737 unsigned long type = (unsigned long)attr->attr;
2738
2739 if (type != KVM_VGIC_ITS_ADDR_TYPE)
2740 return -ENODEV;
2741
2742 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2743 return -EFAULT;
2744 break;
2745 }
2746 case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
2747 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2748 u64 reg;
2749 int ret;
2750
2751 ret = vgic_its_attr_regs_access(dev, attr, ®, false);
2752 if (ret)
2753 return ret;
2754 return put_user(reg, uaddr);
2755 }
2756 default:
2757 return -ENXIO;
2758 }
2759
2760 return 0;
2761}
2762
2763static struct kvm_device_ops kvm_arm_vgic_its_ops = {
2764 .name = "kvm-arm-vgic-its",
2765 .create = vgic_its_create,
2766 .destroy = vgic_its_destroy,
2767 .set_attr = vgic_its_set_attr,
2768 .get_attr = vgic_its_get_attr,
2769 .has_attr = vgic_its_has_attr,
2770};
2771
2772int kvm_vgic_register_its_device(void)
2773{
2774 return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
2775 KVM_DEV_TYPE_ARM_VGIC_ITS);
2776}
2777