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10#include <linux/compiler.h>
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <linux/dma-mapping.h>
14#include <asm/cacheflush.h>
15#include <asm/glue-df.h>
16#include <asm/glue-pf.h>
17#include <asm/mach/arch.h>
18#include <asm/thread_info.h>
19#include <asm/memory.h>
20#include <asm/mpu.h>
21#include <asm/procinfo.h>
22#include <asm/suspend.h>
23#include <asm/vdso_datapage.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <linux/kbuild.h>
26#include "signal.h"
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30
31#if defined(__APCS_26__)
32#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
33#endif
34
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37
38
39#if defined(GCC_VERSION) && GCC_VERSION >= 40800 && GCC_VERSION < 40803
40#error Your compiler is too buggy; it is known to miscompile kernels
41#error and result in filesystem corruption and oopses.
42#endif
43
44int main(void)
45{
46 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
47#ifdef CONFIG_STACKPROTECTOR
48 DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
49#endif
50 BLANK();
51 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
52 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
53 DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
54 DEFINE(TI_TASK, offsetof(struct thread_info, task));
55 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
56 DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain));
57 DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context));
58 DEFINE(TI_USED_CP, offsetof(struct thread_info, used_cp));
59 DEFINE(TI_TP_VALUE, offsetof(struct thread_info, tp_value));
60 DEFINE(TI_FPSTATE, offsetof(struct thread_info, fpstate));
61#ifdef CONFIG_VFP
62 DEFINE(TI_VFPSTATE, offsetof(struct thread_info, vfpstate));
63#ifdef CONFIG_SMP
64 DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
65#endif
66#endif
67#ifdef CONFIG_ARM_THUMBEE
68 DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
69#endif
70#ifdef CONFIG_IWMMXT
71 DEFINE(TI_IWMMXT_STATE, offsetof(struct thread_info, fpstate.iwmmxt));
72#endif
73#ifdef CONFIG_CRUNCH
74 DEFINE(TI_CRUNCH_STATE, offsetof(struct thread_info, crunchstate));
75#endif
76#ifdef CONFIG_STACKPROTECTOR_PER_TASK
77 DEFINE(TI_STACK_CANARY, offsetof(struct thread_info, stack_canary));
78#endif
79 DEFINE(THREAD_SZ_ORDER, THREAD_SIZE_ORDER);
80 BLANK();
81 DEFINE(S_R0, offsetof(struct pt_regs, ARM_r0));
82 DEFINE(S_R1, offsetof(struct pt_regs, ARM_r1));
83 DEFINE(S_R2, offsetof(struct pt_regs, ARM_r2));
84 DEFINE(S_R3, offsetof(struct pt_regs, ARM_r3));
85 DEFINE(S_R4, offsetof(struct pt_regs, ARM_r4));
86 DEFINE(S_R5, offsetof(struct pt_regs, ARM_r5));
87 DEFINE(S_R6, offsetof(struct pt_regs, ARM_r6));
88 DEFINE(S_R7, offsetof(struct pt_regs, ARM_r7));
89 DEFINE(S_R8, offsetof(struct pt_regs, ARM_r8));
90 DEFINE(S_R9, offsetof(struct pt_regs, ARM_r9));
91 DEFINE(S_R10, offsetof(struct pt_regs, ARM_r10));
92 DEFINE(S_FP, offsetof(struct pt_regs, ARM_fp));
93 DEFINE(S_IP, offsetof(struct pt_regs, ARM_ip));
94 DEFINE(S_SP, offsetof(struct pt_regs, ARM_sp));
95 DEFINE(S_LR, offsetof(struct pt_regs, ARM_lr));
96 DEFINE(S_PC, offsetof(struct pt_regs, ARM_pc));
97 DEFINE(S_PSR, offsetof(struct pt_regs, ARM_cpsr));
98 DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0));
99 DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
100 DEFINE(SVC_DACR, offsetof(struct svc_pt_regs, dacr));
101 DEFINE(SVC_ADDR_LIMIT, offsetof(struct svc_pt_regs, addr_limit));
102 DEFINE(SVC_REGS_SIZE, sizeof(struct svc_pt_regs));
103 BLANK();
104 DEFINE(SIGFRAME_RC3_OFFSET, offsetof(struct sigframe, retcode[3]));
105 DEFINE(RT_SIGFRAME_RC3_OFFSET, offsetof(struct rt_sigframe, sig.retcode[3]));
106 BLANK();
107#ifdef CONFIG_CACHE_L2X0
108 DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
109 DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
110 DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency));
111 DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency));
112 DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start));
113 DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end));
114 DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl));
115 DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl));
116 BLANK();
117#endif
118#ifdef CONFIG_CPU_HAS_ASID
119 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
120 BLANK();
121#endif
122 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
123 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
124 BLANK();
125 DEFINE(VM_EXEC, VM_EXEC);
126 BLANK();
127 DEFINE(PAGE_SZ, PAGE_SIZE);
128 BLANK();
129 DEFINE(SYS_ERROR0, 0x9f0000);
130 BLANK();
131 DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc));
132 DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr));
133 DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name));
134 BLANK();
135 DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
136 DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
137 DEFINE(PROCINFO_MM_MMUFLAGS, offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
138 DEFINE(PROCINFO_IO_MMUFLAGS, offsetof(struct proc_info_list, __cpu_io_mmu_flags));
139 BLANK();
140#ifdef MULTI_DABORT
141 DEFINE(PROCESSOR_DABT_FUNC, offsetof(struct processor, _data_abort));
142#endif
143#ifdef MULTI_PABORT
144 DEFINE(PROCESSOR_PABT_FUNC, offsetof(struct processor, _prefetch_abort));
145#endif
146#ifdef MULTI_CPU
147 DEFINE(CPU_SLEEP_SIZE, offsetof(struct processor, suspend_size));
148 DEFINE(CPU_DO_SUSPEND, offsetof(struct processor, do_suspend));
149 DEFINE(CPU_DO_RESUME, offsetof(struct processor, do_resume));
150#endif
151#ifdef MULTI_CACHE
152 DEFINE(CACHE_FLUSH_KERN_ALL, offsetof(struct cpu_cache_fns, flush_kern_all));
153#endif
154#ifdef CONFIG_ARM_CPU_SUSPEND
155 DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
156 DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
157 DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));
158#endif
159 BLANK();
160 DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
161 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
162 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
163 BLANK();
164 DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
165 DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
166 BLANK();
167#ifdef CONFIG_VDSO
168 DEFINE(VDSO_DATA_SIZE, sizeof(union vdso_data_store));
169#endif
170 BLANK();
171#ifdef CONFIG_ARM_MPU
172 DEFINE(MPU_RNG_INFO_RNGS, offsetof(struct mpu_rgn_info, rgns));
173 DEFINE(MPU_RNG_INFO_USED, offsetof(struct mpu_rgn_info, used));
174
175 DEFINE(MPU_RNG_SIZE, sizeof(struct mpu_rgn));
176 DEFINE(MPU_RGN_DRBAR, offsetof(struct mpu_rgn, drbar));
177 DEFINE(MPU_RGN_DRSR, offsetof(struct mpu_rgn, drsr));
178 DEFINE(MPU_RGN_DRACR, offsetof(struct mpu_rgn, dracr));
179 DEFINE(MPU_RGN_PRBAR, offsetof(struct mpu_rgn, prbar));
180 DEFINE(MPU_RGN_PRLAR, offsetof(struct mpu_rgn, prlar));
181#endif
182 return 0;
183}
184
