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10
11#undef DEBUG
12
13#include <linux/sched.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/stddef.h>
17#include <linux/export.h>
18#include <linux/unistd.h>
19#include <linux/user.h>
20#include <linux/reboot.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/irq.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26#include <linux/console.h>
27#include <linux/mutex.h>
28#include <linux/memory_hotplug.h>
29#include <linux/of_platform.h>
30
31#include <asm/mmu.h>
32#include <asm/processor.h>
33#include <asm/io.h>
34#include <asm/pgtable.h>
35#include <asm/prom.h>
36#include <asm/rtas.h>
37#include <asm/pci-bridge.h>
38#include <asm/iommu.h>
39#include <asm/dma.h>
40#include <asm/machdep.h>
41#include <asm/time.h>
42#include <asm/nvram.h>
43#include <asm/cputable.h>
44#include <asm/ppc-pci.h>
45#include <asm/irq.h>
46#include <asm/spu.h>
47#include <asm/spu_priv1.h>
48#include <asm/udbg.h>
49#include <asm/mpic.h>
50#include <asm/cell-regs.h>
51#include <asm/io-workarounds.h>
52
53#include "cell.h"
54#include "interrupt.h"
55#include "pervasive.h"
56#include "ras.h"
57
58#ifdef DEBUG
59#define DBG(fmt...) udbg_printf(fmt)
60#else
61#define DBG(fmt...)
62#endif
63
64static void cell_show_cpuinfo(struct seq_file *m)
65{
66 struct device_node *root;
67 const char *model = "";
68
69 root = of_find_node_by_path("/");
70 if (root)
71 model = of_get_property(root, "model", NULL);
72 seq_printf(m, "machine\t\t: CHRP %s\n", model);
73 of_node_put(root);
74}
75
76static void cell_progress(char *s, unsigned short hex)
77{
78 printk("*** %04x : %s\n", hex, s ? s : "");
79}
80
81static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
82{
83 struct pci_controller *hose;
84 const char *s;
85 int i;
86
87 if (!machine_is(cell))
88 return;
89
90
91 if (dev->bus->self != NULL || dev->devfn != 0)
92 return;
93
94 hose = pci_bus_to_host(dev->bus);
95 if (hose == NULL)
96 return;
97
98
99 if (!of_device_is_compatible(hose->dn, "pciex"))
100 return;
101
102
103 s = of_get_property(hose->dn, "model", NULL);
104 if (!s || strcmp(s, "Axon") != 0)
105 return;
106
107 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
108 dev->resource[i].start = dev->resource[i].end = 0;
109 dev->resource[i].flags = 0;
110 }
111
112 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
113 pci_name(dev));
114}
115DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
116
117static int cell_setup_phb(struct pci_controller *phb)
118{
119 const char *model;
120 struct device_node *np;
121
122 int rc = rtas_setup_phb(phb);
123 if (rc)
124 return rc;
125
126 phb->controller_ops = cell_pci_controller_ops;
127
128 np = phb->dn;
129 model = of_get_property(np, "model", NULL);
130 if (model == NULL || !of_node_name_eq(np, "pci"))
131 return 0;
132
133
134 if (strcmp(model, "Spider"))
135 return 0;
136
137 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
138 (void *)SPIDER_PCI_REG_BASE);
139 return 0;
140}
141
142static const struct of_device_id cell_bus_ids[] __initconst = {
143 { .type = "soc", },
144 { .compatible = "soc", },
145 { .type = "spider", },
146 { .type = "axon", },
147 { .type = "plb5", },
148 { .type = "plb4", },
149 { .type = "opb", },
150 { .type = "ebc", },
151 {},
152};
153
154static int __init cell_publish_devices(void)
155{
156 struct device_node *root = of_find_node_by_path("/");
157 struct device_node *np;
158 int node;
159
160
161 of_platform_bus_probe(NULL, cell_bus_ids, NULL);
162
163
164
165
166 for_each_child_of_node(root, np) {
167 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
168 continue;
169 of_platform_device_create(np, NULL, NULL);
170 }
171
172
173
174
175 for_each_online_node(node) {
176 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
177 continue;
178 platform_device_register_simple("cbe-mic", node, NULL, 0);
179 }
180
181 return 0;
182}
183machine_subsys_initcall(cell, cell_publish_devices);
184
185static void __init mpic_init_IRQ(void)
186{
187 struct device_node *dn;
188 struct mpic *mpic;
189
190 for_each_node_by_name(dn, "interrupt-controller") {
191 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
192 continue;
193
194
195
196
197 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
198 0, 0, " MPIC ");
199 if (mpic == NULL)
200 continue;
201 mpic_init(mpic);
202 }
203}
204
205
206static void __init cell_init_irq(void)
207{
208 iic_init_IRQ();
209 spider_init_IRQ();
210 mpic_init_IRQ();
211}
212
213static void __init cell_set_dabrx(void)
214{
215 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
216}
217
218static void __init cell_setup_arch(void)
219{
220#ifdef CONFIG_SPU_BASE
221 spu_priv1_ops = &spu_priv1_mmio_ops;
222 spu_management_ops = &spu_management_of_ops;
223#endif
224
225 cbe_regs_init();
226
227 cell_set_dabrx();
228
229#ifdef CONFIG_CBE_RAS
230 cbe_ras_init();
231#endif
232
233#ifdef CONFIG_SMP
234 smp_init_cell();
235#endif
236
237 loops_per_jiffy = 50000000;
238
239
240 init_pci_config_tokens();
241
242 cbe_pervasive_init();
243
244 mmio_nvram_init();
245}
246
247static int __init cell_probe(void)
248{
249 if (!of_machine_is_compatible("IBM,CBEA") &&
250 !of_machine_is_compatible("IBM,CPBW-1.0"))
251 return 0;
252
253 pm_power_off = rtas_power_off;
254
255 return 1;
256}
257
258define_machine(cell) {
259 .name = "Cell",
260 .probe = cell_probe,
261 .setup_arch = cell_setup_arch,
262 .show_cpuinfo = cell_show_cpuinfo,
263 .restart = rtas_restart,
264 .halt = rtas_halt,
265 .get_boot_time = rtas_get_boot_time,
266 .get_rtc_time = rtas_get_rtc_time,
267 .set_rtc_time = rtas_set_rtc_time,
268 .calibrate_decr = generic_calibrate_decr,
269 .progress = cell_progress,
270 .init_IRQ = cell_init_irq,
271 .pci_setup_phb = cell_setup_phb,
272};
273
274struct pci_controller_ops cell_pci_controller_ops;
275
