1
2
3
4
5
6
7
8
9
10
11
12#ifndef __ASM_S390_PROCESSOR_H
13#define __ASM_S390_PROCESSOR_H
14
15#include <linux/bits.h>
16
17#define CIF_MCCK_PENDING 0
18#define CIF_ASCE_PRIMARY 1
19#define CIF_ASCE_SECONDARY 2
20#define CIF_NOHZ_DELAY 3
21#define CIF_FPU 4
22#define CIF_IGNORE_IRQ 5
23#define CIF_ENABLED_WAIT 6
24#define CIF_MCCK_GUEST 7
25#define CIF_DEDICATED_CPU 8
26
27#define _CIF_MCCK_PENDING BIT(CIF_MCCK_PENDING)
28#define _CIF_ASCE_PRIMARY BIT(CIF_ASCE_PRIMARY)
29#define _CIF_ASCE_SECONDARY BIT(CIF_ASCE_SECONDARY)
30#define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
31#define _CIF_FPU BIT(CIF_FPU)
32#define _CIF_IGNORE_IRQ BIT(CIF_IGNORE_IRQ)
33#define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
34#define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
35#define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
36
37#ifndef __ASSEMBLY__
38
39#include <linux/cpumask.h>
40#include <linux/linkage.h>
41#include <linux/irqflags.h>
42#include <asm/cpu.h>
43#include <asm/page.h>
44#include <asm/ptrace.h>
45#include <asm/setup.h>
46#include <asm/runtime_instr.h>
47#include <asm/fpu/types.h>
48#include <asm/fpu/internal.h>
49
50static inline void set_cpu_flag(int flag)
51{
52 S390_lowcore.cpu_flags |= (1UL << flag);
53}
54
55static inline void clear_cpu_flag(int flag)
56{
57 S390_lowcore.cpu_flags &= ~(1UL << flag);
58}
59
60static inline int test_cpu_flag(int flag)
61{
62 return !!(S390_lowcore.cpu_flags & (1UL << flag));
63}
64
65
66
67
68
69static inline int test_cpu_flag_of(int flag, int cpu)
70{
71 struct lowcore *lc = lowcore_ptr[cpu];
72 return !!(lc->cpu_flags & (1UL << flag));
73}
74
75#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
76
77static inline void get_cpu_id(struct cpuid *ptr)
78{
79 asm volatile("stidp %0" : "=Q" (*ptr));
80}
81
82void s390_adjust_jiffies(void);
83void s390_update_cpu_mhz(void);
84void cpu_detect_mhz_feature(void);
85
86extern const struct seq_operations cpuinfo_op;
87extern void execve_tail(void);
88extern void __bpon(void);
89
90
91
92
93
94#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \
95 _REGION3_SIZE : TASK_SIZE_MAX)
96#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
97 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
98#define TASK_SIZE TASK_SIZE_OF(current)
99#define TASK_SIZE_MAX (-PAGE_SIZE)
100
101#define STACK_TOP (test_thread_flag(TIF_31BIT) ? \
102 _REGION3_SIZE : _REGION2_SIZE)
103#define STACK_TOP_MAX _REGION2_SIZE
104
105#define HAVE_ARCH_PICK_MMAP_LAYOUT
106
107typedef unsigned int mm_segment_t;
108
109
110
111
112struct thread_struct {
113 unsigned int acrs[NUM_ACRS];
114 unsigned long ksp;
115 unsigned long user_timer;
116 unsigned long guest_timer;
117 unsigned long system_timer;
118 unsigned long hardirq_timer;
119 unsigned long softirq_timer;
120 unsigned long sys_call_table;
121 mm_segment_t mm_segment;
122 unsigned long gmap_addr;
123 unsigned int gmap_write_flag;
124 unsigned int gmap_int_code;
125 unsigned int gmap_pfault;
126
127 struct per_regs per_user;
128 struct per_event per_event;
129 unsigned long per_flags;
130 unsigned int system_call;
131 unsigned long last_break;
132
133 unsigned long pfault_wait;
134 struct list_head list;
135
136 struct runtime_instr_cb *ri_cb;
137 struct gs_cb *gs_cb;
138 struct gs_cb *gs_bc_cb;
139 unsigned char trap_tdb[256];
140
141
142
143
144 struct fpu fpu;
145};
146
147
148#define PER_FLAG_NO_TE 1UL
149
150#define PER_FLAG_TE_ABORT_RAND 2UL
151
152
153
154
155#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
156
157typedef struct thread_struct thread_struct;
158
159#define ARCH_MIN_TASKALIGN 8
160
161#define INIT_THREAD { \
162 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
163 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
164 .last_break = 1, \
165}
166
167
168
169
170#define start_thread(regs, new_psw, new_stackp) do { \
171 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
172 regs->psw.addr = new_psw; \
173 regs->gprs[15] = new_stackp; \
174 execve_tail(); \
175} while (0)
176
177#define start_thread31(regs, new_psw, new_stackp) do { \
178 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
179 regs->psw.addr = new_psw; \
180 regs->gprs[15] = new_stackp; \
181 execve_tail(); \
182} while (0)
183
184
185struct task_struct;
186struct mm_struct;
187struct seq_file;
188struct pt_regs;
189
190void show_registers(struct pt_regs *regs);
191void show_cacheinfo(struct seq_file *m);
192
193
194static inline void release_thread(struct task_struct *tsk) { }
195
196
197void guarded_storage_release(struct task_struct *tsk);
198
199unsigned long get_wchan(struct task_struct *p);
200#define task_pt_regs(tsk) ((struct pt_regs *) \
201 (task_stack_page(tsk) + THREAD_SIZE) - 1)
202#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
203#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
204
205
206#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
207
208static __always_inline unsigned long current_stack_pointer(void)
209{
210 unsigned long sp;
211
212 asm volatile("la %0,0(15)" : "=a" (sp));
213 return sp;
214}
215
216static __no_kasan_or_inline unsigned short stap(void)
217{
218 unsigned short cpu_address;
219
220 asm volatile("stap %0" : "=Q" (cpu_address));
221 return cpu_address;
222}
223
224#define cpu_relax() barrier()
225
226#define ECAG_CACHE_ATTRIBUTE 0
227#define ECAG_CPU_ATTRIBUTE 1
228
229static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
230{
231 unsigned long val;
232
233 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)"
234 : "=d" (val) : "a" (asi << 8 | parm));
235 return val;
236}
237
238static inline void psw_set_key(unsigned int key)
239{
240 asm volatile("spka 0(%0)" : : "d" (key));
241}
242
243
244
245
246static inline void __load_psw(psw_t psw)
247{
248 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
249}
250
251
252
253
254
255static __no_kasan_or_inline void __load_psw_mask(unsigned long mask)
256{
257 unsigned long addr;
258 psw_t psw;
259
260 psw.mask = mask;
261
262 asm volatile(
263 " larl %0,1f\n"
264 " stg %0,%1\n"
265 " lpswe %2\n"
266 "1:"
267 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
268}
269
270
271
272
273static inline unsigned long __extract_psw(void)
274{
275 unsigned int reg1, reg2;
276
277 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
278 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
279}
280
281static inline void local_mcck_enable(void)
282{
283 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
284}
285
286static inline void local_mcck_disable(void)
287{
288 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
289}
290
291
292
293
294static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
295{
296 unsigned long mask;
297
298 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
299 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
300 (1UL << 24) - 1;
301 return (psw.addr - ilc) & mask;
302}
303
304
305
306
307void enabled_wait(void);
308
309
310
311
312static __always_inline void __noreturn disabled_wait(void)
313{
314 psw_t psw;
315
316 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
317 psw.addr = _THIS_IP_;
318 __load_psw(psw);
319 while (1);
320}
321
322
323
324
325
326extern void s390_base_pgm_handler(void);
327extern void s390_base_ext_handler(void);
328
329extern void (*s390_base_pgm_handler_fn)(void);
330extern void (*s390_base_ext_handler_fn)(void);
331
332#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
333
334extern int memcpy_real(void *, void *, size_t);
335extern void memcpy_absolute(void *, void *, size_t);
336
337#define mem_assign_absolute(dest, val) do { \
338 __typeof__(dest) __tmp = (val); \
339 \
340 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
341 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
342} while (0)
343
344extern int s390_isolate_bp(void);
345extern int s390_isolate_bp_guest(void);
346
347#endif
348
349#endif
350