1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * include/asm/sunbpp.h 4 */ 5 6#ifndef _ASM_SPARC_SUNBPP_H 7#define _ASM_SPARC_SUNBPP_H 8 9struct bpp_regs { 10 /* DMA registers */ 11 __volatile__ __u32 p_csr; /* DMA Control/Status Register */ 12 __volatile__ __u32 p_addr; /* Address Register */ 13 __volatile__ __u32 p_bcnt; /* Byte Count Register */ 14 __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ 15 /* Parallel Port registers */ 16 __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ 17 __volatile__ __u16 p_ocr; /* Operation Configuration Register */ 18 __volatile__ __u8 p_dr; /* Parallel Data Register */ 19 __volatile__ __u8 p_tcr; /* Transfer Control Register */ 20 __volatile__ __u8 p_or; /* Output Register */ 21 __volatile__ __u8 p_ir; /* Input Register */ 22 __volatile__ __u16 p_icr; /* Interrupt Control Register */ 23}; 24 25/* P_HCR. Time is in increments of SBus clock. */ 26#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ 27#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ 28#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ 29 30/* P_OCR. */ 31#define P_OCR_MEM_CLR 0x8000 32#define P_OCR_DATA_SRC 0x4000 /* ) */ 33#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ 34#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ 35#define P_OCR_ACK_DSEL 0x0800 /* ) */ 36#define P_OCR_EN_DIAG 0x0400 37#define P_OCR_BUSY_OP 0x0200 /* Busy operation */ 38#define P_OCR_ACK_OP 0x0100 /* Ack operation */ 39#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ 40#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ 41#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ 42#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ 43 44/* P_TCR */ 45#define P_TCR_DIR 0x08 46#define P_TCR_BUSY 0x04 47#define P_TCR_ACK 0x02 48#define P_TCR_DS 0x01 /* Strobe */ 49 50/* P_OR */ 51#define P_OR_V3 0x20 /* ) */ 52#define P_OR_V2 0x10 /* ) on Zebra only */ 53#define P_OR_V1 0x08 /* ) */ 54#define P_OR_INIT 0x04 55#define P_OR_AFXN 0x02 /* Auto Feed */ 56#define P_OR_SLCT_IN 0x01 57 58/* P_IR */ 59#define P_IR_PE 0x04 60#define P_IR_SLCT 0x02 61#define P_IR_ERR 0x01 62 63/* P_ICR */ 64#define P_DS_IRQ 0x8000 /* RW1 */ 65#define P_ACK_IRQ 0x4000 /* RW1 */ 66#define P_BUSY_IRQ 0x2000 /* RW1 */ 67#define P_PE_IRQ 0x1000 /* RW1 */ 68#define P_SLCT_IRQ 0x0800 /* RW1 */ 69#define P_ERR_IRQ 0x0400 /* RW1 */ 70#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ 71#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ 72#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ 73#define P_BUSY_IRQ_EN 0x0040 /* RW */ 74#define P_PE_IRP 0x0020 /* RW 1= rising edge */ 75#define P_PE_IRQ_EN 0x0010 /* RW */ 76#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ 77#define P_SLCT_IRQ_EN 0x0004 /* RW */ 78#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ 79#define P_ERR_IRQ_EN 0x0001 /* RW */ 80 81#endif /* !(_ASM_SPARC_SUNBPP_H) */ 82