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8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/sys_soc.h>
13#include <linux/fsl/mc.h>
14
15#include "compat.h"
16#include "regs.h"
17#include "intern.h"
18#include "jr.h"
19#include "desc_constr.h"
20#include "ctrl.h"
21
22bool caam_dpaa2;
23EXPORT_SYMBOL(caam_dpaa2);
24
25#ifdef CONFIG_CAAM_QI
26#include "qi.h"
27#endif
28
29
30
31
32
33static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
34{
35 u32 *jump_cmd, op_flags;
36
37 init_job_desc(desc, 0);
38
39 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
40 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
41 OP_ALG_PR_ON;
42
43
44 append_operation(desc, op_flags);
45
46 if (!handle && do_sk) {
47
48
49
50
51
52 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
53 set_jump_tgt_here(desc, jump_cmd);
54
55
56
57
58
59 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
60
61
62 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
63 OP_ALG_AAI_RNG4_SK);
64 }
65
66 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
67}
68
69
70static void build_deinstantiation_desc(u32 *desc, int handle)
71{
72 init_job_desc(desc, 0);
73
74
75 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
76 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
77
78 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
79}
80
81
82
83
84
85
86
87
88
89
90
91static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
92 u32 *status)
93{
94 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
95 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
96 struct caam_deco __iomem *deco = ctrlpriv->deco;
97 unsigned int timeout = 100000;
98 u32 deco_dbg_reg, deco_state, flags;
99 int i;
100
101
102 if (ctrlpriv->virt_en == 1 ||
103
104
105
106
107 of_machine_is_compatible("fsl,imx8mq") ||
108 of_machine_is_compatible("fsl,imx8mm") ||
109 of_machine_is_compatible("fsl,imx8mn") ||
110 of_machine_is_compatible("fsl,imx8mp")) {
111 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
112
113 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
114 --timeout)
115 cpu_relax();
116
117 timeout = 100000;
118 }
119
120 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
121
122 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
123 --timeout)
124 cpu_relax();
125
126 if (!timeout) {
127 dev_err(ctrldev, "failed to acquire DECO 0\n");
128 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
129 return -ENODEV;
130 }
131
132 for (i = 0; i < desc_len(desc); i++)
133 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
134
135 flags = DECO_JQCR_WHL;
136
137
138
139
140 if (desc_len(desc) >= 4)
141 flags |= DECO_JQCR_FOUR;
142
143
144 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
145
146 timeout = 10000000;
147 do {
148 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
149
150 if (ctrlpriv->era < 10)
151 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
152 DESC_DBG_DECO_STAT_SHIFT;
153 else
154 deco_state = (rd_reg32(&deco->dbg_exec) &
155 DESC_DER_DECO_STAT_MASK) >>
156 DESC_DER_DECO_STAT_SHIFT;
157
158
159
160
161
162 if (deco_state == DECO_STAT_HOST_ERR)
163 break;
164
165 cpu_relax();
166 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
167
168 *status = rd_reg32(&deco->op_status_hi) &
169 DECO_OP_STATUS_HI_ERR_MASK;
170
171 if (ctrlpriv->virt_en == 1)
172 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
173
174
175 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
176
177 if (!timeout)
178 return -EAGAIN;
179
180 return 0;
181}
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
197{
198 u32 *desc, status;
199 int sh_idx, ret = 0;
200
201 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL | GFP_DMA);
202 if (!desc)
203 return -ENOMEM;
204
205 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
206
207
208
209
210
211 if ((1 << sh_idx) & state_handle_mask) {
212
213
214
215
216 build_deinstantiation_desc(desc, sh_idx);
217
218
219 ret = run_descriptor_deco0(ctrldev, desc, &status);
220
221 if (ret ||
222 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
223 dev_err(ctrldev,
224 "Failed to deinstantiate RNG4 SH%d\n",
225 sh_idx);
226 break;
227 }
228 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
229 }
230 }
231
232 kfree(desc);
233
234 return ret;
235}
236
237static void devm_deinstantiate_rng(void *data)
238{
239 struct device *ctrldev = data;
240 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
241
242
243
244
245
246 if (ctrlpriv->rng4_sh_init)
247 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
248}
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
270 int gen_sk)
271{
272 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
273 struct caam_ctrl __iomem *ctrl;
274 u32 *desc, status = 0, rdsta_val;
275 int ret = 0, sh_idx;
276
277 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
278 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL | GFP_DMA);
279 if (!desc)
280 return -ENOMEM;
281
282 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
283 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
284 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
285 const u32 rdsta_mask = rdsta_if | rdsta_pr;
286
287
288
289
290 if (rdsta_if & state_handle_mask) {
291 if (rdsta_pr & state_handle_mask)
292 continue;
293
294 dev_info(ctrldev,
295 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
296 sh_idx);
297
298 ret = deinstantiate_rng(ctrldev, rdsta_if);
299 if (ret)
300 break;
301 }
302
303
304 build_instantiation_desc(desc, sh_idx, gen_sk);
305
306
307 ret = run_descriptor_deco0(ctrldev, desc, &status);
308
309
310
311
312
313
314
315
316
317
318 if (ret)
319 break;
320
321 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
322 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
323 (rdsta_val & rdsta_mask) != rdsta_mask) {
324 ret = -EAGAIN;
325 break;
326 }
327
328 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
329
330 memset(desc, 0x00, CAAM_CMD_SZ * 7);
331 }
332
333 kfree(desc);
334
335 if (!ret)
336 ret = devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng,
337 ctrldev);
338
339 return ret;
340}
341
342
343
344
345
346
347
348static void kick_trng(struct platform_device *pdev, int ent_delay)
349{
350 struct device *ctrldev = &pdev->dev;
351 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
352 struct caam_ctrl __iomem *ctrl;
353 struct rng4tst __iomem *r4tst;
354 u32 val;
355
356 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
357 r4tst = &ctrl->r4tst[0];
358
359
360
361
362
363
364 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
365
366
367
368
369
370
371
372
373
374 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
375 >> RTSDCTL_ENT_DLY_SHIFT;
376 if (ent_delay <= val)
377 goto start_rng;
378
379 val = rd_reg32(&r4tst->rtsdctl);
380 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
381 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
382 wr_reg32(&r4tst->rtsdctl, val);
383
384 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
385
386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
387
388 val = rd_reg32(&r4tst->rtmctl);
389start_rng:
390
391
392
393
394 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
395 RTMCTL_SAMP_MODE_RAW_ES_SC);
396}
397
398static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
399{
400 static const struct {
401 u16 ip_id;
402 u8 maj_rev;
403 u8 era;
404 } id[] = {
405 {0x0A10, 1, 1},
406 {0x0A10, 2, 2},
407 {0x0A12, 1, 3},
408 {0x0A14, 1, 3},
409 {0x0A14, 2, 4},
410 {0x0A16, 1, 4},
411 {0x0A10, 3, 4},
412 {0x0A11, 1, 4},
413 {0x0A18, 1, 4},
414 {0x0A11, 2, 5},
415 {0x0A12, 2, 5},
416 {0x0A13, 1, 5},
417 {0x0A1C, 1, 5}
418 };
419 u32 ccbvid, id_ms;
420 u8 maj_rev, era;
421 u16 ip_id;
422 int i;
423
424 ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
425 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
426 if (era)
427 return era;
428
429 id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
430 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
431 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
432
433 for (i = 0; i < ARRAY_SIZE(id); i++)
434 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
435 return id[i].era;
436
437 return -ENOTSUPP;
438}
439
440
441
442
443
444
445
446
447static int caam_get_era(struct caam_ctrl __iomem *ctrl)
448{
449 struct device_node *caam_node;
450 int ret;
451 u32 prop;
452
453 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
454 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
455 of_node_put(caam_node);
456
457 if (!ret)
458 return prop;
459 else
460 return caam_get_era_from_hw(ctrl);
461}
462
463
464
465
466
467
468
469
470
471
472static void handle_imx6_err005766(u32 *mcr)
473{
474 if (of_machine_is_compatible("fsl,imx6q") ||
475 of_machine_is_compatible("fsl,imx6dl") ||
476 of_machine_is_compatible("fsl,imx6qp"))
477 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
478 1 << MCFGR_AXIPIPE_SHIFT);
479}
480
481static const struct of_device_id caam_match[] = {
482 {
483 .compatible = "fsl,sec-v4.0",
484 },
485 {
486 .compatible = "fsl,sec4.0",
487 },
488 {},
489};
490MODULE_DEVICE_TABLE(of, caam_match);
491
492struct caam_imx_data {
493 const struct clk_bulk_data *clks;
494 int num_clks;
495};
496
497static const struct clk_bulk_data caam_imx6_clks[] = {
498 { .id = "ipg" },
499 { .id = "mem" },
500 { .id = "aclk" },
501 { .id = "emi_slow" },
502};
503
504static const struct caam_imx_data caam_imx6_data = {
505 .clks = caam_imx6_clks,
506 .num_clks = ARRAY_SIZE(caam_imx6_clks),
507};
508
509static const struct clk_bulk_data caam_imx7_clks[] = {
510 { .id = "ipg" },
511 { .id = "aclk" },
512};
513
514static const struct caam_imx_data caam_imx7_data = {
515 .clks = caam_imx7_clks,
516 .num_clks = ARRAY_SIZE(caam_imx7_clks),
517};
518
519static const struct clk_bulk_data caam_imx6ul_clks[] = {
520 { .id = "ipg" },
521 { .id = "mem" },
522 { .id = "aclk" },
523};
524
525static const struct caam_imx_data caam_imx6ul_data = {
526 .clks = caam_imx6ul_clks,
527 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
528};
529
530static const struct soc_device_attribute caam_imx_soc_table[] = {
531 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
532 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
533 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
534 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
535 { .family = "Freescale i.MX" },
536 { }
537};
538
539static void disable_clocks(void *data)
540{
541 struct caam_drv_private *ctrlpriv = data;
542
543 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
544}
545
546static int init_clocks(struct device *dev, const struct caam_imx_data *data)
547{
548 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
549 int ret;
550
551 ctrlpriv->num_clks = data->num_clks;
552 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
553 data->num_clks * sizeof(data->clks[0]),
554 GFP_KERNEL);
555 if (!ctrlpriv->clks)
556 return -ENOMEM;
557
558 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
559 if (ret) {
560 dev_err(dev,
561 "Failed to request all necessary clocks\n");
562 return ret;
563 }
564
565 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
566 if (ret) {
567 dev_err(dev,
568 "Failed to prepare/enable all necessary clocks\n");
569 return ret;
570 }
571
572 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
573}
574
575#ifdef CONFIG_DEBUG_FS
576static void caam_remove_debugfs(void *root)
577{
578 debugfs_remove_recursive(root);
579}
580#endif
581
582#ifdef CONFIG_FSL_MC_BUS
583static bool check_version(struct fsl_mc_version *mc_version, u32 major,
584 u32 minor, u32 revision)
585{
586 if (mc_version->major > major)
587 return true;
588
589 if (mc_version->major == major) {
590 if (mc_version->minor > minor)
591 return true;
592
593 if (mc_version->minor == minor &&
594 mc_version->revision > revision)
595 return true;
596 }
597
598 return false;
599}
600#endif
601
602
603static int caam_probe(struct platform_device *pdev)
604{
605 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
606 u64 caam_id;
607 const struct soc_device_attribute *imx_soc_match;
608 struct device *dev;
609 struct device_node *nprop, *np;
610 struct caam_ctrl __iomem *ctrl;
611 struct caam_drv_private *ctrlpriv;
612#ifdef CONFIG_DEBUG_FS
613 struct caam_perfmon *perfmon;
614 struct dentry *dfs_root;
615#endif
616 u32 scfgr, comp_params;
617 u8 rng_vid;
618 int pg_size;
619 int BLOCK_OFFSET = 0;
620 bool pr_support = false;
621
622 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
623 if (!ctrlpriv)
624 return -ENOMEM;
625
626 dev = &pdev->dev;
627 dev_set_drvdata(dev, ctrlpriv);
628 nprop = pdev->dev.of_node;
629
630 imx_soc_match = soc_device_match(caam_imx_soc_table);
631 caam_imx = (bool)imx_soc_match;
632
633 if (imx_soc_match) {
634 if (!imx_soc_match->data) {
635 dev_err(dev, "No clock data provided for i.MX SoC");
636 return -EINVAL;
637 }
638
639 ret = init_clocks(dev, imx_soc_match->data);
640 if (ret)
641 return ret;
642 }
643
644
645
646
647 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
648 ret = PTR_ERR_OR_ZERO(ctrl);
649 if (ret) {
650 dev_err(dev, "caam: of_iomap() failed\n");
651 return ret;
652 }
653
654 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
655 (CSTA_PLEND | CSTA_ALT_PLEND));
656 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
657 if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
658 caam_ptr_sz = sizeof(u64);
659 else
660 caam_ptr_sz = sizeof(u32);
661 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
662 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
663
664#ifdef CONFIG_CAAM_QI
665
666 if (ctrlpriv->qi_present && !caam_dpaa2) {
667 ret = qman_is_probed();
668 if (!ret) {
669 return -EPROBE_DEFER;
670 } else if (ret < 0) {
671 dev_err(dev, "failing probe due to qman probe error\n");
672 return -ENODEV;
673 }
674
675 ret = qman_portals_probed();
676 if (!ret) {
677 return -EPROBE_DEFER;
678 } else if (ret < 0) {
679 dev_err(dev, "failing probe due to qman portals probe error\n");
680 return -ENODEV;
681 }
682 }
683#endif
684
685
686
687
688 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
689 if (pg_size == 0)
690 BLOCK_OFFSET = PG_SIZE_4K;
691 else
692 BLOCK_OFFSET = PG_SIZE_64K;
693
694 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
695 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
696 ((__force uint8_t *)ctrl +
697 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
698 );
699 ctrlpriv->deco = (struct caam_deco __iomem __force *)
700 ((__force uint8_t *)ctrl +
701 BLOCK_OFFSET * DECO_BLOCK_NUMBER
702 );
703
704
705 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
706 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
707 ctrlpriv->mc_en = !!np;
708 of_node_put(np);
709
710#ifdef CONFIG_FSL_MC_BUS
711 if (ctrlpriv->mc_en) {
712 struct fsl_mc_version *mc_version;
713
714 mc_version = fsl_mc_get_version();
715 if (mc_version)
716 pr_support = check_version(mc_version, 10, 20, 0);
717 else
718 return -EPROBE_DEFER;
719 }
720#endif
721
722
723
724
725
726
727
728 if (!ctrlpriv->mc_en)
729 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
730 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
731 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
732
733 handle_imx6_err005766(&ctrl->mcr);
734
735
736
737
738
739 scfgr = rd_reg32(&ctrl->scfgr);
740
741 ctrlpriv->virt_en = 0;
742 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
743
744
745
746 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
747 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
748 (scfgr & SCFGR_VIRT_EN)))
749 ctrlpriv->virt_en = 1;
750 } else {
751
752 if (comp_params & CTPR_MS_VIRT_EN_POR)
753 ctrlpriv->virt_en = 1;
754 }
755
756 if (ctrlpriv->virt_en == 1)
757 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
758 JRSTART_JR1_START | JRSTART_JR2_START |
759 JRSTART_JR3_START);
760
761 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
762 if (ret) {
763 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
764 return ret;
765 }
766
767 ctrlpriv->era = caam_get_era(ctrl);
768 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
769
770#ifdef CONFIG_DEBUG_FS
771
772
773
774
775
776 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
777
778 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
779 ret = devm_add_action_or_reset(dev, caam_remove_debugfs, dfs_root);
780 if (ret)
781 return ret;
782
783 ctrlpriv->ctl = debugfs_create_dir("ctl", dfs_root);
784#endif
785
786
787 if (ctrlpriv->qi_present && !caam_dpaa2) {
788 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
789 ((__force uint8_t *)ctrl +
790 BLOCK_OFFSET * QI_BLOCK_NUMBER
791 );
792
793 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
794
795
796#ifdef CONFIG_CAAM_QI
797 ret = caam_qi_init(pdev);
798 if (ret)
799 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
800#endif
801 }
802
803 ring = 0;
804 for_each_available_child_of_node(nprop, np)
805 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
806 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
807 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
808 ((__force uint8_t *)ctrl +
809 (ring + JR_BLOCK_NUMBER) *
810 BLOCK_OFFSET
811 );
812 ctrlpriv->total_jobrs++;
813 ring++;
814 }
815
816
817 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
818 dev_err(dev, "no queues configured, terminating\n");
819 return -ENOMEM;
820 }
821
822 if (ctrlpriv->era < 10)
823 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
824 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
825 else
826 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
827 CHA_VER_VID_SHIFT;
828
829
830
831
832
833
834 if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) {
835 ctrlpriv->rng4_sh_init =
836 rd_reg32(&ctrl->r4tst[0].rdsta);
837
838
839
840
841
842
843 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
844 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
845 do {
846 int inst_handles =
847 rd_reg32(&ctrl->r4tst[0].rdsta) &
848 RDSTA_MASK;
849
850
851
852
853
854
855
856
857 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
858 dev_info(dev,
859 "Entropy delay = %u\n",
860 ent_delay);
861 kick_trng(pdev, ent_delay);
862 ent_delay += 400;
863 }
864
865
866
867
868
869
870
871 ret = instantiate_rng(dev, inst_handles,
872 gen_sk);
873 if (ret == -EAGAIN)
874
875
876
877
878 cpu_relax();
879 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
880 if (ret) {
881 dev_err(dev, "failed to instantiate RNG");
882 return ret;
883 }
884
885
886
887
888 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
889
890
891 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
892 }
893
894
895
896 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
897 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
898
899
900 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
901 ctrlpriv->era);
902 dev_info(dev, "job rings = %d, qi = %d\n",
903 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
904
905#ifdef CONFIG_DEBUG_FS
906 debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
907 ctrlpriv->ctl, &perfmon->req_dequeued,
908 &caam_fops_u64_ro);
909 debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
910 ctrlpriv->ctl, &perfmon->ob_enc_req,
911 &caam_fops_u64_ro);
912 debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
913 ctrlpriv->ctl, &perfmon->ib_dec_req,
914 &caam_fops_u64_ro);
915 debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
916 ctrlpriv->ctl, &perfmon->ob_enc_bytes,
917 &caam_fops_u64_ro);
918 debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
919 ctrlpriv->ctl, &perfmon->ob_prot_bytes,
920 &caam_fops_u64_ro);
921 debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
922 ctrlpriv->ctl, &perfmon->ib_dec_bytes,
923 &caam_fops_u64_ro);
924 debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
925 ctrlpriv->ctl, &perfmon->ib_valid_bytes,
926 &caam_fops_u64_ro);
927
928
929 debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
930 ctrlpriv->ctl, &perfmon->faultaddr,
931 &caam_fops_u32_ro);
932 debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
933 ctrlpriv->ctl, &perfmon->faultdetail,
934 &caam_fops_u32_ro);
935 debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
936 ctrlpriv->ctl, &perfmon->status,
937 &caam_fops_u32_ro);
938
939
940 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
941 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
942 debugfs_create_blob("kek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
943 &ctrlpriv->ctl_kek_wrap);
944
945 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
946 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
947 debugfs_create_blob("tkek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
948 &ctrlpriv->ctl_tkek_wrap);
949
950 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
951 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
952 debugfs_create_blob("tdsk", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
953 &ctrlpriv->ctl_tdsk_wrap);
954#endif
955
956 ret = devm_of_platform_populate(dev);
957 if (ret)
958 dev_err(dev, "JR platform devices creation error\n");
959
960 return ret;
961}
962
963static struct platform_driver caam_driver = {
964 .driver = {
965 .name = "caam",
966 .of_match_table = caam_match,
967 },
968 .probe = caam_probe,
969};
970
971module_platform_driver(caam_driver);
972
973MODULE_LICENSE("GPL");
974MODULE_DESCRIPTION("FSL CAAM request backend");
975MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
976