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2#ifndef __NITROX_DEV_H
3#define __NITROX_DEV_H
4
5#include <linux/dma-mapping.h>
6#include <linux/interrupt.h>
7#include <linux/pci.h>
8#include <linux/if.h>
9
10#define VERSION_LEN 32
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12#define MAX_PF_QUEUES 64
13
14#define MAX_DEV_QUEUES (MAX_PF_QUEUES)
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16#define CNN55XX_MAX_UCD_BLOCKS 8
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39struct nitrox_cmdq {
40 spinlock_t cmd_qlock;
41 spinlock_t resp_qlock;
42 spinlock_t backlog_qlock;
43
44 struct nitrox_device *ndev;
45 struct list_head response_head;
46 struct list_head backlog_head;
47
48 u8 __iomem *dbell_csr_addr;
49 u8 __iomem *compl_cnt_csr_addr;
50 u8 *base;
51 dma_addr_t dma;
52
53 struct work_struct backlog_qflush;
54
55 atomic_t pending_count;
56 atomic_t backlog_count;
57
58 int write_idx;
59 u8 instr_size;
60 u8 qno;
61 u32 qsize;
62
63 u8 *unalign_base;
64 dma_addr_t unalign_dma;
65};
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79struct nitrox_hw {
80 char partname[IFNAMSIZ * 2];
81 char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN];
82
83 int freq;
84 u16 vendor_id;
85 u16 device_id;
86 u8 revision_id;
87
88 u8 se_cores;
89 u8 ae_cores;
90 u8 zip_cores;
91};
92
93struct nitrox_stats {
94 atomic64_t posted;
95 atomic64_t completed;
96 atomic64_t dropped;
97};
98
99#define IRQ_NAMESZ 32
100
101struct nitrox_q_vector {
102 char name[IRQ_NAMESZ];
103 bool valid;
104 int ring;
105 struct tasklet_struct resp_tasklet;
106 union {
107 struct nitrox_cmdq *cmdq;
108 struct nitrox_device *ndev;
109 };
110};
111
112enum mcode_type {
113 MCODE_TYPE_INVALID,
114 MCODE_TYPE_AE,
115 MCODE_TYPE_SE_SSL,
116 MCODE_TYPE_SE_IPSEC,
117};
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125union mbox_msg {
126 u64 value;
127 struct {
128 u64 type: 2;
129 u64 opcode: 6;
130 u64 data: 58;
131 };
132 struct {
133 u64 type: 2;
134 u64 opcode: 6;
135 u64 chipid: 8;
136 u64 vfid: 8;
137 } id;
138 struct {
139 u64 type: 2;
140 u64 opcode: 6;
141 u64 count: 4;
142 u64 info: 40;
143 u64 next_se_grp: 3;
144 u64 next_ae_grp: 3;
145 } mcode_info;
146};
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157struct nitrox_vfdev {
158 atomic_t state;
159 int vfno;
160 int nr_queues;
161 int ring;
162 union mbox_msg msg;
163 atomic64_t mbx_resp;
164};
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174struct nitrox_iov {
175 int num_vfs;
176 int max_vf_queues;
177 struct nitrox_vfdev *vfdev;
178 struct workqueue_struct *pf2vf_wq;
179 struct msix_entry msix;
180};
181
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184
185enum ndev_state {
186 __NDEV_NOT_READY,
187 __NDEV_READY,
188 __NDEV_IN_RESET,
189};
190
191
192enum vf_mode {
193 __NDEV_MODE_PF,
194 __NDEV_MODE_VF16,
195 __NDEV_MODE_VF32,
196 __NDEV_MODE_VF64,
197 __NDEV_MODE_VF128,
198};
199
200#define __NDEV_SRIOV_BIT 0
201
202
203#define DEFAULT_CMD_QLEN 2048
204
205#define CMD_TIMEOUT 2000
206
207#define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
208
209#define NITROX_CSR_ADDR(ndev, offset) \
210 ((ndev)->bar_addr + (offset))
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236struct nitrox_device {
237 struct list_head list;
238
239 u8 __iomem *bar_addr;
240 struct pci_dev *pdev;
241
242 atomic_t state;
243 unsigned long flags;
244 unsigned long timeout;
245 refcount_t refcnt;
246
247 u8 idx;
248 int node;
249 u16 qlen;
250 u16 nr_queues;
251 enum vf_mode mode;
252
253 struct dma_pool *ctx_pool;
254 struct nitrox_cmdq *pkt_inq;
255 struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp;
256
257 struct nitrox_q_vector *qvec;
258 struct nitrox_iov iov;
259 int num_vecs;
260
261 struct nitrox_stats stats;
262 struct nitrox_hw hw;
263#if IS_ENABLED(CONFIG_DEBUG_FS)
264 struct dentry *debugfs_dir;
265#endif
266};
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275static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
276{
277 return readq(ndev->bar_addr + offset);
278}
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286static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
287 u64 value)
288{
289 writeq(value, (ndev->bar_addr + offset));
290}
291
292static inline bool nitrox_ready(struct nitrox_device *ndev)
293{
294 return atomic_read(&ndev->state) == __NDEV_READY;
295}
296
297static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev)
298{
299 return atomic_read(&vfdev->state) == __NDEV_READY;
300}
301
302#endif
303