linux/drivers/gpio/gpio-stmpe.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) ST-Ericsson SA 2010
   4 *
   5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   6 */
   7
   8#include <linux/init.h>
   9#include <linux/platform_device.h>
  10#include <linux/slab.h>
  11#include <linux/gpio/driver.h>
  12#include <linux/interrupt.h>
  13#include <linux/of.h>
  14#include <linux/mfd/stmpe.h>
  15#include <linux/seq_file.h>
  16#include <linux/bitops.h>
  17
  18/*
  19 * These registers are modified under the irq bus lock and cached to avoid
  20 * unnecessary writes in bus_sync_unlock.
  21 */
  22enum { REG_RE, REG_FE, REG_IE };
  23
  24enum { LSB, CSB, MSB };
  25
  26#define CACHE_NR_REGS   3
  27/* No variant has more than 24 GPIOs */
  28#define CACHE_NR_BANKS  (24 / 8)
  29
  30struct stmpe_gpio {
  31        struct gpio_chip chip;
  32        struct stmpe *stmpe;
  33        struct device *dev;
  34        struct mutex irq_lock;
  35        u32 norequest_mask;
  36        /* Caches of interrupt control registers for bus_lock */
  37        u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  38        u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  39};
  40
  41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  42{
  43        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  44        struct stmpe *stmpe = stmpe_gpio->stmpe;
  45        u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
  46        u8 mask = BIT(offset % 8);
  47        int ret;
  48
  49        ret = stmpe_reg_read(stmpe, reg);
  50        if (ret < 0)
  51                return ret;
  52
  53        return !!(ret & mask);
  54}
  55
  56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  57{
  58        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  59        struct stmpe *stmpe = stmpe_gpio->stmpe;
  60        int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  61        u8 reg = stmpe->regs[which + (offset / 8)];
  62        u8 mask = BIT(offset % 8);
  63
  64        /*
  65         * Some variants have single register for gpio set/clear functionality.
  66         * For them we need to write 0 to clear and 1 to set.
  67         */
  68        if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
  69                stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
  70        else
  71                stmpe_reg_write(stmpe, reg, mask);
  72}
  73
  74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
  75                                    unsigned offset)
  76{
  77        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  78        struct stmpe *stmpe = stmpe_gpio->stmpe;
  79        u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  80        u8 mask = BIT(offset % 8);
  81        int ret;
  82
  83        ret = stmpe_reg_read(stmpe, reg);
  84        if (ret < 0)
  85                return ret;
  86
  87        if (ret & mask)
  88                return GPIO_LINE_DIRECTION_OUT;
  89
  90        return GPIO_LINE_DIRECTION_IN;
  91}
  92
  93static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  94                                         unsigned offset, int val)
  95{
  96        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  97        struct stmpe *stmpe = stmpe_gpio->stmpe;
  98        u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
  99        u8 mask = BIT(offset % 8);
 100
 101        stmpe_gpio_set(chip, offset, val);
 102
 103        return stmpe_set_bits(stmpe, reg, mask, mask);
 104}
 105
 106static int stmpe_gpio_direction_input(struct gpio_chip *chip,
 107                                        unsigned offset)
 108{
 109        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 110        struct stmpe *stmpe = stmpe_gpio->stmpe;
 111        u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
 112        u8 mask = BIT(offset % 8);
 113
 114        return stmpe_set_bits(stmpe, reg, mask, 0);
 115}
 116
 117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
 118{
 119        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 120        struct stmpe *stmpe = stmpe_gpio->stmpe;
 121
 122        if (stmpe_gpio->norequest_mask & BIT(offset))
 123                return -EINVAL;
 124
 125        return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
 126}
 127
 128static const struct gpio_chip template_chip = {
 129        .label                  = "stmpe",
 130        .owner                  = THIS_MODULE,
 131        .get_direction          = stmpe_gpio_get_direction,
 132        .direction_input        = stmpe_gpio_direction_input,
 133        .get                    = stmpe_gpio_get,
 134        .direction_output       = stmpe_gpio_direction_output,
 135        .set                    = stmpe_gpio_set,
 136        .request                = stmpe_gpio_request,
 137        .can_sleep              = true,
 138};
 139
 140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 141{
 142        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 143        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 144        int offset = d->hwirq;
 145        int regoffset = offset / 8;
 146        int mask = BIT(offset % 8);
 147
 148        if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
 149                return -EINVAL;
 150
 151        /* STMPE801 and STMPE 1600 don't have RE and FE registers */
 152        if (stmpe_gpio->stmpe->partnum == STMPE801 ||
 153            stmpe_gpio->stmpe->partnum == STMPE1600)
 154                return 0;
 155
 156        if (type & IRQ_TYPE_EDGE_RISING)
 157                stmpe_gpio->regs[REG_RE][regoffset] |= mask;
 158        else
 159                stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
 160
 161        if (type & IRQ_TYPE_EDGE_FALLING)
 162                stmpe_gpio->regs[REG_FE][regoffset] |= mask;
 163        else
 164                stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
 165
 166        return 0;
 167}
 168
 169static void stmpe_gpio_irq_lock(struct irq_data *d)
 170{
 171        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 172        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 173
 174        mutex_lock(&stmpe_gpio->irq_lock);
 175}
 176
 177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 178{
 179        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 180        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 181        struct stmpe *stmpe = stmpe_gpio->stmpe;
 182        int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 183        static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
 184                [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
 185                [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
 186                [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
 187                [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
 188                [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
 189                [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
 190                [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
 191                [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
 192                [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
 193        };
 194        int i, j;
 195
 196        /*
 197         * STMPE1600: to be able to get IRQ from pins,
 198         * a read must be done on GPMR register, or a write in
 199         * GPSR or GPCR registers
 200         */
 201        if (stmpe->partnum == STMPE1600) {
 202                stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
 203                stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
 204        }
 205
 206        for (i = 0; i < CACHE_NR_REGS; i++) {
 207                /* STMPE801 and STMPE1600 don't have RE and FE registers */
 208                if ((stmpe->partnum == STMPE801 ||
 209                     stmpe->partnum == STMPE1600) &&
 210                     (i != REG_IE))
 211                        continue;
 212
 213                for (j = 0; j < num_banks; j++) {
 214                        u8 old = stmpe_gpio->oldregs[i][j];
 215                        u8 new = stmpe_gpio->regs[i][j];
 216
 217                        if (new == old)
 218                                continue;
 219
 220                        stmpe_gpio->oldregs[i][j] = new;
 221                        stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
 222                }
 223        }
 224
 225        mutex_unlock(&stmpe_gpio->irq_lock);
 226}
 227
 228static void stmpe_gpio_irq_mask(struct irq_data *d)
 229{
 230        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 231        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 232        int offset = d->hwirq;
 233        int regoffset = offset / 8;
 234        int mask = BIT(offset % 8);
 235
 236        stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
 237}
 238
 239static void stmpe_gpio_irq_unmask(struct irq_data *d)
 240{
 241        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 242        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 243        int offset = d->hwirq;
 244        int regoffset = offset / 8;
 245        int mask = BIT(offset % 8);
 246
 247        stmpe_gpio->regs[REG_IE][regoffset] |= mask;
 248}
 249
 250static void stmpe_dbg_show_one(struct seq_file *s,
 251                               struct gpio_chip *gc,
 252                               unsigned offset, unsigned gpio)
 253{
 254        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 255        struct stmpe *stmpe = stmpe_gpio->stmpe;
 256        const char *label = gpiochip_is_requested(gc, offset);
 257        bool val = !!stmpe_gpio_get(gc, offset);
 258        u8 bank = offset / 8;
 259        u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
 260        u8 mask = BIT(offset % 8);
 261        int ret;
 262        u8 dir;
 263
 264        ret = stmpe_reg_read(stmpe, dir_reg);
 265        if (ret < 0)
 266                return;
 267        dir = !!(ret & mask);
 268
 269        if (dir) {
 270                seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
 271                           gpio, label ?: "(none)",
 272                           val ? "hi" : "lo");
 273        } else {
 274                u8 edge_det_reg;
 275                u8 rise_reg;
 276                u8 fall_reg;
 277                u8 irqen_reg;
 278
 279                static const char * const edge_det_values[] = {
 280                        "edge-inactive",
 281                        "edge-asserted",
 282                        "not-supported"
 283                };
 284                static const char * const rise_values[] = {
 285                        "no-rising-edge-detection",
 286                        "rising-edge-detection",
 287                        "not-supported"
 288                };
 289                static const char * const fall_values[] = {
 290                        "no-falling-edge-detection",
 291                        "falling-edge-detection",
 292                        "not-supported"
 293                };
 294                #define NOT_SUPPORTED_IDX 2
 295                u8 edge_det = NOT_SUPPORTED_IDX;
 296                u8 rise = NOT_SUPPORTED_IDX;
 297                u8 fall = NOT_SUPPORTED_IDX;
 298                bool irqen;
 299
 300                switch (stmpe->partnum) {
 301                case STMPE610:
 302                case STMPE811:
 303                case STMPE1601:
 304                case STMPE2401:
 305                case STMPE2403:
 306                        edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
 307                        ret = stmpe_reg_read(stmpe, edge_det_reg);
 308                        if (ret < 0)
 309                                return;
 310                        edge_det = !!(ret & mask);
 311                        /* fall through */
 312                case STMPE1801:
 313                        rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
 314                        fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
 315
 316                        ret = stmpe_reg_read(stmpe, rise_reg);
 317                        if (ret < 0)
 318                                return;
 319                        rise = !!(ret & mask);
 320                        ret = stmpe_reg_read(stmpe, fall_reg);
 321                        if (ret < 0)
 322                                return;
 323                        fall = !!(ret & mask);
 324                        /* fall through */
 325                case STMPE801:
 326                case STMPE1600:
 327                        irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
 328                        break;
 329
 330                default:
 331                        return;
 332                }
 333
 334                ret = stmpe_reg_read(stmpe, irqen_reg);
 335                if (ret < 0)
 336                        return;
 337                irqen = !!(ret & mask);
 338
 339                seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
 340                           gpio, label ?: "(none)",
 341                           val ? "hi" : "lo",
 342                           edge_det_values[edge_det],
 343                           irqen ? "IRQ-enabled" : "IRQ-disabled",
 344                           rise_values[rise],
 345                           fall_values[fall]);
 346        }
 347}
 348
 349static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 350{
 351        unsigned i;
 352        unsigned gpio = gc->base;
 353
 354        for (i = 0; i < gc->ngpio; i++, gpio++) {
 355                stmpe_dbg_show_one(s, gc, i, gpio);
 356                seq_putc(s, '\n');
 357        }
 358}
 359
 360static struct irq_chip stmpe_gpio_irq_chip = {
 361        .name                   = "stmpe-gpio",
 362        .irq_bus_lock           = stmpe_gpio_irq_lock,
 363        .irq_bus_sync_unlock    = stmpe_gpio_irq_sync_unlock,
 364        .irq_mask               = stmpe_gpio_irq_mask,
 365        .irq_unmask             = stmpe_gpio_irq_unmask,
 366        .irq_set_type           = stmpe_gpio_irq_set_type,
 367};
 368
 369#define MAX_GPIOS 24
 370
 371static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
 372{
 373        struct stmpe_gpio *stmpe_gpio = dev;
 374        struct stmpe *stmpe = stmpe_gpio->stmpe;
 375        u8 statmsbreg;
 376        int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 377        u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
 378        int ret;
 379        int i;
 380
 381        /*
 382         * the stmpe_block_read() call below, imposes to set statmsbreg
 383         * with the register located at the lowest address. As STMPE1600
 384         * variant is the only one which respect registers address's order
 385         * (LSB regs located at lowest address than MSB ones) whereas all
 386         * the others have a registers layout with MSB located before the
 387         * LSB regs.
 388         */
 389        if (stmpe->partnum == STMPE1600)
 390                statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
 391        else
 392                statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
 393
 394        ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
 395        if (ret < 0)
 396                return IRQ_NONE;
 397
 398        for (i = 0; i < num_banks; i++) {
 399                int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
 400                           num_banks - i - 1;
 401                unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
 402                unsigned int stat = status[i];
 403
 404                stat &= enabled;
 405                if (!stat)
 406                        continue;
 407
 408                while (stat) {
 409                        int bit = __ffs(stat);
 410                        int line = bank * 8 + bit;
 411                        int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
 412                                                         line);
 413
 414                        handle_nested_irq(child_irq);
 415                        stat &= ~BIT(bit);
 416                }
 417
 418                /*
 419                 * interrupt status register write has no effect on
 420                 * 801/1801/1600, bits are cleared when read.
 421                 * Edge detect register is not present on 801/1600/1801
 422                 */
 423                if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
 424                    stmpe->partnum != STMPE1801) {
 425                        stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
 426                        stmpe_reg_write(stmpe,
 427                                        stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
 428                                        status[i]);
 429                }
 430        }
 431
 432        return IRQ_HANDLED;
 433}
 434
 435static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
 436                                      unsigned long *valid_mask,
 437                                      unsigned int ngpios)
 438{
 439        struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 440        int i;
 441
 442        if (!stmpe_gpio->norequest_mask)
 443                return;
 444
 445        /* Forbid unused lines to be mapped as IRQs */
 446        for (i = 0; i < sizeof(u32); i++) {
 447                if (stmpe_gpio->norequest_mask & BIT(i))
 448                        clear_bit(i, valid_mask);
 449        }
 450}
 451
 452static int stmpe_gpio_probe(struct platform_device *pdev)
 453{
 454        struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
 455        struct device_node *np = pdev->dev.of_node;
 456        struct stmpe_gpio *stmpe_gpio;
 457        int ret, irq;
 458
 459        if (stmpe->num_gpios > MAX_GPIOS) {
 460                dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
 461                return -EINVAL;
 462        }
 463
 464        stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
 465        if (!stmpe_gpio)
 466                return -ENOMEM;
 467
 468        mutex_init(&stmpe_gpio->irq_lock);
 469
 470        stmpe_gpio->dev = &pdev->dev;
 471        stmpe_gpio->stmpe = stmpe;
 472        stmpe_gpio->chip = template_chip;
 473        stmpe_gpio->chip.ngpio = stmpe->num_gpios;
 474        stmpe_gpio->chip.parent = &pdev->dev;
 475        stmpe_gpio->chip.of_node = np;
 476        stmpe_gpio->chip.base = -1;
 477        /*
 478         * REVISIT: this makes sure the valid mask gets allocated and
 479         * filled in when adding the gpio_chip, but the rest of the
 480         * gpio_irqchip is still filled in using the old method
 481         * in gpiochip_irqchip_add_nested() so clean this up once we
 482         * get the gpio_irqchip to initialize while adding the
 483         * gpio_chip also for threaded irqchips.
 484         */
 485        stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
 486
 487        if (IS_ENABLED(CONFIG_DEBUG_FS))
 488                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
 489
 490        of_property_read_u32(np, "st,norequest-mask",
 491                        &stmpe_gpio->norequest_mask);
 492
 493        irq = platform_get_irq(pdev, 0);
 494        if (irq < 0)
 495                dev_info(&pdev->dev,
 496                        "device configured in no-irq mode: "
 497                        "irqs are not available\n");
 498
 499        ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
 500        if (ret)
 501                goto out_free;
 502
 503        ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
 504        if (ret) {
 505                dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
 506                goto out_disable;
 507        }
 508
 509        if (irq > 0) {
 510                ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 511                                stmpe_gpio_irq, IRQF_ONESHOT,
 512                                "stmpe-gpio", stmpe_gpio);
 513                if (ret) {
 514                        dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
 515                        goto out_disable;
 516                }
 517                ret =  gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
 518                                                   &stmpe_gpio_irq_chip,
 519                                                   0,
 520                                                   handle_simple_irq,
 521                                                   IRQ_TYPE_NONE);
 522                if (ret) {
 523                        dev_err(&pdev->dev,
 524                                "could not connect irqchip to gpiochip\n");
 525                        goto out_disable;
 526                }
 527
 528                gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
 529                                            &stmpe_gpio_irq_chip,
 530                                            irq);
 531        }
 532
 533        platform_set_drvdata(pdev, stmpe_gpio);
 534
 535        return 0;
 536
 537out_disable:
 538        stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 539        gpiochip_remove(&stmpe_gpio->chip);
 540out_free:
 541        kfree(stmpe_gpio);
 542        return ret;
 543}
 544
 545static struct platform_driver stmpe_gpio_driver = {
 546        .driver = {
 547                .suppress_bind_attrs    = true,
 548                .name                   = "stmpe-gpio",
 549        },
 550        .probe          = stmpe_gpio_probe,
 551};
 552
 553static int __init stmpe_gpio_init(void)
 554{
 555        return platform_driver_register(&stmpe_gpio_driver);
 556}
 557subsys_initcall(stmpe_gpio_init);
 558