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8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/of.h>
18
19#define DRIVER_NAME "zynq-gpio"
20
21
22#define ZYNQ_GPIO_MAX_BANK 4
23#define ZYNQMP_GPIO_MAX_BANK 6
24
25#define ZYNQ_GPIO_BANK0_NGPIO 32
26#define ZYNQ_GPIO_BANK1_NGPIO 22
27#define ZYNQ_GPIO_BANK2_NGPIO 32
28#define ZYNQ_GPIO_BANK3_NGPIO 32
29
30#define ZYNQMP_GPIO_BANK0_NGPIO 26
31#define ZYNQMP_GPIO_BANK1_NGPIO 26
32#define ZYNQMP_GPIO_BANK2_NGPIO 26
33#define ZYNQMP_GPIO_BANK3_NGPIO 32
34#define ZYNQMP_GPIO_BANK4_NGPIO 32
35#define ZYNQMP_GPIO_BANK5_NGPIO 32
36
37#define ZYNQ_GPIO_NR_GPIOS 118
38#define ZYNQMP_GPIO_NR_GPIOS 174
39
40#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
41#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
42 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
43#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
44#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
45 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
46#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
47#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
48 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
49#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
50#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
51 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
52#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
53#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
54 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
55#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
56#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
57 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
58
59
60
61#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
62
63#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
64
65#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
66#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
67
68#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
69
70#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
71
72#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
73
74#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
75
76#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
77
78#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
79
80#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
81
82#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
83
84#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
85
86
87#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
88
89
90#define ZYNQ_GPIO_MID_PIN_NUM 16
91
92
93#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
94
95
96#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
97#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
98
99struct gpio_regs {
100 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
101 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
102 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
103 u32 outen[ZYNQMP_GPIO_MAX_BANK];
104 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
105 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
106 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
107 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
109};
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119
120struct zynq_gpio {
121 struct gpio_chip chip;
122 void __iomem *base_addr;
123 struct clk *clk;
124 int irq;
125 const struct zynq_platform_data *p_data;
126 struct gpio_regs context;
127};
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137
138struct zynq_platform_data {
139 const char *label;
140 u32 quirks;
141 u16 ngpio;
142 int max_bank;
143 int bank_min[ZYNQMP_GPIO_MAX_BANK];
144 int bank_max[ZYNQMP_GPIO_MAX_BANK];
145};
146
147static struct irq_chip zynq_gpio_level_irqchip;
148static struct irq_chip zynq_gpio_edge_irqchip;
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155
156static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
157{
158 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
159}
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166
167static int gpio_data_ro_bug(struct zynq_gpio *gpio)
168{
169 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
170}
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183
184static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
185 unsigned int *bank_num,
186 unsigned int *bank_pin_num,
187 struct zynq_gpio *gpio)
188{
189 int bank;
190
191 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
192 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
193 (pin_num <= gpio->p_data->bank_max[bank])) {
194 *bank_num = bank;
195 *bank_pin_num = pin_num -
196 gpio->p_data->bank_min[bank];
197 return;
198 }
199 }
200
201
202 WARN(true, "invalid GPIO pin number: %u", pin_num);
203 *bank_num = 0;
204 *bank_pin_num = 0;
205}
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216static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
217{
218 u32 data;
219 unsigned int bank_num, bank_pin_num;
220 struct zynq_gpio *gpio = gpiochip_get_data(chip);
221
222 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
223
224 if (gpio_data_ro_bug(gpio)) {
225 if (zynq_gpio_is_zynq(gpio)) {
226 if (bank_num <= 1) {
227 data = readl_relaxed(gpio->base_addr +
228 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
229 } else {
230 data = readl_relaxed(gpio->base_addr +
231 ZYNQ_GPIO_DATA_OFFSET(bank_num));
232 }
233 } else {
234 if (bank_num <= 2) {
235 data = readl_relaxed(gpio->base_addr +
236 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
237 } else {
238 data = readl_relaxed(gpio->base_addr +
239 ZYNQ_GPIO_DATA_OFFSET(bank_num));
240 }
241 }
242 } else {
243 data = readl_relaxed(gpio->base_addr +
244 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
245 }
246 return (data >> bank_pin_num) & 1;
247}
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258
259static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
260 int state)
261{
262 unsigned int reg_offset, bank_num, bank_pin_num;
263 struct zynq_gpio *gpio = gpiochip_get_data(chip);
264
265 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
266
267 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
268
269 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
270 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
271 } else {
272 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
273 }
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279 state = !!state;
280 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
281 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
282
283 writel_relaxed(state, gpio->base_addr + reg_offset);
284}
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296static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
297{
298 u32 reg;
299 unsigned int bank_num, bank_pin_num;
300 struct zynq_gpio *gpio = gpiochip_get_data(chip);
301
302 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
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308 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
309 (bank_pin_num == 7 || bank_pin_num == 8))
310 return -EINVAL;
311
312
313 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
314 reg &= ~BIT(bank_pin_num);
315 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
316
317 return 0;
318}
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331
332static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
333 int state)
334{
335 u32 reg;
336 unsigned int bank_num, bank_pin_num;
337 struct zynq_gpio *gpio = gpiochip_get_data(chip);
338
339 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
340
341
342 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
343 reg |= BIT(bank_pin_num);
344 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
345
346
347 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
348 reg |= BIT(bank_pin_num);
349 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
350
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352 zynq_gpio_set_value(chip, pin, state);
353 return 0;
354}
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365static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
366{
367 u32 reg;
368 unsigned int bank_num, bank_pin_num;
369 struct zynq_gpio *gpio = gpiochip_get_data(chip);
370
371 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
372
373 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
374
375 if (reg & BIT(bank_pin_num))
376 return GPIO_LINE_DIRECTION_OUT;
377
378 return GPIO_LINE_DIRECTION_IN;
379}
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388
389static void zynq_gpio_irq_mask(struct irq_data *irq_data)
390{
391 unsigned int device_pin_num, bank_num, bank_pin_num;
392 struct zynq_gpio *gpio =
393 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
394
395 device_pin_num = irq_data->hwirq;
396 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
397 writel_relaxed(BIT(bank_pin_num),
398 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
399}
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410static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
411{
412 unsigned int device_pin_num, bank_num, bank_pin_num;
413 struct zynq_gpio *gpio =
414 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
415
416 device_pin_num = irq_data->hwirq;
417 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
418 writel_relaxed(BIT(bank_pin_num),
419 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
420}
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430static void zynq_gpio_irq_ack(struct irq_data *irq_data)
431{
432 unsigned int device_pin_num, bank_num, bank_pin_num;
433 struct zynq_gpio *gpio =
434 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
435
436 device_pin_num = irq_data->hwirq;
437 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
438 writel_relaxed(BIT(bank_pin_num),
439 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
440}
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448
449static void zynq_gpio_irq_enable(struct irq_data *irq_data)
450{
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461 zynq_gpio_irq_ack(irq_data);
462 zynq_gpio_irq_unmask(irq_data);
463}
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480static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
481{
482 u32 int_type, int_pol, int_any;
483 unsigned int device_pin_num, bank_num, bank_pin_num;
484 struct zynq_gpio *gpio =
485 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
486
487 device_pin_num = irq_data->hwirq;
488 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
489
490 int_type = readl_relaxed(gpio->base_addr +
491 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
492 int_pol = readl_relaxed(gpio->base_addr +
493 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
494 int_any = readl_relaxed(gpio->base_addr +
495 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
496
497
498
499
500
501 switch (type) {
502 case IRQ_TYPE_EDGE_RISING:
503 int_type |= BIT(bank_pin_num);
504 int_pol |= BIT(bank_pin_num);
505 int_any &= ~BIT(bank_pin_num);
506 break;
507 case IRQ_TYPE_EDGE_FALLING:
508 int_type |= BIT(bank_pin_num);
509 int_pol &= ~BIT(bank_pin_num);
510 int_any &= ~BIT(bank_pin_num);
511 break;
512 case IRQ_TYPE_EDGE_BOTH:
513 int_type |= BIT(bank_pin_num);
514 int_any |= BIT(bank_pin_num);
515 break;
516 case IRQ_TYPE_LEVEL_HIGH:
517 int_type &= ~BIT(bank_pin_num);
518 int_pol |= BIT(bank_pin_num);
519 break;
520 case IRQ_TYPE_LEVEL_LOW:
521 int_type &= ~BIT(bank_pin_num);
522 int_pol &= ~BIT(bank_pin_num);
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 writel_relaxed(int_type,
529 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
530 writel_relaxed(int_pol,
531 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
532 writel_relaxed(int_any,
533 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
534
535 if (type & IRQ_TYPE_LEVEL_MASK)
536 irq_set_chip_handler_name_locked(irq_data,
537 &zynq_gpio_level_irqchip,
538 handle_fasteoi_irq, NULL);
539 else
540 irq_set_chip_handler_name_locked(irq_data,
541 &zynq_gpio_edge_irqchip,
542 handle_level_irq, NULL);
543
544 return 0;
545}
546
547static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
548{
549 struct zynq_gpio *gpio =
550 gpiochip_get_data(irq_data_get_irq_chip_data(data));
551
552 irq_set_irq_wake(gpio->irq, on);
553
554 return 0;
555}
556
557static int zynq_gpio_irq_reqres(struct irq_data *d)
558{
559 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
560 int ret;
561
562 ret = pm_runtime_get_sync(chip->parent);
563 if (ret < 0)
564 return ret;
565
566 return gpiochip_reqres_irq(chip, d->hwirq);
567}
568
569static void zynq_gpio_irq_relres(struct irq_data *d)
570{
571 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
572
573 gpiochip_relres_irq(chip, d->hwirq);
574 pm_runtime_put(chip->parent);
575}
576
577
578static struct irq_chip zynq_gpio_level_irqchip = {
579 .name = DRIVER_NAME,
580 .irq_enable = zynq_gpio_irq_enable,
581 .irq_eoi = zynq_gpio_irq_ack,
582 .irq_mask = zynq_gpio_irq_mask,
583 .irq_unmask = zynq_gpio_irq_unmask,
584 .irq_set_type = zynq_gpio_set_irq_type,
585 .irq_set_wake = zynq_gpio_set_wake,
586 .irq_request_resources = zynq_gpio_irq_reqres,
587 .irq_release_resources = zynq_gpio_irq_relres,
588 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
589 IRQCHIP_MASK_ON_SUSPEND,
590};
591
592static struct irq_chip zynq_gpio_edge_irqchip = {
593 .name = DRIVER_NAME,
594 .irq_enable = zynq_gpio_irq_enable,
595 .irq_ack = zynq_gpio_irq_ack,
596 .irq_mask = zynq_gpio_irq_mask,
597 .irq_unmask = zynq_gpio_irq_unmask,
598 .irq_set_type = zynq_gpio_set_irq_type,
599 .irq_set_wake = zynq_gpio_set_wake,
600 .irq_request_resources = zynq_gpio_irq_reqres,
601 .irq_release_resources = zynq_gpio_irq_relres,
602 .flags = IRQCHIP_MASK_ON_SUSPEND,
603};
604
605static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
606 unsigned int bank_num,
607 unsigned long pending)
608{
609 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
610 struct irq_domain *irqdomain = gpio->chip.irq.domain;
611 int offset;
612
613 if (!pending)
614 return;
615
616 for_each_set_bit(offset, &pending, 32) {
617 unsigned int gpio_irq;
618
619 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
620 generic_handle_irq(gpio_irq);
621 }
622}
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633
634static void zynq_gpio_irqhandler(struct irq_desc *desc)
635{
636 u32 int_sts, int_enb;
637 unsigned int bank_num;
638 struct zynq_gpio *gpio =
639 gpiochip_get_data(irq_desc_get_handler_data(desc));
640 struct irq_chip *irqchip = irq_desc_get_chip(desc);
641
642 chained_irq_enter(irqchip, desc);
643
644 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
645 int_sts = readl_relaxed(gpio->base_addr +
646 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
647 int_enb = readl_relaxed(gpio->base_addr +
648 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
649 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
650 }
651
652 chained_irq_exit(irqchip, desc);
653}
654
655static void zynq_gpio_save_context(struct zynq_gpio *gpio)
656{
657 unsigned int bank_num;
658
659 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
660 gpio->context.datalsw[bank_num] =
661 readl_relaxed(gpio->base_addr +
662 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
663 gpio->context.datamsw[bank_num] =
664 readl_relaxed(gpio->base_addr +
665 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
666 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
667 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
668 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
669 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
670 gpio->context.int_type[bank_num] =
671 readl_relaxed(gpio->base_addr +
672 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
673 gpio->context.int_polarity[bank_num] =
674 readl_relaxed(gpio->base_addr +
675 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
676 gpio->context.int_any[bank_num] =
677 readl_relaxed(gpio->base_addr +
678 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
679 }
680}
681
682static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
683{
684 unsigned int bank_num;
685
686 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
687 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
688 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
689 writel_relaxed(gpio->context.datalsw[bank_num],
690 gpio->base_addr +
691 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
692 writel_relaxed(gpio->context.datamsw[bank_num],
693 gpio->base_addr +
694 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
695 writel_relaxed(gpio->context.dirm[bank_num],
696 gpio->base_addr +
697 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
698 writel_relaxed(gpio->context.int_type[bank_num],
699 gpio->base_addr +
700 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
701 writel_relaxed(gpio->context.int_polarity[bank_num],
702 gpio->base_addr +
703 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
704 writel_relaxed(gpio->context.int_any[bank_num],
705 gpio->base_addr +
706 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
707 writel_relaxed(~(gpio->context.int_en[bank_num]),
708 gpio->base_addr +
709 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
710 }
711}
712
713static int __maybe_unused zynq_gpio_suspend(struct device *dev)
714{
715 struct zynq_gpio *gpio = dev_get_drvdata(dev);
716 struct irq_data *data = irq_get_irq_data(gpio->irq);
717
718 if (!irqd_is_wakeup_set(data)) {
719 zynq_gpio_save_context(gpio);
720 return pm_runtime_force_suspend(dev);
721 }
722
723 return 0;
724}
725
726static int __maybe_unused zynq_gpio_resume(struct device *dev)
727{
728 struct zynq_gpio *gpio = dev_get_drvdata(dev);
729 struct irq_data *data = irq_get_irq_data(gpio->irq);
730 int ret;
731
732 if (!irqd_is_wakeup_set(data)) {
733 ret = pm_runtime_force_resume(dev);
734 zynq_gpio_restore_context(gpio);
735 return ret;
736 }
737
738 return 0;
739}
740
741static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
742{
743 struct zynq_gpio *gpio = dev_get_drvdata(dev);
744
745 clk_disable_unprepare(gpio->clk);
746
747 return 0;
748}
749
750static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
751{
752 struct zynq_gpio *gpio = dev_get_drvdata(dev);
753
754 return clk_prepare_enable(gpio->clk);
755}
756
757static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
758{
759 int ret;
760
761 ret = pm_runtime_get_sync(chip->parent);
762
763
764
765
766
767 return ret < 0 ? ret : 0;
768}
769
770static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
771{
772 pm_runtime_put(chip->parent);
773}
774
775static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
776 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
777 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
778 zynq_gpio_runtime_resume, NULL)
779};
780
781static const struct zynq_platform_data zynqmp_gpio_def = {
782 .label = "zynqmp_gpio",
783 .quirks = GPIO_QUIRK_DATA_RO_BUG,
784 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
785 .max_bank = ZYNQMP_GPIO_MAX_BANK,
786 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
787 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
788 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
789 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
790 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
791 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
792 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
793 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
794 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
795 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
796 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
797 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
798};
799
800static const struct zynq_platform_data zynq_gpio_def = {
801 .label = "zynq_gpio",
802 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
803 .ngpio = ZYNQ_GPIO_NR_GPIOS,
804 .max_bank = ZYNQ_GPIO_MAX_BANK,
805 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
806 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
807 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
808 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
809 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
810 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
811 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
812 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
813};
814
815static const struct of_device_id zynq_gpio_of_match[] = {
816 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
817 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
818 { }
819};
820MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
821
822
823
824
825
826
827
828
829
830
831
832
833static int zynq_gpio_probe(struct platform_device *pdev)
834{
835 int ret, bank_num;
836 struct zynq_gpio *gpio;
837 struct gpio_chip *chip;
838 struct gpio_irq_chip *girq;
839 const struct of_device_id *match;
840
841 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
842 if (!gpio)
843 return -ENOMEM;
844
845 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
846 if (!match) {
847 dev_err(&pdev->dev, "of_match_node() failed\n");
848 return -EINVAL;
849 }
850 gpio->p_data = match->data;
851 platform_set_drvdata(pdev, gpio);
852
853 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
854 if (IS_ERR(gpio->base_addr))
855 return PTR_ERR(gpio->base_addr);
856
857 gpio->irq = platform_get_irq(pdev, 0);
858 if (gpio->irq < 0)
859 return gpio->irq;
860
861
862 chip = &gpio->chip;
863 chip->label = gpio->p_data->label;
864 chip->owner = THIS_MODULE;
865 chip->parent = &pdev->dev;
866 chip->get = zynq_gpio_get_value;
867 chip->set = zynq_gpio_set_value;
868 chip->request = zynq_gpio_request;
869 chip->free = zynq_gpio_free;
870 chip->direction_input = zynq_gpio_dir_in;
871 chip->direction_output = zynq_gpio_dir_out;
872 chip->get_direction = zynq_gpio_get_direction;
873 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
874 chip->ngpio = gpio->p_data->ngpio;
875
876
877 gpio->clk = devm_clk_get(&pdev->dev, NULL);
878 if (IS_ERR(gpio->clk)) {
879 dev_err(&pdev->dev, "input clock not found.\n");
880 return PTR_ERR(gpio->clk);
881 }
882 ret = clk_prepare_enable(gpio->clk);
883 if (ret) {
884 dev_err(&pdev->dev, "Unable to enable clock.\n");
885 return ret;
886 }
887
888 pm_runtime_set_active(&pdev->dev);
889 pm_runtime_enable(&pdev->dev);
890 ret = pm_runtime_get_sync(&pdev->dev);
891 if (ret < 0)
892 goto err_pm_dis;
893
894
895 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
896 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
897 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
898
899
900 girq = &chip->irq;
901 girq->chip = &zynq_gpio_edge_irqchip;
902 girq->parent_handler = zynq_gpio_irqhandler;
903 girq->num_parents = 1;
904 girq->parents = devm_kcalloc(&pdev->dev, 1,
905 sizeof(*girq->parents),
906 GFP_KERNEL);
907 if (!girq->parents) {
908 ret = -ENOMEM;
909 goto err_pm_put;
910 }
911 girq->parents[0] = gpio->irq;
912 girq->default_type = IRQ_TYPE_NONE;
913 girq->handler = handle_level_irq;
914
915
916 ret = gpiochip_add_data(chip, gpio);
917 if (ret) {
918 dev_err(&pdev->dev, "Failed to add gpio chip\n");
919 goto err_pm_put;
920 }
921
922 pm_runtime_put(&pdev->dev);
923
924 return 0;
925
926err_pm_put:
927 pm_runtime_put(&pdev->dev);
928err_pm_dis:
929 pm_runtime_disable(&pdev->dev);
930 clk_disable_unprepare(gpio->clk);
931
932 return ret;
933}
934
935
936
937
938
939
940
941static int zynq_gpio_remove(struct platform_device *pdev)
942{
943 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
944
945 pm_runtime_get_sync(&pdev->dev);
946 gpiochip_remove(&gpio->chip);
947 clk_disable_unprepare(gpio->clk);
948 device_set_wakeup_capable(&pdev->dev, 0);
949 pm_runtime_disable(&pdev->dev);
950 return 0;
951}
952
953static struct platform_driver zynq_gpio_driver = {
954 .driver = {
955 .name = DRIVER_NAME,
956 .pm = &zynq_gpio_dev_pm_ops,
957 .of_match_table = zynq_gpio_of_match,
958 },
959 .probe = zynq_gpio_probe,
960 .remove = zynq_gpio_remove,
961};
962
963
964
965
966
967
968static int __init zynq_gpio_init(void)
969{
970 return platform_driver_register(&zynq_gpio_driver);
971}
972postcore_initcall(zynq_gpio_init);
973
974static void __exit zynq_gpio_exit(void)
975{
976 platform_driver_unregister(&zynq_gpio_driver);
977}
978module_exit(zynq_gpio_exit);
979
980MODULE_AUTHOR("Xilinx Inc.");
981MODULE_DESCRIPTION("Zynq GPIO driver");
982MODULE_LICENSE("GPL");
983