linux/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
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   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24/*
  25 * GPU doorbell structures, functions & helpers
  26 */
  27struct amdgpu_doorbell {
  28        /* doorbell mmio */
  29        resource_size_t         base;
  30        resource_size_t         size;
  31        u32 __iomem             *ptr;
  32        u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */
  33};
  34
  35/* Reserved doorbells for amdgpu (including multimedia).
  36 * KFD can use all the rest in the 2M doorbell bar.
  37 * For asic before vega10, doorbell is 32-bit, so the
  38 * index/offset is in dword. For vega10 and after, doorbell
  39 * can be 64-bit, so the index defined is in qword.
  40 */
  41struct amdgpu_doorbell_index {
  42        uint32_t kiq;
  43        uint32_t mec_ring0;
  44        uint32_t mec_ring1;
  45        uint32_t mec_ring2;
  46        uint32_t mec_ring3;
  47        uint32_t mec_ring4;
  48        uint32_t mec_ring5;
  49        uint32_t mec_ring6;
  50        uint32_t mec_ring7;
  51        uint32_t userqueue_start;
  52        uint32_t userqueue_end;
  53        uint32_t gfx_ring0;
  54        uint32_t gfx_ring1;
  55        uint32_t sdma_engine[8];
  56        uint32_t ih;
  57        union {
  58                struct {
  59                        uint32_t vcn_ring0_1;
  60                        uint32_t vcn_ring2_3;
  61                        uint32_t vcn_ring4_5;
  62                        uint32_t vcn_ring6_7;
  63                } vcn;
  64                struct {
  65                        uint32_t uvd_ring0_1;
  66                        uint32_t uvd_ring2_3;
  67                        uint32_t uvd_ring4_5;
  68                        uint32_t uvd_ring6_7;
  69                        uint32_t vce_ring0_1;
  70                        uint32_t vce_ring2_3;
  71                        uint32_t vce_ring4_5;
  72                        uint32_t vce_ring6_7;
  73                } uvd_vce;
  74        };
  75        uint32_t first_non_cp;
  76        uint32_t last_non_cp;
  77        uint32_t max_assignment;
  78        /* Per engine SDMA doorbell size in dword */
  79        uint32_t sdma_doorbell_range;
  80};
  81
  82typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
  83{
  84        AMDGPU_DOORBELL_KIQ                     = 0x000,
  85        AMDGPU_DOORBELL_HIQ                     = 0x001,
  86        AMDGPU_DOORBELL_DIQ                     = 0x002,
  87        AMDGPU_DOORBELL_MEC_RING0               = 0x010,
  88        AMDGPU_DOORBELL_MEC_RING1               = 0x011,
  89        AMDGPU_DOORBELL_MEC_RING2               = 0x012,
  90        AMDGPU_DOORBELL_MEC_RING3               = 0x013,
  91        AMDGPU_DOORBELL_MEC_RING4               = 0x014,
  92        AMDGPU_DOORBELL_MEC_RING5               = 0x015,
  93        AMDGPU_DOORBELL_MEC_RING6               = 0x016,
  94        AMDGPU_DOORBELL_MEC_RING7               = 0x017,
  95        AMDGPU_DOORBELL_GFX_RING0               = 0x020,
  96        AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
  97        AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
  98        AMDGPU_DOORBELL_IH                      = 0x1E8,
  99        AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
 100        AMDGPU_DOORBELL_INVALID                 = 0xFFFF
 101} AMDGPU_DOORBELL_ASSIGNMENT;
 102
 103typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
 104{
 105        /* Compute + GFX: 0~255 */
 106        AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,
 107        AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,
 108        AMDGPU_VEGA20_DOORBELL_DIQ                     = 0x002,
 109        AMDGPU_VEGA20_DOORBELL_MEC_RING0               = 0x003,
 110        AMDGPU_VEGA20_DOORBELL_MEC_RING1               = 0x004,
 111        AMDGPU_VEGA20_DOORBELL_MEC_RING2               = 0x005,
 112        AMDGPU_VEGA20_DOORBELL_MEC_RING3               = 0x006,
 113        AMDGPU_VEGA20_DOORBELL_MEC_RING4               = 0x007,
 114        AMDGPU_VEGA20_DOORBELL_MEC_RING5               = 0x008,
 115        AMDGPU_VEGA20_DOORBELL_MEC_RING6               = 0x009,
 116        AMDGPU_VEGA20_DOORBELL_MEC_RING7               = 0x00A,
 117        AMDGPU_VEGA20_DOORBELL_USERQUEUE_START         = 0x00B,
 118        AMDGPU_VEGA20_DOORBELL_USERQUEUE_END           = 0x08A,
 119        AMDGPU_VEGA20_DOORBELL_GFX_RING0               = 0x08B,
 120        /* SDMA:256~335*/
 121        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0            = 0x100,
 122        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1            = 0x10A,
 123        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2            = 0x114,
 124        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3            = 0x11E,
 125        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4            = 0x128,
 126        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5            = 0x132,
 127        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6            = 0x13C,
 128        AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7            = 0x146,
 129        /* IH: 376~391 */
 130        AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
 131        /* MMSCH: 392~407
 132         * overlap the doorbell assignment with VCN as they are  mutually exclusive
 133         * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
 134         */
 135        AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* VNC0 */
 136        AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
 137        AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
 138        AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
 139
 140        AMDGPU_VEGA20_DOORBELL64_VCN8_9                  = 0x18C, /* VNC1 */
 141        AMDGPU_VEGA20_DOORBELL64_VCNa_b                  = 0x18D,
 142        AMDGPU_VEGA20_DOORBELL64_VCNc_d                  = 0x18E,
 143        AMDGPU_VEGA20_DOORBELL64_VCNe_f                  = 0x18F,
 144
 145        AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
 146        AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
 147        AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
 148        AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7             = 0x18B,
 149
 150        AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1             = 0x18C,
 151        AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,
 152        AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,
 153        AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,
 154
 155        AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP            = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
 156        AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP             = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
 157
 158        AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,
 159        AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF
 160} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
 161
 162typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
 163{
 164        /* Compute + GFX: 0~255 */
 165        AMDGPU_NAVI10_DOORBELL_KIQ                      = 0x000,
 166        AMDGPU_NAVI10_DOORBELL_HIQ                      = 0x001,
 167        AMDGPU_NAVI10_DOORBELL_DIQ                      = 0x002,
 168        AMDGPU_NAVI10_DOORBELL_MEC_RING0                = 0x003,
 169        AMDGPU_NAVI10_DOORBELL_MEC_RING1                = 0x004,
 170        AMDGPU_NAVI10_DOORBELL_MEC_RING2                = 0x005,
 171        AMDGPU_NAVI10_DOORBELL_MEC_RING3                = 0x006,
 172        AMDGPU_NAVI10_DOORBELL_MEC_RING4                = 0x007,
 173        AMDGPU_NAVI10_DOORBELL_MEC_RING5                = 0x008,
 174        AMDGPU_NAVI10_DOORBELL_MEC_RING6                = 0x009,
 175        AMDGPU_NAVI10_DOORBELL_MEC_RING7                = 0x00A,
 176        AMDGPU_NAVI10_DOORBELL_USERQUEUE_START          = 0x00B,
 177        AMDGPU_NAVI10_DOORBELL_USERQUEUE_END            = 0x08A,
 178        AMDGPU_NAVI10_DOORBELL_GFX_RING0                = 0x08B,
 179        AMDGPU_NAVI10_DOORBELL_GFX_RING1                = 0x08C,
 180        /* SDMA:256~335*/
 181        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0             = 0x100,
 182        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1             = 0x10A,
 183        /* IH: 376~391 */
 184        AMDGPU_NAVI10_DOORBELL_IH                       = 0x178,
 185        /* MMSCH: 392~407
 186         * overlap the doorbell assignment with VCN as they are  mutually exclusive
 187         * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 188         */
 189        AMDGPU_NAVI10_DOORBELL64_VCN0_1                 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
 190        AMDGPU_NAVI10_DOORBELL64_VCN2_3                 = 0x189,
 191        AMDGPU_NAVI10_DOORBELL64_VCN4_5                 = 0x18A,
 192        AMDGPU_NAVI10_DOORBELL64_VCN6_7                 = 0x18B,
 193
 194        AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP           = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
 195        AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP            = AMDGPU_NAVI10_DOORBELL64_VCN6_7,
 196
 197        AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT           = 0x18F,
 198        AMDGPU_NAVI10_DOORBELL_INVALID                  = 0xFFFF
 199} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
 200
 201/*
 202 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
 203 */
 204typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
 205{
 206        /*
 207         * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
 208         * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
 209         *  Compute related doorbells are allocated from 0x00 to 0x8a
 210         */
 211
 212
 213        /* kernel scheduling */
 214        AMDGPU_DOORBELL64_KIQ                     = 0x00,
 215
 216        /* HSA interface queue and debug queue */
 217        AMDGPU_DOORBELL64_HIQ                     = 0x01,
 218        AMDGPU_DOORBELL64_DIQ                     = 0x02,
 219
 220        /* Compute engines */
 221        AMDGPU_DOORBELL64_MEC_RING0               = 0x03,
 222        AMDGPU_DOORBELL64_MEC_RING1               = 0x04,
 223        AMDGPU_DOORBELL64_MEC_RING2               = 0x05,
 224        AMDGPU_DOORBELL64_MEC_RING3               = 0x06,
 225        AMDGPU_DOORBELL64_MEC_RING4               = 0x07,
 226        AMDGPU_DOORBELL64_MEC_RING5               = 0x08,
 227        AMDGPU_DOORBELL64_MEC_RING6               = 0x09,
 228        AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,
 229
 230        /* User queue doorbell range (128 doorbells) */
 231        AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,
 232        AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,
 233
 234        /* Graphics engine */
 235        AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
 236
 237        /*
 238         * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
 239         * Graphics voltage island aperture 1
 240         * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
 241         */
 242
 243        /* For vega10 sriov, the sdma doorbell must be fixed as follow
 244         * to keep the same setting with host driver, or it will
 245         * happen conflicts
 246         */
 247        AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,
 248        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
 249        AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,
 250        AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
 251
 252        /* Interrupt handler */
 253        AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
 254        AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
 255        AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */
 256
 257        /* VCN engine use 32 bits doorbell  */
 258        AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
 259        AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,
 260        AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,
 261        AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,
 262
 263        /* overlap the doorbell assignment with VCN as they are  mutually exclusive
 264         * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 265         */
 266        AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,
 267        AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,
 268        AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,
 269        AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,
 270
 271        AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,
 272        AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,
 273        AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,
 274        AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,
 275
 276        AMDGPU_DOORBELL64_FIRST_NON_CP            = AMDGPU_DOORBELL64_sDMA_ENGINE0,
 277        AMDGPU_DOORBELL64_LAST_NON_CP             = AMDGPU_DOORBELL64_VCE_RING6_7,
 278
 279        AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
 280        AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
 281} AMDGPU_DOORBELL64_ASSIGNMENT;
 282
 283u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
 284void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 285u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
 286void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
 287
 288#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
 289#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
 290#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
 291#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
 292
 293
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