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24#ifndef __AMDGPU_GFX_H__
25#define __AMDGPU_GFX_H__
26
27
28
29
30#include "clearstate_defs.h"
31#include "amdgpu_ring.h"
32#include "amdgpu_rlc.h"
33
34
35#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
36#define AMDGPU_GFX_SAFE_MODE 0x00000001L
37#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
38#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
39#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
40
41#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
42#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
43
44enum gfx_pipe_priority {
45 AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
46 AMDGPU_GFX_PIPE_PRIO_HIGH,
47 AMDGPU_GFX_PIPE_PRIO_MAX
48};
49
50#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
51#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
52
53struct amdgpu_mec {
54 struct amdgpu_bo *hpd_eop_obj;
55 u64 hpd_eop_gpu_addr;
56 struct amdgpu_bo *mec_fw_obj;
57 u64 mec_fw_gpu_addr;
58 u32 num_mec;
59 u32 num_pipe_per_mec;
60 u32 num_queue_per_pipe;
61 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
62
63
64 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
65};
66
67enum amdgpu_unmap_queues_action {
68 PREEMPT_QUEUES = 0,
69 RESET_QUEUES,
70 DISABLE_PROCESS_QUEUES,
71 PREEMPT_QUEUES_NO_UNMAP,
72};
73
74struct kiq_pm4_funcs {
75
76 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
77 uint64_t queue_mask);
78 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
79 struct amdgpu_ring *ring);
80 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
81 struct amdgpu_ring *ring,
82 enum amdgpu_unmap_queues_action action,
83 u64 gpu_addr, u64 seq);
84 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
85 struct amdgpu_ring *ring,
86 u64 addr,
87 u64 seq);
88 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
89 uint16_t pasid, uint32_t flush_type,
90 bool all_hub);
91
92 int set_resources_size;
93 int map_queues_size;
94 int unmap_queues_size;
95 int query_status_size;
96 int invalidate_tlbs_size;
97};
98
99struct amdgpu_kiq {
100 u64 eop_gpu_addr;
101 struct amdgpu_bo *eop_obj;
102 spinlock_t ring_lock;
103 struct amdgpu_ring ring;
104 struct amdgpu_irq_src irq;
105 const struct kiq_pm4_funcs *pmf;
106 uint32_t reg_val_offs;
107};
108
109
110
111
112struct amdgpu_scratch {
113 unsigned num_reg;
114 uint32_t reg_base;
115 uint32_t free_mask;
116};
117
118
119
120
121#define AMDGPU_GFX_MAX_SE 4
122#define AMDGPU_GFX_MAX_SH_PER_SE 2
123
124struct amdgpu_rb_config {
125 uint32_t rb_backend_disable;
126 uint32_t user_rb_backend_disable;
127 uint32_t raster_config;
128 uint32_t raster_config_1;
129};
130
131struct gb_addr_config {
132 uint16_t pipe_interleave_size;
133 uint8_t num_pipes;
134 uint8_t max_compress_frags;
135 uint8_t num_banks;
136 uint8_t num_se;
137 uint8_t num_rb_per_se;
138};
139
140struct amdgpu_gfx_config {
141 unsigned max_shader_engines;
142 unsigned max_tile_pipes;
143 unsigned max_cu_per_sh;
144 unsigned max_sh_per_se;
145 unsigned max_backends_per_se;
146 unsigned max_texture_channel_caches;
147 unsigned max_gprs;
148 unsigned max_gs_threads;
149 unsigned max_hw_contexts;
150 unsigned sc_prim_fifo_size_frontend;
151 unsigned sc_prim_fifo_size_backend;
152 unsigned sc_hiz_tile_fifo_size;
153 unsigned sc_earlyz_tile_fifo_size;
154
155 unsigned num_tile_pipes;
156 unsigned backend_enable_mask;
157 unsigned mem_max_burst_length_bytes;
158 unsigned mem_row_size_in_kb;
159 unsigned shader_engine_tile_size;
160 unsigned num_gpus;
161 unsigned multi_gpu_tile_size;
162 unsigned mc_arb_ramcfg;
163 unsigned num_banks;
164 unsigned num_ranks;
165 unsigned gb_addr_config;
166 unsigned num_rbs;
167 unsigned gs_vgt_table_depth;
168 unsigned gs_prim_buffer_depth;
169
170 uint32_t tile_mode_array[32];
171 uint32_t macrotile_mode_array[16];
172
173 struct gb_addr_config gb_addr_config_fields;
174 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
175
176
177 uint32_t double_offchip_lds_buf;
178
179 uint32_t db_debug2;
180
181 uint32_t num_sc_per_sh;
182 uint32_t num_packer_per_sc;
183 uint32_t pa_sc_tile_steering_override;
184 uint64_t tcc_disabled_mask;
185};
186
187struct amdgpu_cu_info {
188 uint32_t simd_per_cu;
189 uint32_t max_waves_per_simd;
190 uint32_t wave_front_size;
191 uint32_t max_scratch_slots_per_cu;
192 uint32_t lds_size;
193
194
195 uint32_t number;
196 uint32_t ao_cu_mask;
197 uint32_t ao_cu_bitmap[4][4];
198 uint32_t bitmap[4][4];
199};
200
201struct amdgpu_gfx_funcs {
202
203 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
204 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
205 u32 sh_num, u32 instance);
206 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
207 uint32_t wave, uint32_t *dst, int *no_fields);
208 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
209 uint32_t wave, uint32_t thread, uint32_t start,
210 uint32_t size, uint32_t *dst);
211 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
212 uint32_t wave, uint32_t start, uint32_t size,
213 uint32_t *dst);
214 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
215 u32 queue, u32 vmid);
216 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
217 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
218 void (*reset_ras_error_count) (struct amdgpu_device *adev);
219};
220
221struct sq_work {
222 struct work_struct work;
223 unsigned ih_data;
224};
225
226struct amdgpu_pfp {
227 struct amdgpu_bo *pfp_fw_obj;
228 uint64_t pfp_fw_gpu_addr;
229 uint32_t *pfp_fw_ptr;
230};
231
232struct amdgpu_ce {
233 struct amdgpu_bo *ce_fw_obj;
234 uint64_t ce_fw_gpu_addr;
235 uint32_t *ce_fw_ptr;
236};
237
238struct amdgpu_me {
239 struct amdgpu_bo *me_fw_obj;
240 uint64_t me_fw_gpu_addr;
241 uint32_t *me_fw_ptr;
242 uint32_t num_me;
243 uint32_t num_pipe_per_me;
244 uint32_t num_queue_per_pipe;
245 void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
246
247
248 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
249};
250
251struct amdgpu_gfx {
252 struct mutex gpu_clock_mutex;
253 struct amdgpu_gfx_config config;
254 struct amdgpu_rlc rlc;
255 struct amdgpu_pfp pfp;
256 struct amdgpu_ce ce;
257 struct amdgpu_me me;
258 struct amdgpu_mec mec;
259 struct amdgpu_kiq kiq;
260 struct amdgpu_scratch scratch;
261 const struct firmware *me_fw;
262 uint32_t me_fw_version;
263 const struct firmware *pfp_fw;
264 uint32_t pfp_fw_version;
265 const struct firmware *ce_fw;
266 uint32_t ce_fw_version;
267 const struct firmware *rlc_fw;
268 uint32_t rlc_fw_version;
269 const struct firmware *mec_fw;
270 uint32_t mec_fw_version;
271 const struct firmware *mec2_fw;
272 uint32_t mec2_fw_version;
273 uint32_t me_feature_version;
274 uint32_t ce_feature_version;
275 uint32_t pfp_feature_version;
276 uint32_t rlc_feature_version;
277 uint32_t rlc_srlc_fw_version;
278 uint32_t rlc_srlc_feature_version;
279 uint32_t rlc_srlg_fw_version;
280 uint32_t rlc_srlg_feature_version;
281 uint32_t rlc_srls_fw_version;
282 uint32_t rlc_srls_feature_version;
283 uint32_t mec_feature_version;
284 uint32_t mec2_feature_version;
285 bool mec_fw_write_wait;
286 bool me_fw_write_wait;
287 bool cp_fw_write_wait;
288 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
289 struct drm_gpu_scheduler *gfx_sched[AMDGPU_MAX_GFX_RINGS];
290 uint32_t num_gfx_sched;
291 unsigned num_gfx_rings;
292 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
293 struct drm_gpu_scheduler **compute_prio_sched[AMDGPU_GFX_PIPE_PRIO_MAX];
294 struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
295 uint32_t num_compute_sched[AMDGPU_GFX_PIPE_PRIO_MAX];
296 unsigned num_compute_rings;
297 struct amdgpu_irq_src eop_irq;
298 struct amdgpu_irq_src priv_reg_irq;
299 struct amdgpu_irq_src priv_inst_irq;
300 struct amdgpu_irq_src cp_ecc_error_irq;
301 struct amdgpu_irq_src sq_irq;
302 struct sq_work sq_work;
303
304
305 uint32_t gfx_current_status;
306
307 unsigned ce_ram_size;
308 struct amdgpu_cu_info cu_info;
309 const struct amdgpu_gfx_funcs *funcs;
310
311
312 uint32_t grbm_soft_reset;
313 uint32_t srbm_soft_reset;
314
315
316 bool gfx_off_state;
317 struct mutex gfx_off_mutex;
318 uint32_t gfx_off_req_count;
319 struct delayed_work gfx_off_delay_work;
320
321
322 struct mutex pipe_reserve_mutex;
323 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
324
325
326 struct ras_common_if *ras_if;
327};
328
329#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
330#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
331#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
332
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339
340
341static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
342{
343 return (u32)((1ULL << bit_width) - 1);
344}
345
346int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
347void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
348
349void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
350 unsigned max_sh);
351
352int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
353 struct amdgpu_ring *ring,
354 struct amdgpu_irq_src *irq);
355
356void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
357
358void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
359int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
360 unsigned hpd_size);
361
362int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
363 unsigned mqd_size);
364void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
365int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
366int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
367
368void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
369void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
370
371int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
372 int pipe, int queue);
373void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
374 int *mec, int *pipe, int *queue);
375bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
376 int pipe, int queue);
377bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
378 int queue);
379int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
380 int pipe, int queue);
381void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
382 int *me, int *pipe, int *queue);
383bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
384 int pipe, int queue);
385void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
386int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
387void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
388int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
389 void *err_data,
390 struct amdgpu_iv_entry *entry);
391int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
392 struct amdgpu_irq_src *source,
393 struct amdgpu_iv_entry *entry);
394uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
395void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
396#endif
397
