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31#include "amdgpu.h"
32#include "amdgpu_trace.h"
33#include "amdgpu_amdkfd.h"
34
35struct amdgpu_sync_entry {
36 struct hlist_node node;
37 struct dma_fence *fence;
38 bool explicit;
39};
40
41static struct kmem_cache *amdgpu_sync_slab;
42
43
44
45
46
47
48
49
50void amdgpu_sync_create(struct amdgpu_sync *sync)
51{
52 hash_init(sync->fences);
53 sync->last_vm_update = NULL;
54}
55
56
57
58
59
60
61
62
63
64static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
65 struct dma_fence *f)
66{
67 struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
68
69 if (s_fence) {
70 struct amdgpu_ring *ring;
71
72 ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
73 return ring->adev == adev;
74 }
75
76 return false;
77}
78
79
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81
82
83
84
85
86static void *amdgpu_sync_get_owner(struct dma_fence *f)
87{
88 struct drm_sched_fence *s_fence;
89 struct amdgpu_amdkfd_fence *kfd_fence;
90
91 if (!f)
92 return AMDGPU_FENCE_OWNER_UNDEFINED;
93
94 s_fence = to_drm_sched_fence(f);
95 if (s_fence)
96 return s_fence->owner;
97
98 kfd_fence = to_amdgpu_amdkfd_fence(f);
99 if (kfd_fence)
100 return AMDGPU_FENCE_OWNER_KFD;
101
102 return AMDGPU_FENCE_OWNER_UNDEFINED;
103}
104
105
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111
112
113static void amdgpu_sync_keep_later(struct dma_fence **keep,
114 struct dma_fence *fence)
115{
116 if (*keep && dma_fence_is_later(*keep, fence))
117 return;
118
119 dma_fence_put(*keep);
120 *keep = dma_fence_get(fence);
121}
122
123
124
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130
131
132static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f,
133 bool explicit)
134{
135 struct amdgpu_sync_entry *e;
136
137 hash_for_each_possible(sync->fences, e, node, f->context) {
138 if (unlikely(e->fence->context != f->context))
139 continue;
140
141 amdgpu_sync_keep_later(&e->fence, f);
142
143
144 e->explicit |= explicit;
145
146 return true;
147 }
148 return false;
149}
150
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158
159
160int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,
161 bool explicit)
162{
163 struct amdgpu_sync_entry *e;
164
165 if (!f)
166 return 0;
167
168 if (amdgpu_sync_add_later(sync, f, explicit))
169 return 0;
170
171 e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
172 if (!e)
173 return -ENOMEM;
174
175 e->explicit = explicit;
176
177 hash_add(sync->fences, &e->node, f->context);
178 e->fence = dma_fence_get(f);
179 return 0;
180}
181
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189
190
191int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence)
192{
193 if (!fence)
194 return 0;
195
196 amdgpu_sync_keep_later(&sync->last_vm_update, fence);
197 return amdgpu_sync_fence(sync, fence, false);
198}
199
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208
209
210int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
211 struct dma_resv *resv, enum amdgpu_sync_mode mode,
212 void *owner)
213{
214 struct dma_resv_list *flist;
215 struct dma_fence *f;
216 unsigned i;
217 int r = 0;
218
219 if (resv == NULL)
220 return -EINVAL;
221
222
223 f = dma_resv_get_excl(resv);
224 r = amdgpu_sync_fence(sync, f, false);
225
226 flist = dma_resv_get_list(resv);
227 if (!flist || r)
228 return r;
229
230 for (i = 0; i < flist->shared_count; ++i) {
231 void *fence_owner;
232
233 f = rcu_dereference_protected(flist->shared[i],
234 dma_resv_held(resv));
235
236 fence_owner = amdgpu_sync_get_owner(f);
237
238
239 if (fence_owner == AMDGPU_FENCE_OWNER_UNDEFINED) {
240 r = amdgpu_sync_fence(sync, f, false);
241 if (r)
242 break;
243 }
244
245
246
247
248 if (fence_owner == AMDGPU_FENCE_OWNER_KFD &&
249 owner != AMDGPU_FENCE_OWNER_UNDEFINED)
250 continue;
251
252
253 switch (mode) {
254 case AMDGPU_SYNC_ALWAYS:
255 break;
256
257 case AMDGPU_SYNC_NE_OWNER:
258 if (amdgpu_sync_same_dev(adev, f) &&
259 fence_owner == owner)
260 continue;
261 break;
262
263 case AMDGPU_SYNC_EQ_OWNER:
264 if (amdgpu_sync_same_dev(adev, f) &&
265 fence_owner != owner)
266 continue;
267 break;
268
269 case AMDGPU_SYNC_EXPLICIT:
270 continue;
271 }
272
273 r = amdgpu_sync_fence(sync, f, false);
274 if (r)
275 break;
276 }
277 return r;
278}
279
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287
288
289struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
290 struct amdgpu_ring *ring)
291{
292 struct amdgpu_sync_entry *e;
293 struct hlist_node *tmp;
294 int i;
295
296 hash_for_each_safe(sync->fences, i, tmp, e, node) {
297 struct dma_fence *f = e->fence;
298 struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
299
300 if (dma_fence_is_signaled(f)) {
301 hash_del(&e->node);
302 dma_fence_put(f);
303 kmem_cache_free(amdgpu_sync_slab, e);
304 continue;
305 }
306 if (ring && s_fence) {
307
308
309
310 if (s_fence->sched == &ring->sched) {
311 if (dma_fence_is_signaled(&s_fence->scheduled))
312 continue;
313
314 return &s_fence->scheduled;
315 }
316 }
317
318 return f;
319 }
320
321 return NULL;
322}
323
324
325
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328
329
330
331
332struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit)
333{
334 struct amdgpu_sync_entry *e;
335 struct hlist_node *tmp;
336 struct dma_fence *f;
337 int i;
338 hash_for_each_safe(sync->fences, i, tmp, e, node) {
339
340 f = e->fence;
341 if (explicit)
342 *explicit = e->explicit;
343
344 hash_del(&e->node);
345 kmem_cache_free(amdgpu_sync_slab, e);
346
347 if (!dma_fence_is_signaled(f))
348 return f;
349
350 dma_fence_put(f);
351 }
352 return NULL;
353}
354
355
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362
363
364int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)
365{
366 struct amdgpu_sync_entry *e;
367 struct hlist_node *tmp;
368 struct dma_fence *f;
369 int i, r;
370
371 hash_for_each_safe(source->fences, i, tmp, e, node) {
372 f = e->fence;
373 if (!dma_fence_is_signaled(f)) {
374 r = amdgpu_sync_fence(clone, f, e->explicit);
375 if (r)
376 return r;
377 } else {
378 hash_del(&e->node);
379 dma_fence_put(f);
380 kmem_cache_free(amdgpu_sync_slab, e);
381 }
382 }
383
384 dma_fence_put(clone->last_vm_update);
385 clone->last_vm_update = dma_fence_get(source->last_vm_update);
386
387 return 0;
388}
389
390int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
391{
392 struct amdgpu_sync_entry *e;
393 struct hlist_node *tmp;
394 int i, r;
395
396 hash_for_each_safe(sync->fences, i, tmp, e, node) {
397 r = dma_fence_wait(e->fence, intr);
398 if (r)
399 return r;
400
401 hash_del(&e->node);
402 dma_fence_put(e->fence);
403 kmem_cache_free(amdgpu_sync_slab, e);
404 }
405
406 return 0;
407}
408
409
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411
412
413
414
415
416void amdgpu_sync_free(struct amdgpu_sync *sync)
417{
418 struct amdgpu_sync_entry *e;
419 struct hlist_node *tmp;
420 unsigned i;
421
422 hash_for_each_safe(sync->fences, i, tmp, e, node) {
423 hash_del(&e->node);
424 dma_fence_put(e->fence);
425 kmem_cache_free(amdgpu_sync_slab, e);
426 }
427
428 dma_fence_put(sync->last_vm_update);
429}
430
431
432
433
434
435
436int amdgpu_sync_init(void)
437{
438 amdgpu_sync_slab = kmem_cache_create(
439 "amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
440 SLAB_HWCACHE_ALIGN, NULL);
441 if (!amdgpu_sync_slab)
442 return -ENOMEM;
443
444 return 0;
445}
446
447
448
449
450
451
452void amdgpu_sync_fini(void)
453{
454 kmem_cache_destroy(amdgpu_sync_slab);
455}
456