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23#include <linux/firmware.h>
24#include <linux/module.h>
25#include "amdgpu.h"
26#include "amdgpu_psp.h"
27#include "amdgpu_ucode.h"
28#include "soc15_common.h"
29#include "psp_v12_0.h"
30
31#include "mp/mp_12_0_0_offset.h"
32#include "mp/mp_12_0_0_sh_mask.h"
33#include "gc/gc_9_0_offset.h"
34#include "sdma0/sdma0_4_0_offset.h"
35#include "nbio/nbio_7_4_offset.h"
36
37#include "oss/osssys_4_0_offset.h"
38#include "oss/osssys_4_0_sh_mask.h"
39
40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
41
42#define smnMP1_FIRMWARE_FLAGS 0x3010024
43
44static int psp_v12_0_init_microcode(struct psp_context *psp)
45{
46 struct amdgpu_device *adev = psp->adev;
47 const char *chip_name;
48 char fw_name[30];
49 int err = 0;
50 const struct psp_firmware_header_v1_0 *asd_hdr;
51
52 DRM_DEBUG("\n");
53
54 switch (adev->asic_type) {
55 case CHIP_RENOIR:
56 chip_name = "renoir";
57 break;
58 default:
59 BUG();
60 }
61
62 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
63 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
64 if (err)
65 goto out1;
66
67 err = amdgpu_ucode_validate(adev->psp.asd_fw);
68 if (err)
69 goto out1;
70
71 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
72 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
73 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
74 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
75 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
76 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
77
78 return 0;
79
80out1:
81 release_firmware(adev->psp.asd_fw);
82 adev->psp.asd_fw = NULL;
83
84 return err;
85}
86
87static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
88{
89 int ret;
90 uint32_t psp_gfxdrv_command_reg = 0;
91 struct amdgpu_device *adev = psp->adev;
92 uint32_t sol_reg;
93
94
95
96
97 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
98 if (sol_reg) {
99 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
100 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
101 return 0;
102 }
103
104
105 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
106 0x80000000, 0x80000000, false);
107 if (ret)
108 return ret;
109
110 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
111
112
113 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
114
115
116 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
117 (uint32_t)(psp->fw_pri_mc_addr >> 20));
118 psp_gfxdrv_command_reg = 1 << 16;
119 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
120 psp_gfxdrv_command_reg);
121
122
123 mdelay(20);
124
125 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
126 0x80000000, 0x80000000, false);
127
128 return ret;
129}
130
131static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
132{
133 int ret;
134 unsigned int psp_gfxdrv_command_reg = 0;
135 struct amdgpu_device *adev = psp->adev;
136 uint32_t sol_reg;
137
138
139
140
141 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
142 if (sol_reg)
143 return 0;
144
145
146 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
147 0x80000000, 0x80000000, false);
148 if (ret)
149 return ret;
150
151 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
152
153
154 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
155
156
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
158 (uint32_t)(psp->fw_pri_mc_addr >> 20));
159 psp_gfxdrv_command_reg = 2 << 16;
160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
161 psp_gfxdrv_command_reg);
162
163
164 mdelay(20);
165 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
166 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
167 0, true);
168
169 return ret;
170}
171
172static void psp_v12_0_reroute_ih(struct psp_context *psp)
173{
174 struct amdgpu_device *adev = psp->adev;
175 uint32_t tmp;
176
177
178 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
179 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
180 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
181
182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
184 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
185
186 mdelay(20);
187 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
188 0x80000000, 0x8000FFFF, false);
189
190
191 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
192 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
193
194 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
196 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
197
198 mdelay(20);
199 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
200 0x80000000, 0x8000FFFF, false);
201}
202
203static int psp_v12_0_ring_init(struct psp_context *psp,
204 enum psp_ring_type ring_type)
205{
206 int ret = 0;
207 struct psp_ring *ring;
208 struct amdgpu_device *adev = psp->adev;
209
210 psp_v12_0_reroute_ih(psp);
211
212 ring = &psp->km_ring;
213
214 ring->ring_type = ring_type;
215
216
217 ring->ring_size = 0x1000;
218 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
219 AMDGPU_GEM_DOMAIN_VRAM,
220 &adev->firmware.rbuf,
221 &ring->ring_mem_mc_addr,
222 (void **)&ring->ring_mem);
223 if (ret) {
224 ring->ring_size = 0;
225 return ret;
226 }
227
228 return 0;
229}
230
231static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
232{
233 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
234 return true;
235 return false;
236}
237
238static int psp_v12_0_ring_create(struct psp_context *psp,
239 enum psp_ring_type ring_type)
240{
241 int ret = 0;
242 unsigned int psp_ring_reg = 0;
243 struct psp_ring *ring = &psp->km_ring;
244 struct amdgpu_device *adev = psp->adev;
245
246 if (psp_v12_0_support_vmr_ring(psp)) {
247
248 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
249 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
250
251 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
252 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
253
254
255 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
256 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
257
258
259 mdelay(20);
260
261
262 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
263 0x80000000, 0x8000FFFF, false);
264
265 } else {
266
267 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
269
270 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
272
273 psp_ring_reg = ring->ring_size;
274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
275
276 psp_ring_reg = ring_type;
277 psp_ring_reg = psp_ring_reg << 16;
278 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
279
280
281 mdelay(20);
282
283
284 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
285 0x80000000, 0x8000FFFF, false);
286 }
287
288 return ret;
289}
290
291static int psp_v12_0_ring_stop(struct psp_context *psp,
292 enum psp_ring_type ring_type)
293{
294 int ret = 0;
295 struct amdgpu_device *adev = psp->adev;
296
297
298 if (psp_v12_0_support_vmr_ring(psp))
299 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
300 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
301 else
302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
303 GFX_CTRL_CMD_ID_DESTROY_RINGS);
304
305
306 mdelay(20);
307
308
309 if (psp_v12_0_support_vmr_ring(psp))
310 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
311 0x80000000, 0x80000000, false);
312 else
313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
314 0x80000000, 0x80000000, false);
315
316 return ret;
317}
318
319static int psp_v12_0_ring_destroy(struct psp_context *psp,
320 enum psp_ring_type ring_type)
321{
322 int ret = 0;
323 struct psp_ring *ring = &psp->km_ring;
324 struct amdgpu_device *adev = psp->adev;
325
326 ret = psp_v12_0_ring_stop(psp, ring_type);
327 if (ret)
328 DRM_ERROR("Fail to stop psp ring\n");
329
330 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
331 &ring->ring_mem_mc_addr,
332 (void **)&ring->ring_mem);
333
334 return ret;
335}
336
337static int
338psp_v12_0_sram_map(struct amdgpu_device *adev,
339 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
340 unsigned int *sram_data_reg_offset,
341 enum AMDGPU_UCODE_ID ucode_id)
342{
343 int ret = 0;
344
345 switch (ucode_id) {
346
347#if 0
348 case AMDGPU_UCODE_ID_SMC:
349 *sram_offset = 0;
350 *sram_addr_reg_offset = 0;
351 *sram_data_reg_offset = 0;
352 break;
353#endif
354
355 case AMDGPU_UCODE_ID_CP_CE:
356 *sram_offset = 0x0;
357 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
358 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
359 break;
360
361 case AMDGPU_UCODE_ID_CP_PFP:
362 *sram_offset = 0x0;
363 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
364 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
365 break;
366
367 case AMDGPU_UCODE_ID_CP_ME:
368 *sram_offset = 0x0;
369 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
370 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
371 break;
372
373 case AMDGPU_UCODE_ID_CP_MEC1:
374 *sram_offset = 0x10000;
375 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
376 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
377 break;
378
379 case AMDGPU_UCODE_ID_CP_MEC2:
380 *sram_offset = 0x10000;
381 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
382 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
383 break;
384
385 case AMDGPU_UCODE_ID_RLC_G:
386 *sram_offset = 0x2000;
387 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
388 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
389 break;
390
391 case AMDGPU_UCODE_ID_SDMA0:
392 *sram_offset = 0x0;
393 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
394 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
395 break;
396
397
398#if 0
399 case AMDGPU_UCODE_ID_SDMA1:
400 *sram_offset = ;
401 *sram_addr_reg_offset = ;
402 break;
403
404 case AMDGPU_UCODE_ID_UVD:
405 *sram_offset = ;
406 *sram_addr_reg_offset = ;
407 break;
408
409 case AMDGPU_UCODE_ID_VCE:
410 *sram_offset = ;
411 *sram_addr_reg_offset = ;
412 break;
413#endif
414
415 case AMDGPU_UCODE_ID_MAXIMUM:
416 default:
417 ret = -EINVAL;
418 break;
419 }
420
421 return ret;
422}
423
424static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
425 struct amdgpu_firmware_info *ucode,
426 enum AMDGPU_UCODE_ID ucode_type)
427{
428 int err = 0;
429 unsigned int fw_sram_reg_val = 0;
430 unsigned int fw_sram_addr_reg_offset = 0;
431 unsigned int fw_sram_data_reg_offset = 0;
432 unsigned int ucode_size;
433 uint32_t *ucode_mem = NULL;
434 struct amdgpu_device *adev = psp->adev;
435
436 err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
437 &fw_sram_data_reg_offset, ucode_type);
438 if (err)
439 return false;
440
441 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
442
443 ucode_size = ucode->ucode_size;
444 ucode_mem = (uint32_t *)ucode->kaddr;
445 while (ucode_size) {
446 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
447
448 if (*ucode_mem != fw_sram_reg_val)
449 return false;
450
451 ucode_mem++;
452
453 ucode_size -= 4;
454 }
455
456 return true;
457}
458
459static int psp_v12_0_mode1_reset(struct psp_context *psp)
460{
461 int ret;
462 uint32_t offset;
463 struct amdgpu_device *adev = psp->adev;
464
465 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
466
467 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
468
469 if (ret) {
470 DRM_INFO("psp is not working correctly before mode1 reset!\n");
471 return -EINVAL;
472 }
473
474
475 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
476
477 msleep(500);
478
479 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
480
481 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
482
483 if (ret) {
484 DRM_INFO("psp mode 1 reset failed!\n");
485 return -EINVAL;
486 }
487
488 DRM_INFO("psp mode1 reset succeed \n");
489
490 return 0;
491}
492
493static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
494{
495 uint32_t data;
496 struct amdgpu_device *adev = psp->adev;
497
498 if (psp_v12_0_support_vmr_ring(psp))
499 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
500 else
501 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
502
503 return data;
504}
505
506static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
507{
508 struct amdgpu_device *adev = psp->adev;
509
510 if (psp_v12_0_support_vmr_ring(psp)) {
511 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
512 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
513 } else
514 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
515}
516
517static const struct psp_funcs psp_v12_0_funcs = {
518 .init_microcode = psp_v12_0_init_microcode,
519 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
520 .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
521 .ring_init = psp_v12_0_ring_init,
522 .ring_create = psp_v12_0_ring_create,
523 .ring_stop = psp_v12_0_ring_stop,
524 .ring_destroy = psp_v12_0_ring_destroy,
525 .compare_sram_data = psp_v12_0_compare_sram_data,
526 .mode1_reset = psp_v12_0_mode1_reset,
527 .ring_get_wptr = psp_v12_0_ring_get_wptr,
528 .ring_set_wptr = psp_v12_0_ring_set_wptr,
529};
530
531void psp_v12_0_set_psp_funcs(struct psp_context *psp)
532{
533 psp->funcs = &psp_v12_0_funcs;
534}
535
