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8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/dma-buf.h>
11#include <linux/gpio/consumer.h>
12#include <linux/module.h>
13#include <linux/regulator/consumer.h>
14#include <linux/spi/spi.h>
15
16#include <drm/drm_connector.h>
17#include <drm/drm_damage_helper.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_gem_cma_helper.h>
20#include <drm/drm_format_helper.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_mipi_dbi.h>
24#include <drm/drm_modes.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_rect.h>
27#include <video/mipi_display.h>
28
29#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000
30
31#define DCS_POWER_MODE_DISPLAY BIT(2)
32#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
33#define DCS_POWER_MODE_SLEEP_MODE BIT(4)
34#define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
35#define DCS_POWER_MODE_IDLE_MODE BIT(6)
36#define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
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66
67#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
68({ \
69 if (!len) \
70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
71 else if (len <= 32) \
72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
73 else \
74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
75})
76
77static const u8 mipi_dbi_dcs_read_commands[] = {
78 MIPI_DCS_GET_DISPLAY_ID,
79 MIPI_DCS_GET_RED_CHANNEL,
80 MIPI_DCS_GET_GREEN_CHANNEL,
81 MIPI_DCS_GET_BLUE_CHANNEL,
82 MIPI_DCS_GET_DISPLAY_STATUS,
83 MIPI_DCS_GET_POWER_MODE,
84 MIPI_DCS_GET_ADDRESS_MODE,
85 MIPI_DCS_GET_PIXEL_FORMAT,
86 MIPI_DCS_GET_DISPLAY_MODE,
87 MIPI_DCS_GET_SIGNAL_MODE,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 MIPI_DCS_READ_MEMORY_START,
90 MIPI_DCS_READ_MEMORY_CONTINUE,
91 MIPI_DCS_GET_SCANLINE,
92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 MIPI_DCS_GET_CONTROL_DISPLAY,
94 MIPI_DCS_GET_POWER_SAVE,
95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 MIPI_DCS_READ_DDB_START,
97 MIPI_DCS_READ_DDB_CONTINUE,
98 0,
99};
100
101static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
102{
103 unsigned int i;
104
105 if (!dbi->read_commands)
106 return false;
107
108 for (i = 0; i < 0xff; i++) {
109 if (!dbi->read_commands[i])
110 return false;
111 if (cmd == dbi->read_commands[i])
112 return true;
113 }
114
115 return false;
116}
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129int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
130{
131 if (!dbi->read_commands)
132 return -EACCES;
133
134 if (!mipi_dbi_command_is_read(dbi, cmd))
135 return -EINVAL;
136
137 return mipi_dbi_command_buf(dbi, cmd, val, 1);
138}
139EXPORT_SYMBOL(mipi_dbi_command_read);
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151int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
152{
153 u8 *cmdbuf;
154 int ret;
155
156
157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
158 if (!cmdbuf)
159 return -ENOMEM;
160
161 mutex_lock(&dbi->cmdlock);
162 ret = dbi->command(dbi, cmdbuf, data, len);
163 mutex_unlock(&dbi->cmdlock);
164
165 kfree(cmdbuf);
166
167 return ret;
168}
169EXPORT_SYMBOL(mipi_dbi_command_buf);
170
171
172int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
173{
174 u8 *buf;
175 int ret;
176
177 buf = kmemdup(data, len, GFP_KERNEL);
178 if (!buf)
179 return -ENOMEM;
180
181 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
182
183 kfree(buf);
184
185 return ret;
186}
187EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
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198
199int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
200 struct drm_rect *clip, bool swap)
201{
202 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
203 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
204 struct dma_buf_attachment *import_attach = gem->import_attach;
205 struct drm_format_name_buf format_name;
206 void *src = cma_obj->vaddr;
207 int ret = 0;
208
209 if (import_attach) {
210 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
211 DMA_FROM_DEVICE);
212 if (ret)
213 return ret;
214 }
215
216 switch (fb->format->format) {
217 case DRM_FORMAT_RGB565:
218 if (swap)
219 drm_fb_swab16(dst, src, fb, clip);
220 else
221 drm_fb_memcpy(dst, src, fb, clip);
222 break;
223 case DRM_FORMAT_XRGB8888:
224 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
225 break;
226 default:
227 dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
228 drm_get_format_name(fb->format->format,
229 &format_name));
230 return -EINVAL;
231 }
232
233 if (import_attach)
234 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
235 DMA_FROM_DEVICE);
236 return ret;
237}
238EXPORT_SYMBOL(mipi_dbi_buf_copy);
239
240static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
241 unsigned int xs, unsigned int xe,
242 unsigned int ys, unsigned int ye)
243{
244 struct mipi_dbi *dbi = &dbidev->dbi;
245
246 xs += dbidev->left_offset;
247 xe += dbidev->left_offset;
248 ys += dbidev->top_offset;
249 ye += dbidev->top_offset;
250
251 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
252 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
253 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
254 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
255}
256
257static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
258{
259 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
260 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
261 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
262 unsigned int height = rect->y2 - rect->y1;
263 unsigned int width = rect->x2 - rect->x1;
264 struct mipi_dbi *dbi = &dbidev->dbi;
265 bool swap = dbi->swap_bytes;
266 int idx, ret = 0;
267 bool full;
268 void *tr;
269
270 if (!dbidev->enabled)
271 return;
272
273 if (!drm_dev_enter(fb->dev, &idx))
274 return;
275
276 full = width == fb->width && height == fb->height;
277
278 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
279
280 if (!dbi->dc || !full || swap ||
281 fb->format->format == DRM_FORMAT_XRGB8888) {
282 tr = dbidev->tx_buf;
283 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
284 if (ret)
285 goto err_msg;
286 } else {
287 tr = cma_obj->vaddr;
288 }
289
290 mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
291 rect->y2 - 1);
292
293 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
294 width * height * 2);
295err_msg:
296 if (ret)
297 dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
298
299 drm_dev_exit(idx);
300}
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310void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
311 struct drm_plane_state *old_state)
312{
313 struct drm_plane_state *state = pipe->plane.state;
314 struct drm_rect rect;
315
316 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
317 mipi_dbi_fb_dirty(state->fb, &rect);
318}
319EXPORT_SYMBOL(mipi_dbi_pipe_update);
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335void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
336 struct drm_crtc_state *crtc_state,
337 struct drm_plane_state *plane_state)
338{
339 struct drm_framebuffer *fb = plane_state->fb;
340 struct drm_rect rect = {
341 .x1 = 0,
342 .x2 = fb->width,
343 .y1 = 0,
344 .y2 = fb->height,
345 };
346 int idx;
347
348 if (!drm_dev_enter(&dbidev->drm, &idx))
349 return;
350
351 dbidev->enabled = true;
352 mipi_dbi_fb_dirty(fb, &rect);
353 backlight_enable(dbidev->backlight);
354
355 drm_dev_exit(idx);
356}
357EXPORT_SYMBOL(mipi_dbi_enable_flush);
358
359static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
360{
361 struct drm_device *drm = &dbidev->drm;
362 u16 height = drm->mode_config.min_height;
363 u16 width = drm->mode_config.min_width;
364 struct mipi_dbi *dbi = &dbidev->dbi;
365 size_t len = width * height * 2;
366 int idx;
367
368 if (!drm_dev_enter(drm, &idx))
369 return;
370
371 memset(dbidev->tx_buf, 0, len);
372
373 mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
374 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
375 (u8 *)dbidev->tx_buf, len);
376
377 drm_dev_exit(idx);
378}
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386
387
388void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
389{
390 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
391
392 if (!dbidev->enabled)
393 return;
394
395 DRM_DEBUG_KMS("\n");
396
397 dbidev->enabled = false;
398
399 if (dbidev->backlight)
400 backlight_disable(dbidev->backlight);
401 else
402 mipi_dbi_blank(dbidev);
403
404 if (dbidev->regulator)
405 regulator_disable(dbidev->regulator);
406}
407EXPORT_SYMBOL(mipi_dbi_pipe_disable);
408
409static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
410{
411 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
412 struct drm_display_mode *mode;
413
414 mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
415 if (!mode) {
416 DRM_ERROR("Failed to duplicate mode\n");
417 return 0;
418 }
419
420 if (mode->name[0] == '\0')
421 drm_mode_set_name(mode);
422
423 mode->type |= DRM_MODE_TYPE_PREFERRED;
424 drm_mode_probed_add(connector, mode);
425
426 if (mode->width_mm) {
427 connector->display_info.width_mm = mode->width_mm;
428 connector->display_info.height_mm = mode->height_mm;
429 }
430
431 return 1;
432}
433
434static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
435 .get_modes = mipi_dbi_connector_get_modes,
436};
437
438static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
439 .reset = drm_atomic_helper_connector_reset,
440 .fill_modes = drm_helper_probe_single_connector_modes,
441 .destroy = drm_connector_cleanup,
442 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
443 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
444};
445
446static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
447 unsigned int rotation)
448{
449 if (rotation == 0 || rotation == 180) {
450 return 0;
451 } else if (rotation == 90 || rotation == 270) {
452 swap(mode->hdisplay, mode->vdisplay);
453 swap(mode->hsync_start, mode->vsync_start);
454 swap(mode->hsync_end, mode->vsync_end);
455 swap(mode->htotal, mode->vtotal);
456 swap(mode->width_mm, mode->height_mm);
457 return 0;
458 } else {
459 return -EINVAL;
460 }
461}
462
463static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
464 .fb_create = drm_gem_fb_create_with_dirty,
465 .atomic_check = drm_atomic_helper_check,
466 .atomic_commit = drm_atomic_helper_commit,
467};
468
469static const uint32_t mipi_dbi_formats[] = {
470 DRM_FORMAT_RGB565,
471 DRM_FORMAT_XRGB8888,
472};
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497int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
498 const struct drm_simple_display_pipe_funcs *funcs,
499 const uint32_t *formats, unsigned int format_count,
500 const struct drm_display_mode *mode,
501 unsigned int rotation, size_t tx_buf_size)
502{
503 static const uint64_t modifiers[] = {
504 DRM_FORMAT_MOD_LINEAR,
505 DRM_FORMAT_MOD_INVALID
506 };
507 struct drm_device *drm = &dbidev->drm;
508 int ret;
509
510 if (!dbidev->dbi.command)
511 return -EINVAL;
512
513 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
514 if (!dbidev->tx_buf)
515 return -ENOMEM;
516
517 drm_mode_copy(&dbidev->mode, mode);
518 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
519 if (ret) {
520 DRM_ERROR("Illegal rotation value %u\n", rotation);
521 return -EINVAL;
522 }
523
524 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
525 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
526 DRM_MODE_CONNECTOR_SPI);
527 if (ret)
528 return ret;
529
530 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
531 modifiers, &dbidev->connector);
532 if (ret)
533 return ret;
534
535 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
536
537 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
538 drm->mode_config.min_width = dbidev->mode.hdisplay;
539 drm->mode_config.max_width = dbidev->mode.hdisplay;
540 drm->mode_config.min_height = dbidev->mode.vdisplay;
541 drm->mode_config.max_height = dbidev->mode.vdisplay;
542 dbidev->rotation = rotation;
543
544 DRM_DEBUG_KMS("rotation = %u\n", rotation);
545
546 return 0;
547}
548EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
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567int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
568 const struct drm_simple_display_pipe_funcs *funcs,
569 const struct drm_display_mode *mode, unsigned int rotation)
570{
571 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
572
573 dbidev->drm.mode_config.preferred_depth = 16;
574
575 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
576 ARRAY_SIZE(mipi_dbi_formats), mode,
577 rotation, bufsize);
578}
579EXPORT_SYMBOL(mipi_dbi_dev_init);
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589void mipi_dbi_release(struct drm_device *drm)
590{
591 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(drm);
592
593 DRM_DEBUG_DRIVER("\n");
594
595 drm_mode_config_cleanup(drm);
596 drm_dev_fini(drm);
597 kfree(dbidev);
598}
599EXPORT_SYMBOL(mipi_dbi_release);
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607void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
608{
609 if (!dbi->reset)
610 return;
611
612 gpiod_set_value_cansleep(dbi->reset, 0);
613 usleep_range(20, 1000);
614 gpiod_set_value_cansleep(dbi->reset, 1);
615 msleep(120);
616}
617EXPORT_SYMBOL(mipi_dbi_hw_reset);
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631bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
632{
633 u8 val;
634
635 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
636 return false;
637
638 val &= ~DCS_POWER_MODE_RESERVED_MASK;
639
640
641 if (val != (DCS_POWER_MODE_DISPLAY |
642 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
643 return false;
644
645 DRM_DEBUG_DRIVER("Display is ON\n");
646
647 return true;
648}
649EXPORT_SYMBOL(mipi_dbi_display_is_on);
650
651static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
652{
653 struct device *dev = dbidev->drm.dev;
654 struct mipi_dbi *dbi = &dbidev->dbi;
655 int ret;
656
657 if (dbidev->regulator) {
658 ret = regulator_enable(dbidev->regulator);
659 if (ret) {
660 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
661 return ret;
662 }
663 }
664
665 if (cond && mipi_dbi_display_is_on(dbi))
666 return 1;
667
668 mipi_dbi_hw_reset(dbi);
669 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
670 if (ret) {
671 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
672 if (dbidev->regulator)
673 regulator_disable(dbidev->regulator);
674 return ret;
675 }
676
677
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679
680
681
682 if (dbi->reset)
683 usleep_range(5000, 20000);
684 else
685 msleep(120);
686
687 return 0;
688}
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699
700int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
701{
702 return mipi_dbi_poweron_reset_conditional(dbidev, false);
703}
704EXPORT_SYMBOL(mipi_dbi_poweron_reset);
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718int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
719{
720 return mipi_dbi_poweron_reset_conditional(dbidev, true);
721}
722EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
723
724#if IS_ENABLED(CONFIG_SPI)
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735u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
736{
737 if (len > 64)
738 return 0;
739
740 return min_t(u32, 10000000, spi->max_speed_hz);
741}
742EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
743
744static bool mipi_dbi_machine_little_endian(void)
745{
746#if defined(__LITTLE_ENDIAN)
747 return true;
748#else
749 return false;
750#endif
751}
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771static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
772 const void *buf, size_t len,
773 unsigned int bpw)
774{
775 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
776 size_t chunk, max_chunk = dbi->tx_buf9_len;
777 struct spi_device *spi = dbi->spi;
778 struct spi_transfer tr = {
779 .tx_buf = dbi->tx_buf9,
780 .bits_per_word = 8,
781 };
782 struct spi_message m;
783 const u8 *src = buf;
784 int i, ret;
785 u8 *dst;
786
787 if (drm_debug_enabled(DRM_UT_DRIVER))
788 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
789 __func__, dc, max_chunk);
790
791 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
792 spi_message_init_with_transfers(&m, &tr, 1);
793
794 if (!dc) {
795 if (WARN_ON_ONCE(len != 1))
796 return -EINVAL;
797
798
799 dst = dbi->tx_buf9;
800 memset(dst, 0, 9);
801 dst[8] = *src;
802 tr.len = 9;
803
804 return spi_sync(spi, &m);
805 }
806
807
808 max_chunk = max_chunk / 9 * 8;
809
810 max_chunk = min(max_chunk, len);
811
812 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
813
814 while (len) {
815 size_t added = 0;
816
817 chunk = min(len, max_chunk);
818 len -= chunk;
819 dst = dbi->tx_buf9;
820
821 if (chunk < 8) {
822 u8 val, carry = 0;
823
824
825 memset(dst, 0, 9);
826
827 if (swap_bytes) {
828 for (i = 1; i < (chunk + 1); i++) {
829 val = src[1];
830 *dst++ = carry | BIT(8 - i) | (val >> i);
831 carry = val << (8 - i);
832 i++;
833 val = src[0];
834 *dst++ = carry | BIT(8 - i) | (val >> i);
835 carry = val << (8 - i);
836 src += 2;
837 }
838 *dst++ = carry;
839 } else {
840 for (i = 1; i < (chunk + 1); i++) {
841 val = *src++;
842 *dst++ = carry | BIT(8 - i) | (val >> i);
843 carry = val << (8 - i);
844 }
845 *dst++ = carry;
846 }
847
848 chunk = 8;
849 added = 1;
850 } else {
851 for (i = 0; i < chunk; i += 8) {
852 if (swap_bytes) {
853 *dst++ = BIT(7) | (src[1] >> 1);
854 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
855 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
856 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
857 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
858 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
859 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
860 *dst++ = (src[7] << 1) | BIT(0);
861 *dst++ = src[6];
862 } else {
863 *dst++ = BIT(7) | (src[0] >> 1);
864 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
865 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
866 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
867 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
868 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
869 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
870 *dst++ = (src[6] << 1) | BIT(0);
871 *dst++ = src[7];
872 }
873
874 src += 8;
875 added++;
876 }
877 }
878
879 tr.len = chunk + added;
880
881 ret = spi_sync(spi, &m);
882 if (ret)
883 return ret;
884 }
885
886 return 0;
887}
888
889static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
890 const void *buf, size_t len,
891 unsigned int bpw)
892{
893 struct spi_device *spi = dbi->spi;
894 struct spi_transfer tr = {
895 .bits_per_word = 9,
896 };
897 const u16 *src16 = buf;
898 const u8 *src8 = buf;
899 struct spi_message m;
900 size_t max_chunk;
901 u16 *dst16;
902 int ret;
903
904 if (!spi_is_bpw_supported(spi, 9))
905 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
906
907 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
908 max_chunk = dbi->tx_buf9_len;
909 dst16 = dbi->tx_buf9;
910
911 if (drm_debug_enabled(DRM_UT_DRIVER))
912 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
913 __func__, dc, max_chunk);
914
915 max_chunk = min(max_chunk / 2, len);
916
917 spi_message_init_with_transfers(&m, &tr, 1);
918 tr.tx_buf = dst16;
919
920 while (len) {
921 size_t chunk = min(len, max_chunk);
922 unsigned int i;
923
924 if (bpw == 16 && mipi_dbi_machine_little_endian()) {
925 for (i = 0; i < (chunk * 2); i += 2) {
926 dst16[i] = *src16 >> 8;
927 dst16[i + 1] = *src16++ & 0xFF;
928 if (dc) {
929 dst16[i] |= 0x0100;
930 dst16[i + 1] |= 0x0100;
931 }
932 }
933 } else {
934 for (i = 0; i < chunk; i++) {
935 dst16[i] = *src8++;
936 if (dc)
937 dst16[i] |= 0x0100;
938 }
939 }
940
941 tr.len = chunk;
942 len -= chunk;
943
944 ret = spi_sync(spi, &m);
945 if (ret)
946 return ret;
947 }
948
949 return 0;
950}
951
952static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
953 u8 *parameters, size_t num)
954{
955 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
956 int ret;
957
958 if (mipi_dbi_command_is_read(dbi, *cmd))
959 return -EOPNOTSUPP;
960
961 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
962
963 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
964 if (ret || !num)
965 return ret;
966
967 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
968}
969
970
971
972static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
973 u8 *data, size_t len)
974{
975 struct spi_device *spi = dbi->spi;
976 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
977 spi->max_speed_hz / 2);
978 struct spi_transfer tr[2] = {
979 {
980 .speed_hz = speed_hz,
981 .tx_buf = cmd,
982 .len = 1,
983 }, {
984 .speed_hz = speed_hz,
985 .len = len,
986 },
987 };
988 struct spi_message m;
989 u8 *buf;
990 int ret;
991
992 if (!len)
993 return -EINVAL;
994
995
996
997
998
999 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1000 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1001 if (!(len == 3 || len == 4))
1002 return -EINVAL;
1003
1004 tr[1].len = len + 1;
1005 }
1006
1007 buf = kmalloc(tr[1].len, GFP_KERNEL);
1008 if (!buf)
1009 return -ENOMEM;
1010
1011 tr[1].rx_buf = buf;
1012 gpiod_set_value_cansleep(dbi->dc, 0);
1013
1014 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1015 ret = spi_sync(spi, &m);
1016 if (ret)
1017 goto err_free;
1018
1019 if (tr[1].len == len) {
1020 memcpy(data, buf, len);
1021 } else {
1022 unsigned int i;
1023
1024 for (i = 0; i < len; i++)
1025 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1026 }
1027
1028 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1029
1030err_free:
1031 kfree(buf);
1032
1033 return ret;
1034}
1035
1036static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1037 u8 *par, size_t num)
1038{
1039 struct spi_device *spi = dbi->spi;
1040 unsigned int bpw = 8;
1041 u32 speed_hz;
1042 int ret;
1043
1044 if (mipi_dbi_command_is_read(dbi, *cmd))
1045 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1046
1047 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1048
1049 gpiod_set_value_cansleep(dbi->dc, 0);
1050 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1051 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1052 if (ret || !num)
1053 return ret;
1054
1055 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1056 bpw = 16;
1057
1058 gpiod_set_value_cansleep(dbi->dc, 1);
1059 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1060
1061 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1062}
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1087 struct gpio_desc *dc)
1088{
1089 struct device *dev = &spi->dev;
1090 int ret;
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102 if (!dev->coherent_dma_mask) {
1103 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1104 if (ret) {
1105 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1106 return ret;
1107 }
1108 }
1109
1110 dbi->spi = spi;
1111 dbi->read_commands = mipi_dbi_dcs_read_commands;
1112
1113 if (dc) {
1114 dbi->command = mipi_dbi_typec3_command;
1115 dbi->dc = dc;
1116 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1117 dbi->swap_bytes = true;
1118 } else {
1119 dbi->command = mipi_dbi_typec1_command;
1120 dbi->tx_buf9_len = SZ_16K;
1121 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1122 if (!dbi->tx_buf9)
1123 return -ENOMEM;
1124 }
1125
1126 mutex_init(&dbi->cmdlock);
1127
1128 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1129
1130 return 0;
1131}
1132EXPORT_SYMBOL(mipi_dbi_spi_init);
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1149 u8 bpw, const void *buf, size_t len)
1150{
1151 size_t max_chunk = spi_max_transfer_size(spi);
1152 struct spi_transfer tr = {
1153 .bits_per_word = bpw,
1154 .speed_hz = speed_hz,
1155 };
1156 struct spi_message m;
1157 size_t chunk;
1158 int ret;
1159
1160 spi_message_init_with_transfers(&m, &tr, 1);
1161
1162 while (len) {
1163 chunk = min(len, max_chunk);
1164
1165 tr.tx_buf = buf;
1166 tr.len = chunk;
1167 buf += chunk;
1168 len -= chunk;
1169
1170 ret = spi_sync(spi, &m);
1171 if (ret)
1172 return ret;
1173 }
1174
1175 return 0;
1176}
1177EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1178
1179#endif
1180
1181#ifdef CONFIG_DEBUG_FS
1182
1183static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1184 const char __user *ubuf,
1185 size_t count, loff_t *ppos)
1186{
1187 struct seq_file *m = file->private_data;
1188 struct mipi_dbi_dev *dbidev = m->private;
1189 u8 val, cmd = 0, parameters[64];
1190 char *buf, *pos, *token;
1191 int i, ret, idx;
1192
1193 if (!drm_dev_enter(&dbidev->drm, &idx))
1194 return -ENODEV;
1195
1196 buf = memdup_user_nul(ubuf, count);
1197 if (IS_ERR(buf)) {
1198 ret = PTR_ERR(buf);
1199 goto err_exit;
1200 }
1201
1202
1203 for (i = count - 1; i > 0; i--)
1204 if (isspace(buf[i]))
1205 buf[i] = '\0';
1206 else
1207 break;
1208 i = 0;
1209 pos = buf;
1210 while (pos) {
1211 token = strsep(&pos, " ");
1212 if (!token) {
1213 ret = -EINVAL;
1214 goto err_free;
1215 }
1216
1217 ret = kstrtou8(token, 16, &val);
1218 if (ret < 0)
1219 goto err_free;
1220
1221 if (token == buf)
1222 cmd = val;
1223 else
1224 parameters[i++] = val;
1225
1226 if (i == 64) {
1227 ret = -E2BIG;
1228 goto err_free;
1229 }
1230 }
1231
1232 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1233
1234err_free:
1235 kfree(buf);
1236err_exit:
1237 drm_dev_exit(idx);
1238
1239 return ret < 0 ? ret : count;
1240}
1241
1242static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1243{
1244 struct mipi_dbi_dev *dbidev = m->private;
1245 struct mipi_dbi *dbi = &dbidev->dbi;
1246 u8 cmd, val[4];
1247 int ret, idx;
1248 size_t len;
1249
1250 if (!drm_dev_enter(&dbidev->drm, &idx))
1251 return -ENODEV;
1252
1253 for (cmd = 0; cmd < 255; cmd++) {
1254 if (!mipi_dbi_command_is_read(dbi, cmd))
1255 continue;
1256
1257 switch (cmd) {
1258 case MIPI_DCS_READ_MEMORY_START:
1259 case MIPI_DCS_READ_MEMORY_CONTINUE:
1260 len = 2;
1261 break;
1262 case MIPI_DCS_GET_DISPLAY_ID:
1263 len = 3;
1264 break;
1265 case MIPI_DCS_GET_DISPLAY_STATUS:
1266 len = 4;
1267 break;
1268 default:
1269 len = 1;
1270 break;
1271 }
1272
1273 seq_printf(m, "%02x: ", cmd);
1274 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1275 if (ret) {
1276 seq_puts(m, "XX\n");
1277 continue;
1278 }
1279 seq_printf(m, "%*phN\n", (int)len, val);
1280 }
1281
1282 drm_dev_exit(idx);
1283
1284 return 0;
1285}
1286
1287static int mipi_dbi_debugfs_command_open(struct inode *inode,
1288 struct file *file)
1289{
1290 return single_open(file, mipi_dbi_debugfs_command_show,
1291 inode->i_private);
1292}
1293
1294static const struct file_operations mipi_dbi_debugfs_command_fops = {
1295 .owner = THIS_MODULE,
1296 .open = mipi_dbi_debugfs_command_open,
1297 .read = seq_read,
1298 .llseek = seq_lseek,
1299 .release = single_release,
1300 .write = mipi_dbi_debugfs_command_write,
1301};
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314int mipi_dbi_debugfs_init(struct drm_minor *minor)
1315{
1316 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1317 umode_t mode = S_IFREG | S_IWUSR;
1318
1319 if (dbidev->dbi.read_commands)
1320 mode |= S_IRUGO;
1321 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1322 &mipi_dbi_debugfs_command_fops);
1323
1324 return 0;
1325}
1326EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1327
1328#endif
1329
1330MODULE_LICENSE("GPL");
1331