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25#include "intel_color.h"
26#include "intel_display_types.h"
27
28#define CTM_COEFF_SIGN (1ULL << 63)
29
30#define CTM_COEFF_1_0 (1ULL << 32)
31#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
32#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
33#define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
34#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
35#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
36#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
37
38#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
39
40#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
41#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
42
43#define LEGACY_LUT_LENGTH 256
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68
69#define ILK_CSC_COEFF_FP(coeff, fbits) \
70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
71
72#define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
73#define ILK_CSC_COEFF_1_0 0x7800
74
75#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
76
77
78static const u16 ilk_csc_off_zero[3] = {};
79
80
81static const u16 ilk_csc_coeff_identity[9] = {
82 ILK_CSC_COEFF_1_0, 0, 0,
83 0, ILK_CSC_COEFF_1_0, 0,
84 0, 0, ILK_CSC_COEFF_1_0,
85};
86
87
88static const u16 ilk_csc_postoff_limited_range[3] = {
89 ILK_CSC_POSTOFF_LIMITED_RANGE,
90 ILK_CSC_POSTOFF_LIMITED_RANGE,
91 ILK_CSC_POSTOFF_LIMITED_RANGE,
92};
93
94
95static const u16 ilk_csc_coeff_limited_range[9] = {
96 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
97 0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
98 0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
99};
100
101
102static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
103 0x1e08, 0x9cc0, 0xb528,
104 0x2ba8, 0x09d8, 0x37e8,
105 0xbce8, 0x9ad8, 0x1e08,
106};
107
108
109static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
110 0x0800, 0x0100, 0x0800,
111};
112
113static bool lut_is_legacy(const struct drm_property_blob *lut)
114{
115 return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
116}
117
118static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
119{
120 return !crtc_state->hw.degamma_lut &&
121 !crtc_state->hw.ctm &&
122 crtc_state->hw.gamma_lut &&
123 lut_is_legacy(crtc_state->hw.gamma_lut);
124}
125
126
127
128
129
130static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
131{
132 int i;
133
134 for (i = 0; i < 9; i++) {
135 u64 user_coeff = input[i];
136 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
137 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
138 CTM_COEFF_4_0 - 1) >> 2;
139
140
141
142
143
144
145 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
146 result[i] |= user_coeff & CTM_COEFF_SIGN;
147 }
148
149 return result;
150}
151
152static void ilk_update_pipe_csc(struct intel_crtc *crtc,
153 const u16 preoff[3],
154 const u16 coeff[9],
155 const u16 postoff[3])
156{
157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
158 enum pipe pipe = crtc->pipe;
159
160 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
163
164 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe),
165 coeff[0] << 16 | coeff[1]);
166 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
167
168 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe),
169 coeff[3] << 16 | coeff[4]);
170 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
171
172 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe),
173 coeff[6] << 16 | coeff[7]);
174 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
175
176 if (INTEL_GEN(dev_priv) >= 7) {
177 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe),
178 postoff[0]);
179 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe),
180 postoff[1]);
181 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe),
182 postoff[2]);
183 }
184}
185
186static void icl_update_output_csc(struct intel_crtc *crtc,
187 const u16 preoff[3],
188 const u16 coeff[9],
189 const u16 postoff[3])
190{
191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
192 enum pipe pipe = crtc->pipe;
193
194 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
195 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
196 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
197
198 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
199 coeff[0] << 16 | coeff[1]);
200 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
201 coeff[2] << 16);
202
203 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
204 coeff[3] << 16 | coeff[4]);
205 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
206 coeff[5] << 16);
207
208 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
209 coeff[6] << 16 | coeff[7]);
210 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
211 coeff[8] << 16);
212
213 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
214 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
215 intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
216}
217
218static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
219{
220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
221
222
223
224
225
226 return crtc_state->limited_color_range &&
227 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
228 IS_GEN_RANGE(dev_priv, 9, 10));
229}
230
231static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
232 u16 coeffs[9])
233{
234 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
235 const u64 *input;
236 u64 temp[9];
237 int i;
238
239 if (ilk_csc_limited_range(crtc_state))
240 input = ctm_mult_by_limited(temp, ctm->matrix);
241 else
242 input = ctm->matrix;
243
244
245
246
247
248 for (i = 0; i < 9; i++) {
249 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
250
251
252
253
254
255 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
256
257 coeffs[i] = 0;
258
259
260 if (CTM_COEFF_NEGATIVE(input[i]))
261 coeffs[i] |= 1 << 15;
262
263 if (abs_coeff < CTM_COEFF_0_125)
264 coeffs[i] |= (3 << 12) |
265 ILK_CSC_COEFF_FP(abs_coeff, 12);
266 else if (abs_coeff < CTM_COEFF_0_25)
267 coeffs[i] |= (2 << 12) |
268 ILK_CSC_COEFF_FP(abs_coeff, 11);
269 else if (abs_coeff < CTM_COEFF_0_5)
270 coeffs[i] |= (1 << 12) |
271 ILK_CSC_COEFF_FP(abs_coeff, 10);
272 else if (abs_coeff < CTM_COEFF_1_0)
273 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
274 else if (abs_coeff < CTM_COEFF_2_0)
275 coeffs[i] |= (7 << 12) |
276 ILK_CSC_COEFF_FP(abs_coeff, 8);
277 else
278 coeffs[i] |= (6 << 12) |
279 ILK_CSC_COEFF_FP(abs_coeff, 7);
280 }
281}
282
283static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
284{
285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
287 bool limited_color_range = ilk_csc_limited_range(crtc_state);
288
289 if (crtc_state->hw.ctm) {
290 u16 coeff[9];
291
292 ilk_csc_convert_ctm(crtc_state, coeff);
293 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
294 limited_color_range ?
295 ilk_csc_postoff_limited_range :
296 ilk_csc_off_zero);
297 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
298 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
299 ilk_csc_coeff_rgb_to_ycbcr,
300 ilk_csc_postoff_rgb_to_ycbcr);
301 } else if (limited_color_range) {
302 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
303 ilk_csc_coeff_limited_range,
304 ilk_csc_postoff_limited_range);
305 } else if (crtc_state->csc_enable) {
306
307
308
309
310
311
312 drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
313 !IS_GEMINILAKE(dev_priv));
314
315 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
316 ilk_csc_coeff_identity,
317 ilk_csc_off_zero);
318 }
319
320 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
321 crtc_state->csc_mode);
322}
323
324static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
325{
326 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
328
329 if (crtc_state->hw.ctm) {
330 u16 coeff[9];
331
332 ilk_csc_convert_ctm(crtc_state, coeff);
333 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
334 coeff, ilk_csc_off_zero);
335 }
336
337 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
338 icl_update_output_csc(crtc, ilk_csc_off_zero,
339 ilk_csc_coeff_rgb_to_ycbcr,
340 ilk_csc_postoff_rgb_to_ycbcr);
341 } else if (crtc_state->limited_color_range) {
342 icl_update_output_csc(crtc, ilk_csc_off_zero,
343 ilk_csc_coeff_limited_range,
344 ilk_csc_postoff_limited_range);
345 }
346
347 intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe),
348 crtc_state->csc_mode);
349}
350
351static void chv_load_cgm_csc(struct intel_crtc *crtc,
352 const struct drm_property_blob *blob)
353{
354 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
355 const struct drm_color_ctm *ctm = blob->data;
356 enum pipe pipe = crtc->pipe;
357 u16 coeffs[9];
358 int i;
359
360 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
361 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
362
363
364 abs_coeff += 1 << (32 - 13);
365
366 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
367
368 coeffs[i] = 0;
369
370
371 if (ctm->matrix[i] & (1ULL << 63))
372 coeffs[i] |= 1 << 15;
373
374 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
375 coeffs[i] |= (abs_coeff >> 20) & 0xfff;
376 }
377
378 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
379 coeffs[1] << 16 | coeffs[0]);
380 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
381 coeffs[3] << 16 | coeffs[2]);
382 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
383 coeffs[5] << 16 | coeffs[4]);
384 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
385 coeffs[7] << 16 | coeffs[6]);
386 intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
387 coeffs[8]);
388}
389
390
391static u32 intel_color_lut_pack(u32 val, int bit_precision)
392{
393 u32 max = 0xffff >> (16 - bit_precision);
394
395 val = clamp_val(val, 0, max);
396
397 if (bit_precision < 16)
398 val <<= 16 - bit_precision;
399
400 return val;
401}
402
403static u32 i9xx_lut_8(const struct drm_color_lut *color)
404{
405 return drm_color_lut_extract(color->red, 8) << 16 |
406 drm_color_lut_extract(color->green, 8) << 8 |
407 drm_color_lut_extract(color->blue, 8);
408}
409
410static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
411{
412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
415}
416
417
418static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
419{
420 return (color->red & 0xff) << 16 |
421 (color->green & 0xff) << 8 |
422 (color->blue & 0xff);
423}
424
425
426static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
427{
428 return (color->red >> 8) << 16 |
429 (color->green >> 8) << 8 |
430 (color->blue >> 8);
431}
432
433static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
434{
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
436 REG_FIELD_GET(PALETTE_RED_MASK, ldw);
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
441}
442
443static u16 i965_lut_11p6_max_pack(u32 val)
444{
445
446 return clamp_val(val, 0, 0xffff);
447}
448
449static u32 ilk_lut_10(const struct drm_color_lut *color)
450{
451 return drm_color_lut_extract(color->red, 10) << 20 |
452 drm_color_lut_extract(color->green, 10) << 10 |
453 drm_color_lut_extract(color->blue, 10);
454}
455
456static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
457{
458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
459 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
460 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
461}
462
463static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
464{
465 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
467 enum pipe pipe = crtc->pipe;
468 u32 val;
469
470 val = intel_de_read(dev_priv, PIPECONF(pipe));
471 val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
472 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
473 intel_de_write(dev_priv, PIPECONF(pipe), val);
474}
475
476static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
477{
478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
480 enum pipe pipe = crtc->pipe;
481 u32 val;
482
483 val = intel_de_read(dev_priv, PIPECONF(pipe));
484 val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
485 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
486 intel_de_write(dev_priv, PIPECONF(pipe), val);
487
488 ilk_load_csc_matrix(crtc_state);
489}
490
491static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
492{
493 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
494 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
495
496 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
497 crtc_state->gamma_mode);
498
499 ilk_load_csc_matrix(crtc_state);
500}
501
502static void skl_color_commit(const struct intel_crtc_state *crtc_state)
503{
504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
506 enum pipe pipe = crtc->pipe;
507 u32 val = 0;
508
509
510
511
512
513
514 if (crtc_state->gamma_enable)
515 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
516 if (crtc_state->csc_enable)
517 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
518 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val);
519
520 intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe),
521 crtc_state->gamma_mode);
522
523 if (INTEL_GEN(dev_priv) >= 11)
524 icl_load_csc_matrix(crtc_state);
525 else
526 ilk_load_csc_matrix(crtc_state);
527}
528
529static void i9xx_load_lut_8(struct intel_crtc *crtc,
530 const struct drm_property_blob *blob)
531{
532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
533 const struct drm_color_lut *lut;
534 enum pipe pipe = crtc->pipe;
535 int i;
536
537 if (!blob)
538 return;
539
540 lut = blob->data;
541
542 for (i = 0; i < 256; i++)
543 intel_de_write(dev_priv, PALETTE(pipe, i),
544 i9xx_lut_8(&lut[i]));
545}
546
547static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
548{
549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
551 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
552
553 assert_pll_enabled(dev_priv, crtc->pipe);
554
555 i9xx_load_lut_8(crtc, gamma_lut);
556}
557
558static void i965_load_lut_10p6(struct intel_crtc *crtc,
559 const struct drm_property_blob *blob)
560{
561 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
562 const struct drm_color_lut *lut = blob->data;
563 int i, lut_size = drm_color_lut_size(blob);
564 enum pipe pipe = crtc->pipe;
565
566 for (i = 0; i < lut_size - 1; i++) {
567 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0),
568 i965_lut_10p6_ldw(&lut[i]));
569 intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1),
570 i965_lut_10p6_udw(&lut[i]));
571 }
572
573 intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
574 intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
575 intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
576}
577
578static void i965_load_luts(const struct intel_crtc_state *crtc_state)
579{
580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
582 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
583
584 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
585 assert_dsi_pll_enabled(dev_priv);
586 else
587 assert_pll_enabled(dev_priv, crtc->pipe);
588
589 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
590 i9xx_load_lut_8(crtc, gamma_lut);
591 else
592 i965_load_lut_10p6(crtc, gamma_lut);
593}
594
595static void ilk_load_lut_8(struct intel_crtc *crtc,
596 const struct drm_property_blob *blob)
597{
598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
599 const struct drm_color_lut *lut;
600 enum pipe pipe = crtc->pipe;
601 int i;
602
603 if (!blob)
604 return;
605
606 lut = blob->data;
607
608 for (i = 0; i < 256; i++)
609 intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
610 i9xx_lut_8(&lut[i]));
611}
612
613static void ilk_load_lut_10(struct intel_crtc *crtc,
614 const struct drm_property_blob *blob)
615{
616 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
617 const struct drm_color_lut *lut = blob->data;
618 int i, lut_size = drm_color_lut_size(blob);
619 enum pipe pipe = crtc->pipe;
620
621 for (i = 0; i < lut_size; i++)
622 intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
623 ilk_lut_10(&lut[i]));
624}
625
626static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
627{
628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
629 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
630
631 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
632 ilk_load_lut_8(crtc, gamma_lut);
633 else
634 ilk_load_lut_10(crtc, gamma_lut);
635}
636
637static int ivb_lut_10_size(u32 prec_index)
638{
639 if (prec_index & PAL_PREC_SPLIT_MODE)
640 return 512;
641 else
642 return 1024;
643}
644
645
646
647
648
649
650static void ivb_load_lut_10(struct intel_crtc *crtc,
651 const struct drm_property_blob *blob,
652 u32 prec_index)
653{
654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
655 int hw_lut_size = ivb_lut_10_size(prec_index);
656 const struct drm_color_lut *lut = blob->data;
657 int i, lut_size = drm_color_lut_size(blob);
658 enum pipe pipe = crtc->pipe;
659
660 for (i = 0; i < hw_lut_size; i++) {
661
662 const struct drm_color_lut *entry =
663 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
664
665 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++);
666 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
667 ilk_lut_10(entry));
668 }
669
670
671
672
673
674 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
675}
676
677
678static void bdw_load_lut_10(struct intel_crtc *crtc,
679 const struct drm_property_blob *blob,
680 u32 prec_index)
681{
682 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
683 int hw_lut_size = ivb_lut_10_size(prec_index);
684 const struct drm_color_lut *lut = blob->data;
685 int i, lut_size = drm_color_lut_size(blob);
686 enum pipe pipe = crtc->pipe;
687
688 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
689 prec_index | PAL_PREC_AUTO_INCREMENT);
690
691 for (i = 0; i < hw_lut_size; i++) {
692
693 const struct drm_color_lut *entry =
694 &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
695
696 intel_de_write(dev_priv, PREC_PAL_DATA(pipe),
697 ilk_lut_10(entry));
698 }
699
700
701
702
703
704 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
705}
706
707static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
708{
709 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
710 struct intel_dsb *dsb = intel_dsb_get(crtc);
711 enum pipe pipe = crtc->pipe;
712
713
714 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
715 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
716 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
717
718
719
720
721
722
723 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
724 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
725 1 << 16);
726 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
727 1 << 16);
728 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
729 1 << 16);
730 }
731
732 intel_dsb_put(dsb);
733}
734
735static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
736{
737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
738 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
739 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
740
741 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
742 ilk_load_lut_8(crtc, gamma_lut);
743 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
744 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
745 PAL_PREC_INDEX_VALUE(0));
746 ivb_load_lut_ext_max(crtc);
747 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
748 PAL_PREC_INDEX_VALUE(512));
749 } else {
750 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
751
752 ivb_load_lut_10(crtc, blob,
753 PAL_PREC_INDEX_VALUE(0));
754 ivb_load_lut_ext_max(crtc);
755 }
756}
757
758static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
759{
760 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
761 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
762 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
763
764 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
765 ilk_load_lut_8(crtc, gamma_lut);
766 } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
767 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
768 PAL_PREC_INDEX_VALUE(0));
769 ivb_load_lut_ext_max(crtc);
770 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
771 PAL_PREC_INDEX_VALUE(512));
772 } else {
773 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
774
775 bdw_load_lut_10(crtc, blob,
776 PAL_PREC_INDEX_VALUE(0));
777 ivb_load_lut_ext_max(crtc);
778 }
779}
780
781static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
782{
783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
785 enum pipe pipe = crtc->pipe;
786 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
787 const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
788
789
790
791
792
793
794 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
795 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
796 PRE_CSC_GAMC_AUTO_INCREMENT);
797
798 for (i = 0; i < lut_size; i++) {
799
800
801
802
803
804
805
806
807
808
809
810
811
812 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
813 lut[i].green);
814 }
815
816
817 while (i++ < 35)
818 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
819}
820
821static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
822{
823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
825 enum pipe pipe = crtc->pipe;
826 int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
827
828
829
830
831
832
833 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
834 intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
835 PRE_CSC_GAMC_AUTO_INCREMENT);
836
837 for (i = 0; i < lut_size; i++) {
838 u32 v = (i << 16) / (lut_size - 1);
839
840 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v);
841 }
842
843
844 while (i++ < 35)
845 intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
846}
847
848static void glk_load_luts(const struct intel_crtc_state *crtc_state)
849{
850 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
852
853
854
855
856
857
858
859
860
861 if (crtc_state->hw.degamma_lut)
862 glk_load_degamma_lut(crtc_state);
863 else
864 glk_load_degamma_lut_linear(crtc_state);
865
866 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
867 ilk_load_lut_8(crtc, gamma_lut);
868 } else {
869 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
870 ivb_load_lut_ext_max(crtc);
871 }
872}
873
874
875static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
876{
877 return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
878 (color->blue >> 6);
879}
880
881
882static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
883{
884 return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
885 (color->blue & 0x3f) << 4;
886}
887
888static void
889icl_load_gcmax(const struct intel_crtc_state *crtc_state,
890 const struct drm_color_lut *color)
891{
892 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
893 struct intel_dsb *dsb = intel_dsb_get(crtc);
894 enum pipe pipe = crtc->pipe;
895
896
897 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
898 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
899 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
900 intel_dsb_put(dsb);
901}
902
903static void
904icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
905{
906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
907 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
908 const struct drm_color_lut *lut = blob->data;
909 struct intel_dsb *dsb = intel_dsb_get(crtc);
910 enum pipe pipe = crtc->pipe;
911 int i;
912
913
914
915
916
917
918
919
920 intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
921 PAL_PREC_AUTO_INCREMENT);
922
923 for (i = 0; i < 9; i++) {
924 const struct drm_color_lut *entry = &lut[i];
925
926 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
927 ilk_lut_12p4_ldw(entry));
928 intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
929 ilk_lut_12p4_udw(entry));
930 }
931
932 intel_dsb_put(dsb);
933}
934
935static void
936icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
937{
938 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
939 const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
940 const struct drm_color_lut *lut = blob->data;
941 const struct drm_color_lut *entry;
942 struct intel_dsb *dsb = intel_dsb_get(crtc);
943 enum pipe pipe = crtc->pipe;
944 int i;
945
946
947
948
949
950
951
952
953
954
955
956 intel_dsb_reg_write(dsb, PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
957 for (i = 1; i < 257; i++) {
958 entry = &lut[i * 8];
959 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
960 ilk_lut_12p4_ldw(entry));
961 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
962 ilk_lut_12p4_udw(entry));
963 }
964
965
966
967
968
969
970
971
972
973
974
975
976
977 for (i = 0; i < 256; i++) {
978 entry = &lut[i * 8 * 128];
979 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
980 ilk_lut_12p4_ldw(entry));
981 intel_dsb_indexed_reg_write(dsb, PREC_PAL_DATA(pipe),
982 ilk_lut_12p4_udw(entry));
983 }
984
985
986 entry = &lut[256 * 8 * 128];
987 icl_load_gcmax(crtc_state, entry);
988 ivb_load_lut_ext_max(crtc);
989 intel_dsb_put(dsb);
990}
991
992static void icl_load_luts(const struct intel_crtc_state *crtc_state)
993{
994 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
995 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
996 struct intel_dsb *dsb = intel_dsb_get(crtc);
997
998 if (crtc_state->hw.degamma_lut)
999 glk_load_degamma_lut(crtc_state);
1000
1001 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1002 case GAMMA_MODE_MODE_8BIT:
1003 ilk_load_lut_8(crtc, gamma_lut);
1004 break;
1005 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
1006 icl_program_gamma_superfine_segment(crtc_state);
1007 icl_program_gamma_multi_segment(crtc_state);
1008 break;
1009 default:
1010 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
1011 ivb_load_lut_ext_max(crtc);
1012 }
1013
1014 intel_dsb_commit(dsb);
1015 intel_dsb_put(dsb);
1016}
1017
1018static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
1019{
1020 return drm_color_lut_extract(color->green, 14) << 16 |
1021 drm_color_lut_extract(color->blue, 14);
1022}
1023
1024static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
1025{
1026 return drm_color_lut_extract(color->red, 14);
1027}
1028
1029static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1030{
1031 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
1032 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
1033 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
1034}
1035
1036static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1037 const struct drm_property_blob *blob)
1038{
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 const struct drm_color_lut *lut = blob->data;
1041 int i, lut_size = drm_color_lut_size(blob);
1042 enum pipe pipe = crtc->pipe;
1043
1044 for (i = 0; i < lut_size; i++) {
1045 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0),
1046 chv_cgm_degamma_ldw(&lut[i]));
1047 intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1),
1048 chv_cgm_degamma_udw(&lut[i]));
1049 }
1050}
1051
1052static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1053{
1054 return drm_color_lut_extract(color->green, 10) << 16 |
1055 drm_color_lut_extract(color->blue, 10);
1056}
1057
1058static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1059{
1060 return drm_color_lut_extract(color->red, 10);
1061}
1062
1063static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1064 const struct drm_property_blob *blob)
1065{
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 const struct drm_color_lut *lut = blob->data;
1068 int i, lut_size = drm_color_lut_size(blob);
1069 enum pipe pipe = crtc->pipe;
1070
1071 for (i = 0; i < lut_size; i++) {
1072 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0),
1073 chv_cgm_gamma_ldw(&lut[i]));
1074 intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1),
1075 chv_cgm_gamma_udw(&lut[i]));
1076 }
1077}
1078
1079static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1080{
1081 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1082 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1083 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1084 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1085 const struct drm_property_blob *ctm = crtc_state->hw.ctm;
1086
1087 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1088 chv_load_cgm_csc(crtc, ctm);
1089
1090 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1091 chv_load_cgm_degamma(crtc, degamma_lut);
1092
1093 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1094 chv_load_cgm_gamma(crtc, gamma_lut);
1095 else
1096 i965_load_luts(crtc_state);
1097
1098 intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
1099 crtc_state->cgm_mode);
1100}
1101
1102void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1103{
1104 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1105
1106 dev_priv->display.load_luts(crtc_state);
1107}
1108
1109void intel_color_commit(const struct intel_crtc_state *crtc_state)
1110{
1111 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1112
1113 dev_priv->display.color_commit(crtc_state);
1114}
1115
1116static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1117{
1118 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1119 struct intel_atomic_state *state =
1120 to_intel_atomic_state(new_crtc_state->uapi.state);
1121 const struct intel_crtc_state *old_crtc_state =
1122 intel_atomic_get_old_crtc_state(state, crtc);
1123
1124 return !old_crtc_state->hw.gamma_lut &&
1125 !old_crtc_state->hw.degamma_lut;
1126}
1127
1128static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1129{
1130 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1131 struct intel_atomic_state *state =
1132 to_intel_atomic_state(new_crtc_state->uapi.state);
1133 const struct intel_crtc_state *old_crtc_state =
1134 intel_atomic_get_old_crtc_state(state, crtc);
1135
1136
1137
1138
1139
1140
1141 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1142 return false;
1143
1144 return !old_crtc_state->hw.gamma_lut;
1145}
1146
1147static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1148{
1149 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1150 struct intel_atomic_state *state =
1151 to_intel_atomic_state(new_crtc_state->uapi.state);
1152 const struct intel_crtc_state *old_crtc_state =
1153 intel_atomic_get_old_crtc_state(state, crtc);
1154
1155
1156
1157
1158
1159
1160
1161 return !old_crtc_state->csc_enable &&
1162 !old_crtc_state->hw.gamma_lut;
1163}
1164
1165int intel_color_check(struct intel_crtc_state *crtc_state)
1166{
1167 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1168
1169 return dev_priv->display.color_check(crtc_state);
1170}
1171
1172void intel_color_get_config(struct intel_crtc_state *crtc_state)
1173{
1174 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1175
1176 if (dev_priv->display.read_luts)
1177 dev_priv->display.read_luts(crtc_state);
1178}
1179
1180static bool need_plane_update(struct intel_plane *plane,
1181 const struct intel_crtc_state *crtc_state)
1182{
1183 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1184
1185
1186
1187
1188
1189
1190 return crtc_state->active_planes & BIT(plane->id) ||
1191 (INTEL_GEN(dev_priv) < 9 &&
1192 plane->id == PLANE_PRIMARY);
1193}
1194
1195static int
1196intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1197{
1198 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1199 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1200 struct intel_atomic_state *state =
1201 to_intel_atomic_state(new_crtc_state->uapi.state);
1202 const struct intel_crtc_state *old_crtc_state =
1203 intel_atomic_get_old_crtc_state(state, crtc);
1204 struct intel_plane *plane;
1205
1206 if (!new_crtc_state->hw.active ||
1207 drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1208 return 0;
1209
1210 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1211 new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1212 return 0;
1213
1214 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1215 struct intel_plane_state *plane_state;
1216
1217 if (!need_plane_update(plane, new_crtc_state))
1218 continue;
1219
1220 plane_state = intel_atomic_get_plane_state(state, plane);
1221 if (IS_ERR(plane_state))
1222 return PTR_ERR(plane_state);
1223
1224 new_crtc_state->update_planes |= BIT(plane->id);
1225 }
1226
1227 return 0;
1228}
1229
1230static int check_lut_size(const struct drm_property_blob *lut, int expected)
1231{
1232 int len;
1233
1234 if (!lut)
1235 return 0;
1236
1237 len = drm_color_lut_size(lut);
1238 if (len != expected) {
1239 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1240 len, expected);
1241 return -EINVAL;
1242 }
1243
1244 return 0;
1245}
1246
1247static int check_luts(const struct intel_crtc_state *crtc_state)
1248{
1249 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1250 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1251 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1252 int gamma_length, degamma_length;
1253 u32 gamma_tests, degamma_tests;
1254
1255
1256 if (crtc_state_is_legacy_gamma(crtc_state))
1257 return 0;
1258
1259
1260 if (crtc_state->c8_planes) {
1261 drm_dbg_kms(&dev_priv->drm,
1262 "C8 pixelformat requires the legacy LUT\n");
1263 return -EINVAL;
1264 }
1265
1266 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1267 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1268 degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1269 gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1270
1271 if (check_lut_size(degamma_lut, degamma_length) ||
1272 check_lut_size(gamma_lut, gamma_length))
1273 return -EINVAL;
1274
1275 if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1276 drm_color_lut_check(gamma_lut, gamma_tests))
1277 return -EINVAL;
1278
1279 return 0;
1280}
1281
1282static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1283{
1284 if (!crtc_state->gamma_enable ||
1285 crtc_state_is_legacy_gamma(crtc_state))
1286 return GAMMA_MODE_MODE_8BIT;
1287 else
1288 return GAMMA_MODE_MODE_10BIT;
1289}
1290
1291static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1292{
1293 int ret;
1294
1295 ret = check_luts(crtc_state);
1296 if (ret)
1297 return ret;
1298
1299 crtc_state->gamma_enable =
1300 crtc_state->hw.gamma_lut &&
1301 !crtc_state->c8_planes;
1302
1303 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1304
1305 ret = intel_color_add_affected_planes(crtc_state);
1306 if (ret)
1307 return ret;
1308
1309 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1310
1311 return 0;
1312}
1313
1314static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1315{
1316 u32 cgm_mode = 0;
1317
1318 if (crtc_state_is_legacy_gamma(crtc_state))
1319 return 0;
1320
1321 if (crtc_state->hw.degamma_lut)
1322 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1323 if (crtc_state->hw.ctm)
1324 cgm_mode |= CGM_PIPE_MODE_CSC;
1325 if (crtc_state->hw.gamma_lut)
1326 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1327
1328 return cgm_mode;
1329}
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339static int chv_color_check(struct intel_crtc_state *crtc_state)
1340{
1341 int ret;
1342
1343 ret = check_luts(crtc_state);
1344 if (ret)
1345 return ret;
1346
1347
1348
1349
1350
1351 crtc_state->gamma_enable =
1352 crtc_state_is_legacy_gamma(crtc_state) &&
1353 !crtc_state->c8_planes;
1354
1355 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1356
1357 crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1358
1359 ret = intel_color_add_affected_planes(crtc_state);
1360 if (ret)
1361 return ret;
1362
1363 crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1364
1365 return 0;
1366}
1367
1368static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1369{
1370 if (!crtc_state->gamma_enable ||
1371 crtc_state_is_legacy_gamma(crtc_state))
1372 return GAMMA_MODE_MODE_8BIT;
1373 else
1374 return GAMMA_MODE_MODE_10BIT;
1375}
1376
1377static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1378{
1379
1380
1381
1382
1383
1384
1385 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1386 return CSC_BLACK_SCREEN_OFFSET;
1387
1388 return CSC_MODE_YUV_TO_RGB |
1389 CSC_POSITION_BEFORE_GAMMA;
1390}
1391
1392static int ilk_color_check(struct intel_crtc_state *crtc_state)
1393{
1394 int ret;
1395
1396 ret = check_luts(crtc_state);
1397 if (ret)
1398 return ret;
1399
1400 crtc_state->gamma_enable =
1401 crtc_state->hw.gamma_lut &&
1402 !crtc_state->c8_planes;
1403
1404
1405
1406
1407
1408 crtc_state->csc_enable =
1409 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1410
1411 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1412
1413 crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1414
1415 ret = intel_color_add_affected_planes(crtc_state);
1416 if (ret)
1417 return ret;
1418
1419 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1420
1421 return 0;
1422}
1423
1424static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1425{
1426 if (!crtc_state->gamma_enable ||
1427 crtc_state_is_legacy_gamma(crtc_state))
1428 return GAMMA_MODE_MODE_8BIT;
1429 else if (crtc_state->hw.gamma_lut &&
1430 crtc_state->hw.degamma_lut)
1431 return GAMMA_MODE_MODE_SPLIT;
1432 else
1433 return GAMMA_MODE_MODE_10BIT;
1434}
1435
1436static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1437{
1438 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1439
1440
1441
1442
1443
1444 if (crtc_state->hw.degamma_lut ||
1445 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1446 limited_color_range)
1447 return 0;
1448
1449 return CSC_POSITION_BEFORE_GAMMA;
1450}
1451
1452static int ivb_color_check(struct intel_crtc_state *crtc_state)
1453{
1454 bool limited_color_range = ilk_csc_limited_range(crtc_state);
1455 int ret;
1456
1457 ret = check_luts(crtc_state);
1458 if (ret)
1459 return ret;
1460
1461 crtc_state->gamma_enable =
1462 (crtc_state->hw.gamma_lut ||
1463 crtc_state->hw.degamma_lut) &&
1464 !crtc_state->c8_planes;
1465
1466 crtc_state->csc_enable =
1467 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1468 crtc_state->hw.ctm || limited_color_range;
1469
1470 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1471
1472 crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1473
1474 ret = intel_color_add_affected_planes(crtc_state);
1475 if (ret)
1476 return ret;
1477
1478 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1479
1480 return 0;
1481}
1482
1483static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1484{
1485 if (!crtc_state->gamma_enable ||
1486 crtc_state_is_legacy_gamma(crtc_state))
1487 return GAMMA_MODE_MODE_8BIT;
1488 else
1489 return GAMMA_MODE_MODE_10BIT;
1490}
1491
1492static int glk_color_check(struct intel_crtc_state *crtc_state)
1493{
1494 int ret;
1495
1496 ret = check_luts(crtc_state);
1497 if (ret)
1498 return ret;
1499
1500 crtc_state->gamma_enable =
1501 crtc_state->hw.gamma_lut &&
1502 !crtc_state->c8_planes;
1503
1504
1505 crtc_state->csc_enable =
1506 crtc_state->hw.degamma_lut ||
1507 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1508 crtc_state->hw.ctm || crtc_state->limited_color_range;
1509
1510 crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1511
1512 crtc_state->csc_mode = 0;
1513
1514 ret = intel_color_add_affected_planes(crtc_state);
1515 if (ret)
1516 return ret;
1517
1518 crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1519
1520 return 0;
1521}
1522
1523static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1524{
1525 u32 gamma_mode = 0;
1526
1527 if (crtc_state->hw.degamma_lut)
1528 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1529
1530 if (crtc_state->hw.gamma_lut &&
1531 !crtc_state->c8_planes)
1532 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1533
1534 if (!crtc_state->hw.gamma_lut ||
1535 crtc_state_is_legacy_gamma(crtc_state))
1536 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1537 else
1538 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1539
1540 return gamma_mode;
1541}
1542
1543static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1544{
1545 u32 csc_mode = 0;
1546
1547 if (crtc_state->hw.ctm)
1548 csc_mode |= ICL_CSC_ENABLE;
1549
1550 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1551 crtc_state->limited_color_range)
1552 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1553
1554 return csc_mode;
1555}
1556
1557static int icl_color_check(struct intel_crtc_state *crtc_state)
1558{
1559 int ret;
1560
1561 ret = check_luts(crtc_state);
1562 if (ret)
1563 return ret;
1564
1565 crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1566
1567 crtc_state->csc_mode = icl_csc_mode(crtc_state);
1568
1569 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1570
1571 return 0;
1572}
1573
1574static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1575{
1576 if (!crtc_state->gamma_enable)
1577 return 0;
1578
1579 switch (crtc_state->gamma_mode) {
1580 case GAMMA_MODE_MODE_8BIT:
1581 return 8;
1582 case GAMMA_MODE_MODE_10BIT:
1583 return 16;
1584 default:
1585 MISSING_CASE(crtc_state->gamma_mode);
1586 return 0;
1587 }
1588}
1589
1590static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1591{
1592 if (!crtc_state->gamma_enable)
1593 return 0;
1594
1595 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1596 return 0;
1597
1598 switch (crtc_state->gamma_mode) {
1599 case GAMMA_MODE_MODE_8BIT:
1600 return 8;
1601 case GAMMA_MODE_MODE_10BIT:
1602 return 10;
1603 default:
1604 MISSING_CASE(crtc_state->gamma_mode);
1605 return 0;
1606 }
1607}
1608
1609static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1610{
1611 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1612 return 10;
1613 else
1614 return i9xx_gamma_precision(crtc_state);
1615}
1616
1617static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1618{
1619 if (!crtc_state->gamma_enable)
1620 return 0;
1621
1622 switch (crtc_state->gamma_mode) {
1623 case GAMMA_MODE_MODE_8BIT:
1624 return 8;
1625 case GAMMA_MODE_MODE_10BIT:
1626 return 10;
1627 default:
1628 MISSING_CASE(crtc_state->gamma_mode);
1629 return 0;
1630 }
1631}
1632
1633int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1634{
1635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1637
1638 if (HAS_GMCH(dev_priv)) {
1639 if (IS_CHERRYVIEW(dev_priv))
1640 return chv_gamma_precision(crtc_state);
1641 else
1642 return i9xx_gamma_precision(crtc_state);
1643 } else {
1644 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1645 return glk_gamma_precision(crtc_state);
1646 else if (IS_IRONLAKE(dev_priv))
1647 return ilk_gamma_precision(crtc_state);
1648 }
1649
1650 return 0;
1651}
1652
1653static bool err_check(struct drm_color_lut *lut1,
1654 struct drm_color_lut *lut2, u32 err)
1655{
1656 return ((abs((long)lut2->red - lut1->red)) <= err) &&
1657 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1658 ((abs((long)lut2->green - lut1->green)) <= err);
1659}
1660
1661static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1662 struct drm_color_lut *lut2,
1663 int lut_size, u32 err)
1664{
1665 int i;
1666
1667 for (i = 0; i < lut_size; i++) {
1668 if (!err_check(&lut1[i], &lut2[i], err))
1669 return false;
1670 }
1671
1672 return true;
1673}
1674
1675bool intel_color_lut_equal(struct drm_property_blob *blob1,
1676 struct drm_property_blob *blob2,
1677 u32 gamma_mode, u32 bit_precision)
1678{
1679 struct drm_color_lut *lut1, *lut2;
1680 int lut_size1, lut_size2;
1681 u32 err;
1682
1683 if (!blob1 != !blob2)
1684 return false;
1685
1686 if (!blob1)
1687 return true;
1688
1689 lut_size1 = drm_color_lut_size(blob1);
1690 lut_size2 = drm_color_lut_size(blob2);
1691
1692
1693 switch (gamma_mode) {
1694 case GAMMA_MODE_MODE_8BIT:
1695 case GAMMA_MODE_MODE_10BIT:
1696 if (lut_size1 != lut_size2)
1697 return false;
1698 break;
1699 default:
1700 MISSING_CASE(gamma_mode);
1701 return false;
1702 }
1703
1704 lut1 = blob1->data;
1705 lut2 = blob2->data;
1706
1707 err = 0xffff >> bit_precision;
1708
1709
1710 switch (gamma_mode) {
1711 case GAMMA_MODE_MODE_8BIT:
1712 case GAMMA_MODE_MODE_10BIT:
1713 if (!intel_color_lut_entry_equal(lut1, lut2,
1714 lut_size2, err))
1715 return false;
1716 break;
1717 default:
1718 MISSING_CASE(gamma_mode);
1719 return false;
1720 }
1721
1722 return true;
1723}
1724
1725static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
1726{
1727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1728 enum pipe pipe = crtc->pipe;
1729 struct drm_property_blob *blob;
1730 struct drm_color_lut *lut;
1731 int i;
1732
1733 blob = drm_property_create_blob(&dev_priv->drm,
1734 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1735 NULL);
1736 if (IS_ERR(blob))
1737 return NULL;
1738
1739 lut = blob->data;
1740
1741 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1742 u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
1743
1744 i9xx_lut_8_pack(&lut[i], val);
1745 }
1746
1747 return blob;
1748}
1749
1750static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1751{
1752 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1753
1754 if (!crtc_state->gamma_enable)
1755 return;
1756
1757 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1758}
1759
1760static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
1761{
1762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1763 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1764 enum pipe pipe = crtc->pipe;
1765 struct drm_property_blob *blob;
1766 struct drm_color_lut *lut;
1767
1768 blob = drm_property_create_blob(&dev_priv->drm,
1769 sizeof(struct drm_color_lut) * lut_size,
1770 NULL);
1771 if (IS_ERR(blob))
1772 return NULL;
1773
1774 lut = blob->data;
1775
1776 for (i = 0; i < lut_size - 1; i++) {
1777 u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
1778 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
1779
1780 i965_lut_10p6_pack(&lut[i], ldw, udw);
1781 }
1782
1783 lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
1784 lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
1785 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
1786
1787 return blob;
1788}
1789
1790static void i965_read_luts(struct intel_crtc_state *crtc_state)
1791{
1792 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1793
1794 if (!crtc_state->gamma_enable)
1795 return;
1796
1797 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1798 crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
1799 else
1800 crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
1801}
1802
1803static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
1804{
1805 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1806 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1807 enum pipe pipe = crtc->pipe;
1808 struct drm_property_blob *blob;
1809 struct drm_color_lut *lut;
1810
1811 blob = drm_property_create_blob(&dev_priv->drm,
1812 sizeof(struct drm_color_lut) * lut_size,
1813 NULL);
1814 if (IS_ERR(blob))
1815 return NULL;
1816
1817 lut = blob->data;
1818
1819 for (i = 0; i < lut_size; i++) {
1820 u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
1821 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
1822
1823 chv_cgm_gamma_pack(&lut[i], ldw, udw);
1824 }
1825
1826 return blob;
1827}
1828
1829static void chv_read_luts(struct intel_crtc_state *crtc_state)
1830{
1831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1832
1833 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1834 crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
1835 else
1836 i965_read_luts(crtc_state);
1837}
1838
1839static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
1840{
1841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842 enum pipe pipe = crtc->pipe;
1843 struct drm_property_blob *blob;
1844 struct drm_color_lut *lut;
1845 int i;
1846
1847 blob = drm_property_create_blob(&dev_priv->drm,
1848 sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1849 NULL);
1850 if (IS_ERR(blob))
1851 return NULL;
1852
1853 lut = blob->data;
1854
1855 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1856 u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
1857
1858 i9xx_lut_8_pack(&lut[i], val);
1859 }
1860
1861 return blob;
1862}
1863
1864static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
1865{
1866 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1867 int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1868 enum pipe pipe = crtc->pipe;
1869 struct drm_property_blob *blob;
1870 struct drm_color_lut *lut;
1871
1872 blob = drm_property_create_blob(&dev_priv->drm,
1873 sizeof(struct drm_color_lut) * lut_size,
1874 NULL);
1875 if (IS_ERR(blob))
1876 return NULL;
1877
1878 lut = blob->data;
1879
1880 for (i = 0; i < lut_size; i++) {
1881 u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
1882
1883 ilk_lut_10_pack(&lut[i], val);
1884 }
1885
1886 return blob;
1887}
1888
1889static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1890{
1891 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1892
1893 if (!crtc_state->gamma_enable)
1894 return;
1895
1896 if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1897 return;
1898
1899 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1900 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1901 else
1902 crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
1903}
1904
1905static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
1906 u32 prec_index)
1907{
1908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1909 int i, hw_lut_size = ivb_lut_10_size(prec_index);
1910 enum pipe pipe = crtc->pipe;
1911 struct drm_property_blob *blob;
1912 struct drm_color_lut *lut;
1913
1914 blob = drm_property_create_blob(&dev_priv->drm,
1915 sizeof(struct drm_color_lut) * hw_lut_size,
1916 NULL);
1917 if (IS_ERR(blob))
1918 return NULL;
1919
1920 lut = blob->data;
1921
1922 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
1923 prec_index | PAL_PREC_AUTO_INCREMENT);
1924
1925 for (i = 0; i < hw_lut_size; i++) {
1926 u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
1927
1928 ilk_lut_10_pack(&lut[i], val);
1929 }
1930
1931 intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
1932
1933 return blob;
1934}
1935
1936static void glk_read_luts(struct intel_crtc_state *crtc_state)
1937{
1938 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1939
1940 if (!crtc_state->gamma_enable)
1941 return;
1942
1943 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1944 crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
1945 else
1946 crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
1947}
1948
1949void intel_color_init(struct intel_crtc *crtc)
1950{
1951 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1952 bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1953
1954 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1955
1956 if (HAS_GMCH(dev_priv)) {
1957 if (IS_CHERRYVIEW(dev_priv)) {
1958 dev_priv->display.color_check = chv_color_check;
1959 dev_priv->display.color_commit = i9xx_color_commit;
1960 dev_priv->display.load_luts = chv_load_luts;
1961 dev_priv->display.read_luts = chv_read_luts;
1962 } else if (INTEL_GEN(dev_priv) >= 4) {
1963 dev_priv->display.color_check = i9xx_color_check;
1964 dev_priv->display.color_commit = i9xx_color_commit;
1965 dev_priv->display.load_luts = i965_load_luts;
1966 dev_priv->display.read_luts = i965_read_luts;
1967 } else {
1968 dev_priv->display.color_check = i9xx_color_check;
1969 dev_priv->display.color_commit = i9xx_color_commit;
1970 dev_priv->display.load_luts = i9xx_load_luts;
1971 dev_priv->display.read_luts = i9xx_read_luts;
1972 }
1973 } else {
1974 if (INTEL_GEN(dev_priv) >= 11)
1975 dev_priv->display.color_check = icl_color_check;
1976 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1977 dev_priv->display.color_check = glk_color_check;
1978 else if (INTEL_GEN(dev_priv) >= 7)
1979 dev_priv->display.color_check = ivb_color_check;
1980 else
1981 dev_priv->display.color_check = ilk_color_check;
1982
1983 if (INTEL_GEN(dev_priv) >= 9)
1984 dev_priv->display.color_commit = skl_color_commit;
1985 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1986 dev_priv->display.color_commit = hsw_color_commit;
1987 else
1988 dev_priv->display.color_commit = ilk_color_commit;
1989
1990 if (INTEL_GEN(dev_priv) >= 11) {
1991 dev_priv->display.load_luts = icl_load_luts;
1992 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1993 dev_priv->display.load_luts = glk_load_luts;
1994 dev_priv->display.read_luts = glk_read_luts;
1995 } else if (INTEL_GEN(dev_priv) >= 8) {
1996 dev_priv->display.load_luts = bdw_load_luts;
1997 } else if (INTEL_GEN(dev_priv) >= 7) {
1998 dev_priv->display.load_luts = ivb_load_luts;
1999 } else {
2000 dev_priv->display.load_luts = ilk_load_luts;
2001 dev_priv->display.read_luts = ilk_read_luts;
2002 }
2003 }
2004
2005 drm_crtc_enable_color_mgmt(&crtc->base,
2006 INTEL_INFO(dev_priv)->color.degamma_lut_size,
2007 has_ctm,
2008 INTEL_INFO(dev_priv)->color.gamma_lut_size);
2009}
2010