1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6#ifndef __INTEL_RESET_TYPES_H_ 7#define __INTEL_RESET_TYPES_H_ 8 9#include <linux/mutex.h> 10#include <linux/wait.h> 11#include <linux/srcu.h> 12 13struct intel_reset { 14 /** 15 * flags: Control various stages of the GPU reset 16 * 17 * #I915_RESET_BACKOFF - When we start a global reset, we need to 18 * serialise with any other users attempting to do the same, and 19 * any global resources that may be clobber by the reset (such as 20 * FENCE registers). 21 * 22 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to 23 * acquire the struct_mutex to reset an engine, we need an explicit 24 * flag to prevent two concurrent reset attempts in the same engine. 25 * As the number of engines continues to grow, allocate the flags from 26 * the most significant bits. 27 * 28 * #I915_WEDGED - If reset fails and we can no longer use the GPU, 29 * we set the #I915_WEDGED bit. Prior to command submission, e.g. 30 * i915_request_alloc(), this bit is checked and the sequence 31 * aborted (with -EIO reported to userspace) if set. 32 * 33 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no 34 * longer use the GPU - similar to #I915_WEDGED bit. The difference in 35 * in the way we're handling "forced" unwedged (e.g. through debugfs), 36 * which is not allowed in case we failed to initialize. 37 */ 38 unsigned long flags; 39#define I915_RESET_BACKOFF 0 40#define I915_RESET_MODESET 1 41#define I915_RESET_ENGINE 2 42#define I915_WEDGED_ON_INIT (BITS_PER_LONG - 2) 43#define I915_WEDGED (BITS_PER_LONG - 1) 44 45 struct mutex mutex; /* serialises wedging/unwedging */ 46 47 /** 48 * Waitqueue to signal when the reset has completed. Used by clients 49 * that wait for dev_priv->mm.wedged to settle. 50 */ 51 wait_queue_head_t queue; 52 53 struct srcu_struct backoff_srcu; 54}; 55 56#endif /* _INTEL_RESET_TYPES_H_ */ 57