LXR linux/drivers/gpu/drm/i915/intel_device

   1/*
   2 * Copyright © 2014-2017 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef _INTEL_DEVICE_INFO_H_
  26#define _INTEL_DEVICE_INFO_H_
  27
  28#include <uapi/drm/i915_drm.h>
  29
  30#include "display/intel_display.h"
  31
  32#include "gt/intel_engine_types.h"
  33#include "gt/intel_context_types.h"
  34#include "gt/intel_sseu.h"
  35
  36struct drm_printer;
  37struct drm_i915_private;
  38
  39/* Keep in gen based order, and chronological order within a gen */
  40enum intel_platform {
  41        INTEL_PLATFORM_UNINITIALIZED = 0,
  42        /* gen2 */
  43        INTEL_I830,
  44        INTEL_I845G,
  45        INTEL_I85X,
  46        INTEL_I865G,
  47        /* gen3 */
  48        INTEL_I915G,
  49        INTEL_I915GM,
  50        INTEL_I945G,
  51        INTEL_I945GM,
  52        INTEL_G33,
  53        INTEL_PINEVIEW,
  54        /* gen4 */
  55        INTEL_I965G,
  56        INTEL_I965GM,
  57        INTEL_G45,
  58        INTEL_GM45,
  59        /* gen5 */
  60        INTEL_IRONLAKE,
  61        /* gen6 */
  62        INTEL_SANDYBRIDGE,
  63        /* gen7 */
  64        INTEL_IVYBRIDGE,
  65        INTEL_VALLEYVIEW,
  66        INTEL_HASWELL,
  67        /* gen8 */
  68        INTEL_BROADWELL,
  69        INTEL_CHERRYVIEW,
  70        /* gen9 */
  71        INTEL_SKYLAKE,
  72        INTEL_BROXTON,
  73        INTEL_KABYLAKE,
  74        INTEL_GEMINILAKE,
  75        INTEL_COFFEELAKE,
  76        /* gen10 */
  77        INTEL_CANNONLAKE,
  78        /* gen11 */
  79        INTEL_ICELAKE,
  80        INTEL_ELKHARTLAKE,
  81        /* gen12 */
  82        INTEL_TIGERLAKE,
  83        INTEL_MAX_PLATFORMS
  84};
  85
  86/*
  87 * Subplatform bits share the same namespace per parent platform. In other words
  88 * it is fine for the same bit to be used on multiple parent platforms.
  89 */
  90
  91#define INTEL_SUBPLATFORM_BITS (3)
  92
  93/* HSW/BDW/SKL/KBL/CFL */
  94#define INTEL_SUBPLATFORM_ULT   (0)
  95#define INTEL_SUBPLATFORM_ULX   (1)
  96
  97/* CNL/ICL */
  98#define INTEL_SUBPLATFORM_PORTF (0)
  99
 100enum intel_ppgtt_type {
 101        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 102        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 103        INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
 104};
 105
 106#define DEV_INFO_FOR_EACH_FLAG(func) \
 107        func(is_mobile); \
 108        func(is_lp); \
 109        func(require_force_probe); \
 110        func(is_dgfx); \
 111        /* Keep has_* in alphabetical order */ \
 112        func(has_64bit_reloc); \
 113        func(gpu_reset_clobbers_display); \
 114        func(has_reset_engine); \
 115        func(has_fpga_dbg); \
 116        func(has_global_mocs); \
 117        func(has_gt_uc); \
 118        func(has_l3_dpf); \
 119        func(has_llc); \
 120        func(has_logical_ring_contexts); \
 121        func(has_logical_ring_elsq); \
 122        func(has_logical_ring_preemption); \
 123        func(has_pooled_eu); \
 124        func(has_rc6); \
 125        func(has_rc6p); \
 126        func(has_rps); \
 127        func(has_runtime_pm); \
 128        func(has_snoop); \
 129        func(has_coherent_ggtt); \
 130        func(unfenced_needs_alignment); \
 131        func(hws_needs_physical);
 132
 133#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 134        /* Keep in alphabetical order */ \
 135        func(cursor_needs_physical); \
 136        func(has_csr); \
 137        func(has_ddi); \
 138        func(has_dp_mst); \
 139        func(has_dsb); \
 140        func(has_dsc); \
 141        func(has_fbc); \
 142        func(has_gmch); \
 143        func(has_hdcp); \
 144        func(has_hotplug); \
 145        func(has_ipc); \
 146        func(has_modular_fia); \
 147        func(has_overlay); \
 148        func(has_psr); \
 149        func(overlay_needs_physical); \
 150        func(supports_tv);
 151
 152struct intel_device_info {
 153        u16 gen_mask;
 154
 155        u8 gen;
 156        u8 gt; /* GT number, 0 if undefined */
 157        intel_engine_mask_t engine_mask; /* Engines supported by the HW */
 158
 159        enum intel_platform platform;
 160
 161        enum intel_ppgtt_type ppgtt_type;
 162        unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
 163
 164        unsigned int page_sizes; /* page sizes supported by the HW */
 165
 166        u32 memory_regions; /* regions supported by the HW */
 167
 168        u32 display_mmio_offset;
 169
 170        u8 pipe_mask;
 171
 172#define DEFINE_FLAG(name) u8 name:1
 173        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 174#undef DEFINE_FLAG
 175
 176        struct {
 177#define DEFINE_FLAG(name) u8 name:1
 178                DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 179#undef DEFINE_FLAG
 180        } display;
 181
 182        u16 ddb_size; /* in blocks */
 183        u8 num_supported_dbuf_slices; /* number of DBuf slices */
 184
 185        /* Register offsets for the various display pipes and transcoders */
 186        int pipe_offsets[I915_MAX_TRANSCODERS];
 187        int trans_offsets[I915_MAX_TRANSCODERS];
 188        int cursor_offsets[I915_MAX_PIPES];
 189
 190        struct color_luts {
 191                u32 degamma_lut_size;
 192                u32 gamma_lut_size;
 193                u32 degamma_lut_tests;
 194                u32 gamma_lut_tests;
 195        } color;
 196};
 197
 198struct intel_runtime_info {
 199        /*
 200         * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
 201         * into single runtime conditionals, and also to provide groundwork
 202         * for future per platform, or per SKU build optimizations.
 203         *
 204         * Array can be extended when necessary if the corresponding
 205         * BUILD_BUG_ON is hit.
 206         */
 207        u32 platform_mask[2];
 208
 209        u16 device_id;
 210
 211        u8 num_sprites[I915_MAX_PIPES];
 212        u8 num_scalers[I915_MAX_PIPES];
 213
 214        u8 num_engines;
 215
 216        /* Slice/subslice/EU info */
 217        struct sseu_dev_info sseu;
 218
 219        u32 rawclk_freq;
 220
 221        u32 cs_timestamp_frequency_khz;
 222        u32 cs_timestamp_period_ns;
 223
 224        /* Media engine access to SFC per instance */
 225        u8 vdbox_sfc_access;
 226};
 227
 228struct intel_driver_caps {
 229        unsigned int scheduler;
 230        bool has_logical_contexts:1;
 231};
 232
 233const char *intel_platform_name(enum intel_platform platform);
 234
 235void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 236void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 237
 238void intel_device_info_print_static(const struct intel_device_info *info,
 239                                    struct drm_printer *p);
 240void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 241                                     struct drm_printer *p);
 242void intel_device_info_print_topology(const struct sseu_dev_info *sseu,
 243                                      struct drm_printer *p);
 244
 245void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
 246
 247void intel_driver_caps_print(const struct intel_driver_caps *caps,
 248                             struct drm_printer *p);
 249
 250#endif
 251