LXR linux/drivers/gpu/drm/msm/adreno/a6xx

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3
   4#ifndef _A6XX_GMU_H_
   5#define _A6XX_GMU_H_
   6
   7#include <linux/iopoll.h>
   8#include <linux/interrupt.h>
   9#include "msm_drv.h"
  10#include "a6xx_hfi.h"
  11
  12struct a6xx_gmu_bo {
  13        void *virt;
  14        size_t size;
  15        dma_addr_t iova;
  16};
  17
  18/*
  19 * These define the different GMU wake up options - these define how both the
  20 * CPU and the GMU bring up the hardware
  21 */
  22
  23/* THe GMU has already been booted and the rentention registers are active */
  24#define GMU_WARM_BOOT 0
  25
  26/* the GMU is coming up for the first time or back from a power collapse */
  27#define GMU_COLD_BOOT 1
  28
  29/*
  30 * These define the level of control that the GMU has - the higher the number
  31 * the more things that the GMU hardware controls on its own.
  32 */
  33
  34/* The GMU does not do any idle state management */
  35#define GMU_IDLE_STATE_ACTIVE 0
  36
  37/* The GMU manages SPTP power collapse */
  38#define GMU_IDLE_STATE_SPTP 2
  39
  40/* The GMU does automatic IFPC (intra-frame power collapse) */
  41#define GMU_IDLE_STATE_IFPC 3
  42
  43struct a6xx_gmu {
  44        struct device *dev;
  45
  46        void * __iomem mmio;
  47
  48        int hfi_irq;
  49        int gmu_irq;
  50
  51        struct device *gxpd;
  52
  53        int idle_level;
  54
  55        struct a6xx_gmu_bo *hfi;
  56        struct a6xx_gmu_bo *debug;
  57
  58        int nr_clocks;
  59        struct clk_bulk_data *clocks;
  60        struct clk *core_clk;
  61
  62        /* current performance index set externally */
  63        int current_perf_index;
  64
  65        int nr_gpu_freqs;
  66        unsigned long gpu_freqs[16];
  67        u32 gx_arc_votes[16];
  68
  69        int nr_gmu_freqs;
  70        unsigned long gmu_freqs[4];
  71        u32 cx_arc_votes[4];
  72
  73        unsigned long freq;
  74
  75        struct a6xx_hfi_queue queues[2];
  76
  77        bool initialized;
  78        bool hung;
  79};
  80
  81static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
  82{
  83        return msm_readl(gmu->mmio + (offset << 2));
  84}
  85
  86static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
  87{
  88        return msm_writel(value, gmu->mmio + (offset << 2));
  89}
  90
  91static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
  92{
  93        u32 val = gmu_read(gmu, reg);
  94
  95        val &= ~mask;
  96
  97        gmu_write(gmu, reg, val | or);
  98}
  99
 100static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 101{
 102        u64 val;
 103
 104        val = (u64) msm_readl(gmu->mmio + (lo << 2));
 105        val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
 106
 107        return val;
 108}
 109
 110#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
 111        readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
 112                interval, timeout)
 113
 114/*
 115 * These are the available OOB (out of band requests) to the GMU where "out of
 116 * band" means that the CPU talks to the GMU directly and not through HFI.
 117 * Normally this works by writing a ITCM/DTCM register and then triggering a
 118 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 119 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 120 *
 121 * These are used to force the GMU/GPU to stay on during a critical sequence or
 122 * for hardware workarounds.
 123 */
 124
 125enum a6xx_gmu_oob_state {
 126        GMU_OOB_BOOT_SLUMBER = 0,
 127        GMU_OOB_GPU_SET,
 128        GMU_OOB_DCVS_SET,
 129};
 130
 131/* These are the interrupt / ack bits for each OOB request that are set
 132 * in a6xx_gmu_set_oob and a6xx_clear_oob
 133 */
 134
 135/*
 136 * Let the GMU know that a boot or slumber operation has started. The value in
 137 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
 138 * doing
 139 */
 140#define GMU_OOB_BOOT_SLUMBER_REQUEST    22
 141#define GMU_OOB_BOOT_SLUMBER_ACK        30
 142#define GMU_OOB_BOOT_SLUMBER_CLEAR      30
 143
 144/*
 145 * Set a new power level for the GPU when the CPU is doing frequency scaling
 146 */
 147#define GMU_OOB_DCVS_REQUEST    23
 148#define GMU_OOB_DCVS_ACK        31
 149#define GMU_OOB_DCVS_CLEAR      31
 150
 151/*
 152 * Let the GMU know to not turn off any GPU registers while the CPU is in a
 153 * critical section
 154 */
 155#define GMU_OOB_GPU_SET_REQUEST 16
 156#define GMU_OOB_GPU_SET_ACK     24
 157#define GMU_OOB_GPU_SET_CLEAR   24
 158
 159
 160void a6xx_hfi_init(struct a6xx_gmu *gmu);
 161int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
 162void a6xx_hfi_stop(struct a6xx_gmu *gmu);
 163
 164bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
 165bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
 166
 167#endif
 168