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8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29
30
31
32
33
34
35
36
37
38
39
40
41#define MSM_VERSION_MAJOR 1
42#define MSM_VERSION_MINOR 5
43#define MSM_VERSION_PATCHLEVEL 0
44
45static const struct drm_mode_config_funcs mode_config_funcs = {
46 .fb_create = msm_framebuffer_create,
47 .output_poll_changed = drm_fb_helper_output_poll_changed,
48 .atomic_check = drm_atomic_helper_check,
49 .atomic_commit = drm_atomic_helper_commit,
50};
51
52static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
53 .atomic_commit_tail = msm_atomic_commit_tail,
54};
55
56#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
57static bool reglog = false;
58MODULE_PARM_DESC(reglog, "Enable register read/write logging");
59module_param(reglog, bool, 0600);
60#else
61#define reglog 0
62#endif
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate = false;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82
83
84
85
86struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
87 const char *name)
88{
89 int i;
90 char n[32];
91
92 snprintf(n, sizeof(n), "%s_clk", name);
93
94 for (i = 0; bulk && i < count; i++) {
95 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
96 return bulk[i].clk;
97 }
98
99
100 return NULL;
101}
102
103struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
104{
105 struct clk *clk;
106 char name2[32];
107
108 clk = devm_clk_get(&pdev->dev, name);
109 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
110 return clk;
111
112 snprintf(name2, sizeof(name2), "%s_clk", name);
113
114 clk = devm_clk_get(&pdev->dev, name2);
115 if (!IS_ERR(clk))
116 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
117 "\"%s\" instead of \"%s\"\n", name, name2);
118
119 return clk;
120}
121
122void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
123 const char *dbgname)
124{
125 struct resource *res;
126 unsigned long size;
127 void __iomem *ptr;
128
129 if (name)
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
131 else
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 if (!res) {
135 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
136 return ERR_PTR(-EINVAL);
137 }
138
139 size = resource_size(res);
140
141 ptr = devm_ioremap(&pdev->dev, res->start, size);
142 if (!ptr) {
143 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
144 return ERR_PTR(-ENOMEM);
145 }
146
147 if (reglog)
148 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
149
150 return ptr;
151}
152
153void msm_writel(u32 data, void __iomem *addr)
154{
155 if (reglog)
156 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
157 writel(data, addr);
158}
159
160u32 msm_readl(const void __iomem *addr)
161{
162 u32 val = readl(addr);
163 if (reglog)
164 pr_err("IO:R %p %08x\n", addr, val);
165 return val;
166}
167
168struct msm_vblank_work {
169 struct work_struct work;
170 int crtc_id;
171 bool enable;
172 struct msm_drm_private *priv;
173};
174
175static void vblank_ctrl_worker(struct work_struct *work)
176{
177 struct msm_vblank_work *vbl_work = container_of(work,
178 struct msm_vblank_work, work);
179 struct msm_drm_private *priv = vbl_work->priv;
180 struct msm_kms *kms = priv->kms;
181
182 if (vbl_work->enable)
183 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
184 else
185 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
186
187 kfree(vbl_work);
188}
189
190static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
191 int crtc_id, bool enable)
192{
193 struct msm_vblank_work *vbl_work;
194
195 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
196 if (!vbl_work)
197 return -ENOMEM;
198
199 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
200
201 vbl_work->crtc_id = crtc_id;
202 vbl_work->enable = enable;
203 vbl_work->priv = priv;
204
205 queue_work(priv->wq, &vbl_work->work);
206
207 return 0;
208}
209
210static int msm_drm_uninit(struct device *dev)
211{
212 struct platform_device *pdev = to_platform_device(dev);
213 struct drm_device *ddev = platform_get_drvdata(pdev);
214 struct msm_drm_private *priv = ddev->dev_private;
215 struct msm_kms *kms = priv->kms;
216 struct msm_mdss *mdss = priv->mdss;
217 int i;
218
219
220
221
222
223
224
225
226 if (ddev->registered) {
227 drm_dev_unregister(ddev);
228 drm_atomic_helper_shutdown(ddev);
229 }
230
231
232
233
234
235
236 flush_workqueue(priv->wq);
237
238
239 for (i = 0; i < priv->num_crtcs; i++) {
240 if (priv->event_thread[i].thread) {
241 kthread_destroy_worker(&priv->event_thread[i].worker);
242 priv->event_thread[i].thread = NULL;
243 }
244 }
245
246 msm_gem_shrinker_cleanup(ddev);
247
248 drm_kms_helper_poll_fini(ddev);
249
250 msm_perf_debugfs_cleanup(priv);
251 msm_rd_debugfs_cleanup(priv);
252
253#ifdef CONFIG_DRM_FBDEV_EMULATION
254 if (fbdev && priv->fbdev)
255 msm_fbdev_free(ddev);
256#endif
257
258 drm_mode_config_cleanup(ddev);
259
260 pm_runtime_get_sync(dev);
261 drm_irq_uninstall(ddev);
262 pm_runtime_put_sync(dev);
263
264 if (kms && kms->funcs)
265 kms->funcs->destroy(kms);
266
267 if (priv->vram.paddr) {
268 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
269 drm_mm_takedown(&priv->vram.mm);
270 dma_free_attrs(dev, priv->vram.size, NULL,
271 priv->vram.paddr, attrs);
272 }
273
274 component_unbind_all(dev, ddev);
275
276 if (mdss && mdss->funcs)
277 mdss->funcs->destroy(ddev);
278
279 ddev->dev_private = NULL;
280 drm_dev_put(ddev);
281
282 destroy_workqueue(priv->wq);
283 kfree(priv);
284
285 return 0;
286}
287
288#define KMS_MDP4 4
289#define KMS_MDP5 5
290#define KMS_DPU 3
291
292static int get_mdp_ver(struct platform_device *pdev)
293{
294 struct device *dev = &pdev->dev;
295
296 return (int) (unsigned long) of_device_get_match_data(dev);
297}
298
299#include <linux/of_address.h>
300
301bool msm_use_mmu(struct drm_device *dev)
302{
303 struct msm_drm_private *priv = dev->dev_private;
304
305
306 return priv->is_a2xx || iommu_present(&platform_bus_type);
307}
308
309static int msm_init_vram(struct drm_device *dev)
310{
311 struct msm_drm_private *priv = dev->dev_private;
312 struct device_node *node;
313 unsigned long size = 0;
314 int ret = 0;
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
334 if (node) {
335 struct resource r;
336 ret = of_address_to_resource(node, 0, &r);
337 of_node_put(node);
338 if (ret)
339 return ret;
340 size = r.end - r.start;
341 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
342
343
344
345
346
347 } else if (!msm_use_mmu(dev)) {
348 DRM_INFO("using %s VRAM carveout\n", vram);
349 size = memparse(vram, NULL);
350 }
351
352 if (size) {
353 unsigned long attrs = 0;
354 void *p;
355
356 priv->vram.size = size;
357
358 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
359 spin_lock_init(&priv->vram.lock);
360
361 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
362 attrs |= DMA_ATTR_WRITE_COMBINE;
363
364
365
366
367 p = dma_alloc_attrs(dev->dev, size,
368 &priv->vram.paddr, GFP_KERNEL, attrs);
369 if (!p) {
370 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
371 priv->vram.paddr = 0;
372 return -ENOMEM;
373 }
374
375 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
376 (uint32_t)priv->vram.paddr,
377 (uint32_t)(priv->vram.paddr + size));
378 }
379
380 return ret;
381}
382
383static int msm_drm_init(struct device *dev, struct drm_driver *drv)
384{
385 struct platform_device *pdev = to_platform_device(dev);
386 struct drm_device *ddev;
387 struct msm_drm_private *priv;
388 struct msm_kms *kms;
389 struct msm_mdss *mdss;
390 int ret, i;
391 struct sched_param param;
392
393 ddev = drm_dev_alloc(drv, dev);
394 if (IS_ERR(ddev)) {
395 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
396 return PTR_ERR(ddev);
397 }
398
399 platform_set_drvdata(pdev, ddev);
400
401 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
402 if (!priv) {
403 ret = -ENOMEM;
404 goto err_put_drm_dev;
405 }
406
407 ddev->dev_private = priv;
408 priv->dev = ddev;
409
410 switch (get_mdp_ver(pdev)) {
411 case KMS_MDP5:
412 ret = mdp5_mdss_init(ddev);
413 break;
414 case KMS_DPU:
415 ret = dpu_mdss_init(ddev);
416 break;
417 default:
418 ret = 0;
419 break;
420 }
421 if (ret)
422 goto err_free_priv;
423
424 mdss = priv->mdss;
425
426 priv->wq = alloc_ordered_workqueue("msm", 0);
427
428 INIT_WORK(&priv->free_work, msm_gem_free_work);
429 init_llist_head(&priv->free_list);
430
431 INIT_LIST_HEAD(&priv->inactive_list);
432
433 drm_mode_config_init(ddev);
434
435
436 ret = component_bind_all(dev, ddev);
437 if (ret)
438 goto err_destroy_mdss;
439
440 ret = msm_init_vram(ddev);
441 if (ret)
442 goto err_msm_uninit;
443
444 if (!dev->dma_parms) {
445 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
446 GFP_KERNEL);
447 if (!dev->dma_parms) {
448 ret = -ENOMEM;
449 goto err_msm_uninit;
450 }
451 }
452 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
453
454 msm_gem_shrinker_init(ddev);
455
456 switch (get_mdp_ver(pdev)) {
457 case KMS_MDP4:
458 kms = mdp4_kms_init(ddev);
459 priv->kms = kms;
460 break;
461 case KMS_MDP5:
462 kms = mdp5_kms_init(ddev);
463 break;
464 case KMS_DPU:
465 kms = dpu_kms_init(ddev);
466 priv->kms = kms;
467 break;
468 default:
469
470 WARN_ON(dev->of_node);
471 kms = NULL;
472 break;
473 }
474
475 if (IS_ERR(kms)) {
476 DRM_DEV_ERROR(dev, "failed to load kms\n");
477 ret = PTR_ERR(kms);
478 priv->kms = NULL;
479 goto err_msm_uninit;
480 }
481
482
483 ddev->mode_config.normalize_zpos = true;
484
485 if (kms) {
486 kms->dev = ddev;
487 ret = kms->funcs->hw_init(kms);
488 if (ret) {
489 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
490 goto err_msm_uninit;
491 }
492 }
493
494 ddev->mode_config.funcs = &mode_config_funcs;
495 ddev->mode_config.helper_private = &mode_config_helper_funcs;
496
497
498
499
500
501
502 param.sched_priority = 16;
503 for (i = 0; i < priv->num_crtcs; i++) {
504
505 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
506 kthread_init_worker(&priv->event_thread[i].worker);
507 priv->event_thread[i].dev = ddev;
508 priv->event_thread[i].thread =
509 kthread_run(kthread_worker_fn,
510 &priv->event_thread[i].worker,
511 "crtc_event:%d", priv->event_thread[i].crtc_id);
512 if (IS_ERR(priv->event_thread[i].thread)) {
513 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
514 priv->event_thread[i].thread = NULL;
515 goto err_msm_uninit;
516 }
517
518 ret = sched_setscheduler(priv->event_thread[i].thread,
519 SCHED_FIFO, ¶m);
520 if (ret)
521 dev_warn(dev, "event_thread set priority failed:%d\n",
522 ret);
523 }
524
525 ret = drm_vblank_init(ddev, priv->num_crtcs);
526 if (ret < 0) {
527 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
528 goto err_msm_uninit;
529 }
530
531 if (kms) {
532 pm_runtime_get_sync(dev);
533 ret = drm_irq_install(ddev, kms->irq);
534 pm_runtime_put_sync(dev);
535 if (ret < 0) {
536 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
537 goto err_msm_uninit;
538 }
539 }
540
541 ret = drm_dev_register(ddev, 0);
542 if (ret)
543 goto err_msm_uninit;
544
545 drm_mode_config_reset(ddev);
546
547#ifdef CONFIG_DRM_FBDEV_EMULATION
548 if (kms && fbdev)
549 priv->fbdev = msm_fbdev_init(ddev);
550#endif
551
552 ret = msm_debugfs_late_init(ddev);
553 if (ret)
554 goto err_msm_uninit;
555
556 drm_kms_helper_poll_init(ddev);
557
558 return 0;
559
560err_msm_uninit:
561 msm_drm_uninit(dev);
562 return ret;
563err_destroy_mdss:
564 if (mdss && mdss->funcs)
565 mdss->funcs->destroy(ddev);
566err_free_priv:
567 kfree(priv);
568err_put_drm_dev:
569 drm_dev_put(ddev);
570 return ret;
571}
572
573
574
575
576
577static void load_gpu(struct drm_device *dev)
578{
579 static DEFINE_MUTEX(init_lock);
580 struct msm_drm_private *priv = dev->dev_private;
581
582 mutex_lock(&init_lock);
583
584 if (!priv->gpu)
585 priv->gpu = adreno_load_gpu(dev);
586
587 mutex_unlock(&init_lock);
588}
589
590static int context_init(struct drm_device *dev, struct drm_file *file)
591{
592 struct msm_drm_private *priv = dev->dev_private;
593 struct msm_file_private *ctx;
594
595 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
596 if (!ctx)
597 return -ENOMEM;
598
599 msm_submitqueue_init(dev, ctx);
600
601 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
602 file->driver_priv = ctx;
603
604 return 0;
605}
606
607static int msm_open(struct drm_device *dev, struct drm_file *file)
608{
609
610
611
612 load_gpu(dev);
613
614 return context_init(dev, file);
615}
616
617static void context_close(struct msm_file_private *ctx)
618{
619 msm_submitqueue_close(ctx);
620 kfree(ctx);
621}
622
623static void msm_postclose(struct drm_device *dev, struct drm_file *file)
624{
625 struct msm_drm_private *priv = dev->dev_private;
626 struct msm_file_private *ctx = file->driver_priv;
627
628 mutex_lock(&dev->struct_mutex);
629 if (ctx == priv->lastctx)
630 priv->lastctx = NULL;
631 mutex_unlock(&dev->struct_mutex);
632
633 context_close(ctx);
634}
635
636static irqreturn_t msm_irq(int irq, void *arg)
637{
638 struct drm_device *dev = arg;
639 struct msm_drm_private *priv = dev->dev_private;
640 struct msm_kms *kms = priv->kms;
641 BUG_ON(!kms);
642 return kms->funcs->irq(kms);
643}
644
645static void msm_irq_preinstall(struct drm_device *dev)
646{
647 struct msm_drm_private *priv = dev->dev_private;
648 struct msm_kms *kms = priv->kms;
649 BUG_ON(!kms);
650 kms->funcs->irq_preinstall(kms);
651}
652
653static int msm_irq_postinstall(struct drm_device *dev)
654{
655 struct msm_drm_private *priv = dev->dev_private;
656 struct msm_kms *kms = priv->kms;
657 BUG_ON(!kms);
658
659 if (kms->funcs->irq_postinstall)
660 return kms->funcs->irq_postinstall(kms);
661
662 return 0;
663}
664
665static void msm_irq_uninstall(struct drm_device *dev)
666{
667 struct msm_drm_private *priv = dev->dev_private;
668 struct msm_kms *kms = priv->kms;
669 BUG_ON(!kms);
670 kms->funcs->irq_uninstall(kms);
671}
672
673int msm_crtc_enable_vblank(struct drm_crtc *crtc)
674{
675 struct drm_device *dev = crtc->dev;
676 unsigned int pipe = crtc->index;
677 struct msm_drm_private *priv = dev->dev_private;
678 struct msm_kms *kms = priv->kms;
679 if (!kms)
680 return -ENXIO;
681 DBG("dev=%p, crtc=%u", dev, pipe);
682 return vblank_ctrl_queue_work(priv, pipe, true);
683}
684
685void msm_crtc_disable_vblank(struct drm_crtc *crtc)
686{
687 struct drm_device *dev = crtc->dev;
688 unsigned int pipe = crtc->index;
689 struct msm_drm_private *priv = dev->dev_private;
690 struct msm_kms *kms = priv->kms;
691 if (!kms)
692 return;
693 DBG("dev=%p, crtc=%u", dev, pipe);
694 vblank_ctrl_queue_work(priv, pipe, false);
695}
696
697
698
699
700
701static int msm_ioctl_get_param(struct drm_device *dev, void *data,
702 struct drm_file *file)
703{
704 struct msm_drm_private *priv = dev->dev_private;
705 struct drm_msm_param *args = data;
706 struct msm_gpu *gpu;
707
708
709
710
711 if (args->pipe != MSM_PIPE_3D0)
712 return -EINVAL;
713
714 gpu = priv->gpu;
715
716 if (!gpu)
717 return -ENXIO;
718
719 return gpu->funcs->get_param(gpu, args->param, &args->value);
720}
721
722static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
723 struct drm_file *file)
724{
725 struct drm_msm_gem_new *args = data;
726
727 if (args->flags & ~MSM_BO_FLAGS) {
728 DRM_ERROR("invalid flags: %08x\n", args->flags);
729 return -EINVAL;
730 }
731
732 return msm_gem_new_handle(dev, file, args->size,
733 args->flags, &args->handle, NULL);
734}
735
736static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
737{
738 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
739}
740
741static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
742 struct drm_file *file)
743{
744 struct drm_msm_gem_cpu_prep *args = data;
745 struct drm_gem_object *obj;
746 ktime_t timeout = to_ktime(args->timeout);
747 int ret;
748
749 if (args->op & ~MSM_PREP_FLAGS) {
750 DRM_ERROR("invalid op: %08x\n", args->op);
751 return -EINVAL;
752 }
753
754 obj = drm_gem_object_lookup(file, args->handle);
755 if (!obj)
756 return -ENOENT;
757
758 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
759
760 drm_gem_object_put_unlocked(obj);
761
762 return ret;
763}
764
765static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
766 struct drm_file *file)
767{
768 struct drm_msm_gem_cpu_fini *args = data;
769 struct drm_gem_object *obj;
770 int ret;
771
772 obj = drm_gem_object_lookup(file, args->handle);
773 if (!obj)
774 return -ENOENT;
775
776 ret = msm_gem_cpu_fini(obj);
777
778 drm_gem_object_put_unlocked(obj);
779
780 return ret;
781}
782
783static int msm_ioctl_gem_info_iova(struct drm_device *dev,
784 struct drm_gem_object *obj, uint64_t *iova)
785{
786 struct msm_drm_private *priv = dev->dev_private;
787
788 if (!priv->gpu)
789 return -EINVAL;
790
791
792
793
794
795 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
796}
797
798static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
799 struct drm_file *file)
800{
801 struct drm_msm_gem_info *args = data;
802 struct drm_gem_object *obj;
803 struct msm_gem_object *msm_obj;
804 int i, ret = 0;
805
806 if (args->pad)
807 return -EINVAL;
808
809 switch (args->info) {
810 case MSM_INFO_GET_OFFSET:
811 case MSM_INFO_GET_IOVA:
812
813 if (args->len)
814 return -EINVAL;
815 break;
816 case MSM_INFO_SET_NAME:
817 case MSM_INFO_GET_NAME:
818 break;
819 default:
820 return -EINVAL;
821 }
822
823 obj = drm_gem_object_lookup(file, args->handle);
824 if (!obj)
825 return -ENOENT;
826
827 msm_obj = to_msm_bo(obj);
828
829 switch (args->info) {
830 case MSM_INFO_GET_OFFSET:
831 args->value = msm_gem_mmap_offset(obj);
832 break;
833 case MSM_INFO_GET_IOVA:
834 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
835 break;
836 case MSM_INFO_SET_NAME:
837
838 if (args->len >= sizeof(msm_obj->name)) {
839 ret = -EINVAL;
840 break;
841 }
842 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
843 args->len)) {
844 msm_obj->name[0] = '\0';
845 ret = -EFAULT;
846 break;
847 }
848 msm_obj->name[args->len] = '\0';
849 for (i = 0; i < args->len; i++) {
850 if (!isprint(msm_obj->name[i])) {
851 msm_obj->name[i] = '\0';
852 break;
853 }
854 }
855 break;
856 case MSM_INFO_GET_NAME:
857 if (args->value && (args->len < strlen(msm_obj->name))) {
858 ret = -EINVAL;
859 break;
860 }
861 args->len = strlen(msm_obj->name);
862 if (args->value) {
863 if (copy_to_user(u64_to_user_ptr(args->value),
864 msm_obj->name, args->len))
865 ret = -EFAULT;
866 }
867 break;
868 }
869
870 drm_gem_object_put_unlocked(obj);
871
872 return ret;
873}
874
875static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
876 struct drm_file *file)
877{
878 struct msm_drm_private *priv = dev->dev_private;
879 struct drm_msm_wait_fence *args = data;
880 ktime_t timeout = to_ktime(args->timeout);
881 struct msm_gpu_submitqueue *queue;
882 struct msm_gpu *gpu = priv->gpu;
883 int ret;
884
885 if (args->pad) {
886 DRM_ERROR("invalid pad: %08x\n", args->pad);
887 return -EINVAL;
888 }
889
890 if (!gpu)
891 return 0;
892
893 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
894 if (!queue)
895 return -ENOENT;
896
897 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
898 true);
899
900 msm_submitqueue_put(queue);
901 return ret;
902}
903
904static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
905 struct drm_file *file)
906{
907 struct drm_msm_gem_madvise *args = data;
908 struct drm_gem_object *obj;
909 int ret;
910
911 switch (args->madv) {
912 case MSM_MADV_DONTNEED:
913 case MSM_MADV_WILLNEED:
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 ret = mutex_lock_interruptible(&dev->struct_mutex);
920 if (ret)
921 return ret;
922
923 obj = drm_gem_object_lookup(file, args->handle);
924 if (!obj) {
925 ret = -ENOENT;
926 goto unlock;
927 }
928
929 ret = msm_gem_madvise(obj, args->madv);
930 if (ret >= 0) {
931 args->retained = ret;
932 ret = 0;
933 }
934
935 drm_gem_object_put(obj);
936
937unlock:
938 mutex_unlock(&dev->struct_mutex);
939 return ret;
940}
941
942
943static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
944 struct drm_file *file)
945{
946 struct drm_msm_submitqueue *args = data;
947
948 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
949 return -EINVAL;
950
951 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
952 args->flags, &args->id);
953}
954
955static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
956 struct drm_file *file)
957{
958 return msm_submitqueue_query(dev, file->driver_priv, data);
959}
960
961static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
962 struct drm_file *file)
963{
964 u32 id = *(u32 *) data;
965
966 return msm_submitqueue_remove(file->driver_priv, id);
967}
968
969static const struct drm_ioctl_desc msm_ioctls[] = {
970 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
971 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
973 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
975 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
977 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
979 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
980 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
981};
982
983static const struct vm_operations_struct vm_ops = {
984 .fault = msm_gem_fault,
985 .open = drm_gem_vm_open,
986 .close = drm_gem_vm_close,
987};
988
989static const struct file_operations fops = {
990 .owner = THIS_MODULE,
991 .open = drm_open,
992 .release = drm_release,
993 .unlocked_ioctl = drm_ioctl,
994 .compat_ioctl = drm_compat_ioctl,
995 .poll = drm_poll,
996 .read = drm_read,
997 .llseek = no_llseek,
998 .mmap = msm_gem_mmap,
999};
1000
1001static struct drm_driver msm_driver = {
1002 .driver_features = DRIVER_GEM |
1003 DRIVER_RENDER |
1004 DRIVER_ATOMIC |
1005 DRIVER_MODESET,
1006 .open = msm_open,
1007 .postclose = msm_postclose,
1008 .lastclose = drm_fb_helper_lastclose,
1009 .irq_handler = msm_irq,
1010 .irq_preinstall = msm_irq_preinstall,
1011 .irq_postinstall = msm_irq_postinstall,
1012 .irq_uninstall = msm_irq_uninstall,
1013 .gem_free_object_unlocked = msm_gem_free_object,
1014 .gem_vm_ops = &vm_ops,
1015 .dumb_create = msm_gem_dumb_create,
1016 .dumb_map_offset = msm_gem_dumb_map_offset,
1017 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1018 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1019 .gem_prime_pin = msm_gem_prime_pin,
1020 .gem_prime_unpin = msm_gem_prime_unpin,
1021 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1022 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1023 .gem_prime_vmap = msm_gem_prime_vmap,
1024 .gem_prime_vunmap = msm_gem_prime_vunmap,
1025 .gem_prime_mmap = msm_gem_prime_mmap,
1026#ifdef CONFIG_DEBUG_FS
1027 .debugfs_init = msm_debugfs_init,
1028#endif
1029 .ioctls = msm_ioctls,
1030 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1031 .fops = &fops,
1032 .name = "msm",
1033 .desc = "MSM Snapdragon DRM",
1034 .date = "20130625",
1035 .major = MSM_VERSION_MAJOR,
1036 .minor = MSM_VERSION_MINOR,
1037 .patchlevel = MSM_VERSION_PATCHLEVEL,
1038};
1039
1040#ifdef CONFIG_PM_SLEEP
1041static int msm_pm_suspend(struct device *dev)
1042{
1043 struct drm_device *ddev = dev_get_drvdata(dev);
1044 struct msm_drm_private *priv = ddev->dev_private;
1045
1046 if (WARN_ON(priv->pm_state))
1047 drm_atomic_state_put(priv->pm_state);
1048
1049 priv->pm_state = drm_atomic_helper_suspend(ddev);
1050 if (IS_ERR(priv->pm_state)) {
1051 int ret = PTR_ERR(priv->pm_state);
1052 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1053 return ret;
1054 }
1055
1056 return 0;
1057}
1058
1059static int msm_pm_resume(struct device *dev)
1060{
1061 struct drm_device *ddev = dev_get_drvdata(dev);
1062 struct msm_drm_private *priv = ddev->dev_private;
1063 int ret;
1064
1065 if (WARN_ON(!priv->pm_state))
1066 return -ENOENT;
1067
1068 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1069 if (!ret)
1070 priv->pm_state = NULL;
1071
1072 return ret;
1073}
1074#endif
1075
1076#ifdef CONFIG_PM
1077static int msm_runtime_suspend(struct device *dev)
1078{
1079 struct drm_device *ddev = dev_get_drvdata(dev);
1080 struct msm_drm_private *priv = ddev->dev_private;
1081 struct msm_mdss *mdss = priv->mdss;
1082
1083 DBG("");
1084
1085 if (mdss && mdss->funcs)
1086 return mdss->funcs->disable(mdss);
1087
1088 return 0;
1089}
1090
1091static int msm_runtime_resume(struct device *dev)
1092{
1093 struct drm_device *ddev = dev_get_drvdata(dev);
1094 struct msm_drm_private *priv = ddev->dev_private;
1095 struct msm_mdss *mdss = priv->mdss;
1096
1097 DBG("");
1098
1099 if (mdss && mdss->funcs)
1100 return mdss->funcs->enable(mdss);
1101
1102 return 0;
1103}
1104#endif
1105
1106static const struct dev_pm_ops msm_pm_ops = {
1107 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1108 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1109};
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119static int compare_of(struct device *dev, void *data)
1120{
1121 return dev->of_node == data;
1122}
1123
1124
1125
1126
1127
1128
1129
1130static int add_components_mdp(struct device *mdp_dev,
1131 struct component_match **matchptr)
1132{
1133 struct device_node *np = mdp_dev->of_node;
1134 struct device_node *ep_node;
1135 struct device *master_dev;
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145 if (of_device_is_compatible(np, "qcom,mdp4"))
1146 master_dev = mdp_dev;
1147 else
1148 master_dev = mdp_dev->parent;
1149
1150 for_each_endpoint_of_node(np, ep_node) {
1151 struct device_node *intf;
1152 struct of_endpoint ep;
1153 int ret;
1154
1155 ret = of_graph_parse_endpoint(ep_node, &ep);
1156 if (ret) {
1157 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1158 of_node_put(ep_node);
1159 return ret;
1160 }
1161
1162
1163
1164
1165
1166 if (of_device_is_compatible(np, "qcom,mdp4") &&
1167 ep.port == 0)
1168 continue;
1169
1170
1171
1172
1173
1174
1175 intf = of_graph_get_remote_port_parent(ep_node);
1176 if (!intf)
1177 continue;
1178
1179 if (of_device_is_available(intf))
1180 drm_of_component_match_add(master_dev, matchptr,
1181 compare_of, intf);
1182
1183 of_node_put(intf);
1184 }
1185
1186 return 0;
1187}
1188
1189static int compare_name_mdp(struct device *dev, void *data)
1190{
1191 return (strstr(dev_name(dev), "mdp") != NULL);
1192}
1193
1194static int add_display_components(struct device *dev,
1195 struct component_match **matchptr)
1196{
1197 struct device *mdp_dev;
1198 int ret;
1199
1200
1201
1202
1203
1204
1205
1206 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1207 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
1208 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
1209 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1210 if (ret) {
1211 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1212 return ret;
1213 }
1214
1215 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1216 if (!mdp_dev) {
1217 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1218 of_platform_depopulate(dev);
1219 return -ENODEV;
1220 }
1221
1222 put_device(mdp_dev);
1223
1224
1225 drm_of_component_match_add(dev, matchptr, compare_of,
1226 mdp_dev->of_node);
1227 } else {
1228
1229 mdp_dev = dev;
1230 }
1231
1232 ret = add_components_mdp(mdp_dev, matchptr);
1233 if (ret)
1234 of_platform_depopulate(dev);
1235
1236 return ret;
1237}
1238
1239
1240
1241
1242
1243
1244static const struct of_device_id msm_gpu_match[] = {
1245 { .compatible = "qcom,adreno" },
1246 { .compatible = "qcom,adreno-3xx" },
1247 { .compatible = "amd,imageon" },
1248 { .compatible = "qcom,kgsl-3d0" },
1249 { },
1250};
1251
1252static int add_gpu_components(struct device *dev,
1253 struct component_match **matchptr)
1254{
1255 struct device_node *np;
1256
1257 np = of_find_matching_node(NULL, msm_gpu_match);
1258 if (!np)
1259 return 0;
1260
1261 if (of_device_is_available(np))
1262 drm_of_component_match_add(dev, matchptr, compare_of, np);
1263
1264 of_node_put(np);
1265
1266 return 0;
1267}
1268
1269static int msm_drm_bind(struct device *dev)
1270{
1271 return msm_drm_init(dev, &msm_driver);
1272}
1273
1274static void msm_drm_unbind(struct device *dev)
1275{
1276 msm_drm_uninit(dev);
1277}
1278
1279static const struct component_master_ops msm_drm_ops = {
1280 .bind = msm_drm_bind,
1281 .unbind = msm_drm_unbind,
1282};
1283
1284
1285
1286
1287
1288static int msm_pdev_probe(struct platform_device *pdev)
1289{
1290 struct component_match *match = NULL;
1291 int ret;
1292
1293 if (get_mdp_ver(pdev)) {
1294 ret = add_display_components(&pdev->dev, &match);
1295 if (ret)
1296 return ret;
1297 }
1298
1299 ret = add_gpu_components(&pdev->dev, &match);
1300 if (ret)
1301 goto fail;
1302
1303
1304
1305
1306 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1307 if (ret)
1308 goto fail;
1309
1310 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1311 if (ret)
1312 goto fail;
1313
1314 return 0;
1315
1316fail:
1317 of_platform_depopulate(&pdev->dev);
1318 return ret;
1319}
1320
1321static int msm_pdev_remove(struct platform_device *pdev)
1322{
1323 component_master_del(&pdev->dev, &msm_drm_ops);
1324 of_platform_depopulate(&pdev->dev);
1325
1326 return 0;
1327}
1328
1329static const struct of_device_id dt_match[] = {
1330 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1331 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1332 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1333 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1334 {}
1335};
1336MODULE_DEVICE_TABLE(of, dt_match);
1337
1338static struct platform_driver msm_platform_driver = {
1339 .probe = msm_pdev_probe,
1340 .remove = msm_pdev_remove,
1341 .driver = {
1342 .name = "msm",
1343 .of_match_table = dt_match,
1344 .pm = &msm_pm_ops,
1345 },
1346};
1347
1348static int __init msm_drm_register(void)
1349{
1350 if (!modeset)
1351 return -EINVAL;
1352
1353 DBG("init");
1354 msm_mdp_register();
1355 msm_dpu_register();
1356 msm_dsi_register();
1357 msm_edp_register();
1358 msm_hdmi_register();
1359 adreno_register();
1360 return platform_driver_register(&msm_platform_driver);
1361}
1362
1363static void __exit msm_drm_unregister(void)
1364{
1365 DBG("fini");
1366 platform_driver_unregister(&msm_platform_driver);
1367 msm_hdmi_unregister();
1368 adreno_unregister();
1369 msm_edp_unregister();
1370 msm_dsi_unregister();
1371 msm_mdp_unregister();
1372 msm_dpu_unregister();
1373}
1374
1375module_init(msm_drm_register);
1376module_exit(msm_drm_unregister);
1377
1378MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1379MODULE_DESCRIPTION("MSM DRM Driver");
1380MODULE_LICENSE("GPL");
1381