LXR linux/drivers/gpu/drm/nouveau/nouveau

   1/*
   2 * Copyright (C) 2007 Ben Skeggs.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining
   6 * a copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sublicense, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the
  14 * next paragraph) shall be included in all copies or substantial
  15 * portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24 *
  25 */
  26
  27#ifndef __NOUVEAU_DMA_H__
  28#define __NOUVEAU_DMA_H__
  29
  30#include "nouveau_bo.h"
  31#include "nouveau_chan.h"
  32
  33int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
  34void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
  35
  36/*
  37 * There's a hw race condition where you can't jump to your PUT offset,
  38 * to avoid this we jump to offset + SKIPS and fill the difference with
  39 * NOPs.
  40 *
  41 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
  42 * a SKIPS value of 8.  Lets assume that the race condition is to do
  43 * with writing into the fetch area, we configure a fetch size of 128
  44 * bytes so we need a larger SKIPS value.
  45 */
  46#define NOUVEAU_DMA_SKIPS (128 / 4)
  47
  48/* Hardcoded object assignments to subchannels (subchannel id). */
  49enum {
  50        NvSubCtxSurf2D  = 0,
  51        NvSubSw         = 1,
  52        NvSubImageBlit  = 2,
  53        NvSubGdiRect    = 3,
  54
  55        NvSub2D         = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
  56        NvSubCopy       = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
  57};
  58
  59/* Object handles - for stuff that's doesn't use handle == oclass. */
  60enum {
  61        NvDmaFB         = 0x80000002,
  62        NvDmaTT         = 0x80000003,
  63        NvNotify0       = 0x80000006,
  64        NvSema          = 0x8000000f,
  65        NvEvoSema0      = 0x80000010,
  66        NvEvoSema1      = 0x80000011,
  67};
  68
  69#define NV_MEMORY_TO_MEMORY_FORMAT                                    0x00000039
  70#define NV_MEMORY_TO_MEMORY_FORMAT_NAME                               0x00000000
  71#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF                            0x00000050
  72#define NV_MEMORY_TO_MEMORY_FORMAT_NOP                                0x00000100
  73#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY                             0x00000104
  74#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE                 0x00000000
  75#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN       0x00000001
  76#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY                         0x00000180
  77#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE                         0x00000184
  78#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN                          0x0000030c
  79
  80#define NV50_MEMORY_TO_MEMORY_FORMAT                                  0x00005039
  81#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200                           0x00000200
  82#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C                           0x0000021c
  83#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH                   0x00000238
  84#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH                  0x0000023c
  85
  86static __must_check inline int
  87RING_SPACE(struct nouveau_channel *chan, int size)
  88{
  89        int ret;
  90
  91        ret = nouveau_dma_wait(chan, 1, size);
  92        if (ret)
  93                return ret;
  94
  95        chan->dma.free -= size;
  96        return 0;
  97}
  98
  99static inline void
 100OUT_RING(struct nouveau_channel *chan, int data)
 101{
 102        nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
 103}
 104
 105extern void
 106OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
 107
 108static inline void
 109BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
 110{
 111        OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
 112}
 113
 114static inline void
 115BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
 116{
 117        OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
 118}
 119
 120static inline void
 121BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
 122{
 123        OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
 124}
 125
 126static inline void
 127BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
 128{
 129        OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
 130}
 131
 132static inline void
 133BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
 134{
 135        OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
 136}
 137
 138#define WRITE_PUT(val) do {                                                    \
 139        mb();                                                   \
 140        nouveau_bo_rd32(chan->push.buffer, 0);                                 \
 141        nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
 142} while (0)
 143
 144static inline void
 145FIRE_RING(struct nouveau_channel *chan)
 146{
 147        if (chan->dma.cur == chan->dma.put)
 148                return;
 149        chan->accel_done = true;
 150
 151        if (chan->dma.ib_max) {
 152                nv50_dma_push(chan, chan->push.addr + (chan->dma.put << 2),
 153                              (chan->dma.cur - chan->dma.put) << 2);
 154        } else {
 155                WRITE_PUT(chan->dma.cur);
 156        }
 157
 158        chan->dma.put = chan->dma.cur;
 159}
 160
 161static inline void
 162WIND_RING(struct nouveau_channel *chan)
 163{
 164        chan->dma.cur = chan->dma.put;
 165}
 166
 167/* FIFO methods */
 168#define NV01_SUBCHAN_OBJECT                                          0x00000000
 169#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH                          0x00000010
 170#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW                           0x00000014
 171#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE                              0x00000018
 172#define NV84_SUBCHAN_SEMAPHORE_TRIGGER                               0x0000001c
 173#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001
 174#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002
 175#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004
 176#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD                         0x00001000
 177#define NV84_SUBCHAN_UEVENT                                          0x00000020
 178#define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024
 179#define NV10_SUBCHAN_REF_CNT                                         0x00000050
 180#define NV11_SUBCHAN_DMA_SEMAPHORE                                   0x00000060
 181#define NV11_SUBCHAN_SEMAPHORE_OFFSET                                0x00000064
 182#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE                               0x00000068
 183#define NV11_SUBCHAN_SEMAPHORE_RELEASE                               0x0000006c
 184#define NV40_SUBCHAN_YIELD                                           0x00000080
 185
 186/* NV_SW object class */
 187#define NV_SW_DMA_VBLSEM                                             0x0000018c
 188#define NV_SW_VBLSEM_OFFSET                                          0x00000400
 189#define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
 190#define NV_SW_VBLSEM_RELEASE                                         0x00000408
 191#define NV_SW_PAGE_FLIP                                              0x00000500
 192
 193#endif
 194