LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c

   1/*
   2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20 * DEALINGS IN THE SOFTWARE.
  21 */
  22#include "ctxgf100.h"
  23#include "gf100.h"
  24
  25#include <subdev/mc.h>
  26
  27static void
  28gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
  29{
  30        struct nvkm_device *device = gr->base.engine.subdev.device;
  31        const struct gf100_grctx_func *grctx = gr->func->grctx;
  32        u32 idle_timeout;
  33        int i;
  34
  35        gf100_gr_mmio(gr, gr->sw_ctx);
  36
  37        gf100_gr_wait_idle(gr);
  38
  39        idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
  40
  41        grctx->attrib(info);
  42
  43        grctx->unkn(gr);
  44
  45        gf100_grctx_generate_floorsweep(gr);
  46
  47        for (i = 0; i < 8; i++)
  48                nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
  49
  50        nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
  51
  52        nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000);
  53
  54        gf100_gr_wait_idle(gr);
  55
  56        nvkm_wr32(device, 0x404154, idle_timeout);
  57        gf100_gr_wait_idle(gr);
  58
  59        gf100_gr_mthd(gr, gr->method);
  60        gf100_gr_wait_idle(gr);
  61
  62        gf100_gr_icmd(gr, gr->bundle);
  63        grctx->pagepool(info);
  64        grctx->bundle(info);
  65}
  66
  67const struct gf100_grctx_func
  68gk20a_grctx = {
  69        .main  = gk20a_grctx_generate_main,
  70        .unkn  = gk104_grctx_generate_unkn,
  71        .bundle = gk104_grctx_generate_bundle,
  72        .bundle_size = 0x1800,
  73        .bundle_min_gpm_fifo_depth = 0x62,
  74        .bundle_token_limit = 0x100,
  75        .pagepool = gk104_grctx_generate_pagepool,
  76        .pagepool_size = 0x8000,
  77        .attrib = gf117_grctx_generate_attrib,
  78        .attrib_nr_max = 0x240,
  79        .attrib_nr = 0x240,
  80        .alpha_nr_max = 0x648 + (0x648 / 2),
  81        .alpha_nr = 0x648,
  82        .sm_id = gf100_grctx_generate_sm_id,
  83        .tpc_nr = gf100_grctx_generate_tpc_nr,
  84        .rop_mapping = gf117_grctx_generate_rop_mapping,
  85        .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables,
  86};
  87