linux/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4 * Author:Mark Yao <mark.yao@rock-chips.com>
   5 */
   6
   7#ifndef _ROCKCHIP_DRM_VOP_H
   8#define _ROCKCHIP_DRM_VOP_H
   9
  10/*
  11 * major: IP major version, used for IP structure
  12 * minor: big feature change under same structure
  13 */
  14#define VOP_VERSION(major, minor)       ((major) << 8 | (minor))
  15#define VOP_MAJOR(version)              ((version) >> 8)
  16#define VOP_MINOR(version)              ((version) & 0xff)
  17
  18#define NUM_YUV2YUV_COEFFICIENTS 12
  19
  20enum vop_data_format {
  21        VOP_FMT_ARGB8888 = 0,
  22        VOP_FMT_RGB888,
  23        VOP_FMT_RGB565,
  24        VOP_FMT_YUV420SP = 4,
  25        VOP_FMT_YUV422SP,
  26        VOP_FMT_YUV444SP,
  27};
  28
  29struct vop_reg {
  30        uint32_t mask;
  31        uint16_t offset;
  32        uint8_t shift;
  33        bool write_mask;
  34        bool relaxed;
  35};
  36
  37struct vop_modeset {
  38        struct vop_reg htotal_pw;
  39        struct vop_reg hact_st_end;
  40        struct vop_reg hpost_st_end;
  41        struct vop_reg vtotal_pw;
  42        struct vop_reg vact_st_end;
  43        struct vop_reg vpost_st_end;
  44};
  45
  46struct vop_output {
  47        struct vop_reg pin_pol;
  48        struct vop_reg dp_pin_pol;
  49        struct vop_reg dp_dclk_pol;
  50        struct vop_reg edp_pin_pol;
  51        struct vop_reg edp_dclk_pol;
  52        struct vop_reg hdmi_pin_pol;
  53        struct vop_reg hdmi_dclk_pol;
  54        struct vop_reg mipi_pin_pol;
  55        struct vop_reg mipi_dclk_pol;
  56        struct vop_reg rgb_pin_pol;
  57        struct vop_reg rgb_dclk_pol;
  58        struct vop_reg dp_en;
  59        struct vop_reg edp_en;
  60        struct vop_reg hdmi_en;
  61        struct vop_reg mipi_en;
  62        struct vop_reg mipi_dual_channel_en;
  63        struct vop_reg rgb_en;
  64};
  65
  66struct vop_common {
  67        struct vop_reg cfg_done;
  68        struct vop_reg dsp_blank;
  69        struct vop_reg data_blank;
  70        struct vop_reg pre_dither_down;
  71        struct vop_reg dither_down_sel;
  72        struct vop_reg dither_down_mode;
  73        struct vop_reg dither_down_en;
  74        struct vop_reg dither_up;
  75        struct vop_reg dsp_lut_en;
  76        struct vop_reg gate_en;
  77        struct vop_reg mmu_en;
  78        struct vop_reg out_mode;
  79        struct vop_reg standby;
  80};
  81
  82struct vop_misc {
  83        struct vop_reg global_regdone_en;
  84};
  85
  86struct vop_intr {
  87        const int *intrs;
  88        uint32_t nintrs;
  89
  90        struct vop_reg line_flag_num[2];
  91        struct vop_reg enable;
  92        struct vop_reg clear;
  93        struct vop_reg status;
  94};
  95
  96struct vop_scl_extension {
  97        struct vop_reg cbcr_vsd_mode;
  98        struct vop_reg cbcr_vsu_mode;
  99        struct vop_reg cbcr_hsd_mode;
 100        struct vop_reg cbcr_ver_scl_mode;
 101        struct vop_reg cbcr_hor_scl_mode;
 102        struct vop_reg yrgb_vsd_mode;
 103        struct vop_reg yrgb_vsu_mode;
 104        struct vop_reg yrgb_hsd_mode;
 105        struct vop_reg yrgb_ver_scl_mode;
 106        struct vop_reg yrgb_hor_scl_mode;
 107        struct vop_reg line_load_mode;
 108        struct vop_reg cbcr_axi_gather_num;
 109        struct vop_reg yrgb_axi_gather_num;
 110        struct vop_reg vsd_cbcr_gt2;
 111        struct vop_reg vsd_cbcr_gt4;
 112        struct vop_reg vsd_yrgb_gt2;
 113        struct vop_reg vsd_yrgb_gt4;
 114        struct vop_reg bic_coe_sel;
 115        struct vop_reg cbcr_axi_gather_en;
 116        struct vop_reg yrgb_axi_gather_en;
 117        struct vop_reg lb_mode;
 118};
 119
 120struct vop_scl_regs {
 121        const struct vop_scl_extension *ext;
 122
 123        struct vop_reg scale_yrgb_x;
 124        struct vop_reg scale_yrgb_y;
 125        struct vop_reg scale_cbcr_x;
 126        struct vop_reg scale_cbcr_y;
 127};
 128
 129struct vop_yuv2yuv_phy {
 130        struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
 131};
 132
 133struct vop_win_phy {
 134        const struct vop_scl_regs *scl;
 135        const uint32_t *data_formats;
 136        uint32_t nformats;
 137
 138        struct vop_reg enable;
 139        struct vop_reg gate;
 140        struct vop_reg format;
 141        struct vop_reg rb_swap;
 142        struct vop_reg act_info;
 143        struct vop_reg dsp_info;
 144        struct vop_reg dsp_st;
 145        struct vop_reg yrgb_mst;
 146        struct vop_reg uv_mst;
 147        struct vop_reg yrgb_vir;
 148        struct vop_reg uv_vir;
 149        struct vop_reg y_mir_en;
 150        struct vop_reg x_mir_en;
 151
 152        struct vop_reg dst_alpha_ctl;
 153        struct vop_reg src_alpha_ctl;
 154        struct vop_reg channel;
 155};
 156
 157struct vop_win_yuv2yuv_data {
 158        uint32_t base;
 159        const struct vop_yuv2yuv_phy *phy;
 160        struct vop_reg y2r_en;
 161};
 162
 163struct vop_win_data {
 164        uint32_t base;
 165        const struct vop_win_phy *phy;
 166        enum drm_plane_type type;
 167};
 168
 169struct vop_data {
 170        uint32_t version;
 171        const struct vop_intr *intr;
 172        const struct vop_common *common;
 173        const struct vop_misc *misc;
 174        const struct vop_modeset *modeset;
 175        const struct vop_output *output;
 176        const struct vop_win_yuv2yuv_data *win_yuv2yuv;
 177        const struct vop_win_data *win;
 178        unsigned int win_size;
 179        unsigned int lut_size;
 180
 181#define VOP_FEATURE_OUTPUT_RGB10        BIT(0)
 182#define VOP_FEATURE_INTERNAL_RGB        BIT(1)
 183        u64 feature;
 184};
 185
 186/* interrupt define */
 187#define DSP_HOLD_VALID_INTR             (1 << 0)
 188#define FS_INTR                         (1 << 1)
 189#define LINE_FLAG_INTR                  (1 << 2)
 190#define BUS_ERROR_INTR                  (1 << 3)
 191
 192#define INTR_MASK                       (DSP_HOLD_VALID_INTR | FS_INTR | \
 193                                         LINE_FLAG_INTR | BUS_ERROR_INTR)
 194
 195#define DSP_HOLD_VALID_INTR_EN(x)       ((x) << 4)
 196#define FS_INTR_EN(x)                   ((x) << 5)
 197#define LINE_FLAG_INTR_EN(x)            ((x) << 6)
 198#define BUS_ERROR_INTR_EN(x)            ((x) << 7)
 199#define DSP_HOLD_VALID_INTR_MASK        (1 << 4)
 200#define FS_INTR_MASK                    (1 << 5)
 201#define LINE_FLAG_INTR_MASK             (1 << 6)
 202#define BUS_ERROR_INTR_MASK             (1 << 7)
 203
 204#define INTR_CLR_SHIFT                  8
 205#define DSP_HOLD_VALID_INTR_CLR         (1 << (INTR_CLR_SHIFT + 0))
 206#define FS_INTR_CLR                     (1 << (INTR_CLR_SHIFT + 1))
 207#define LINE_FLAG_INTR_CLR              (1 << (INTR_CLR_SHIFT + 2))
 208#define BUS_ERROR_INTR_CLR              (1 << (INTR_CLR_SHIFT + 3))
 209
 210#define DSP_LINE_NUM(x)                 (((x) & 0x1fff) << 12)
 211#define DSP_LINE_NUM_MASK               (0x1fff << 12)
 212
 213/* src alpha ctrl define */
 214#define SRC_FADING_VALUE(x)             (((x) & 0xff) << 24)
 215#define SRC_GLOBAL_ALPHA(x)             (((x) & 0xff) << 16)
 216#define SRC_FACTOR_M0(x)                (((x) & 0x7) << 6)
 217#define SRC_ALPHA_CAL_M0(x)             (((x) & 0x1) << 5)
 218#define SRC_BLEND_M0(x)                 (((x) & 0x3) << 3)
 219#define SRC_ALPHA_M0(x)                 (((x) & 0x1) << 2)
 220#define SRC_COLOR_M0(x)                 (((x) & 0x1) << 1)
 221#define SRC_ALPHA_EN(x)                 (((x) & 0x1) << 0)
 222/* dst alpha ctrl define */
 223#define DST_FACTOR_M0(x)                (((x) & 0x7) << 6)
 224
 225/*
 226 * display output interface supported by rockchip lcdc
 227 */
 228#define ROCKCHIP_OUT_MODE_P888  0
 229#define ROCKCHIP_OUT_MODE_P666  1
 230#define ROCKCHIP_OUT_MODE_P565  2
 231/* for use special outface */
 232#define ROCKCHIP_OUT_MODE_AAAA  15
 233
 234/* output flags */
 235#define ROCKCHIP_OUTPUT_DSI_DUAL        BIT(0)
 236
 237enum alpha_mode {
 238        ALPHA_STRAIGHT,
 239        ALPHA_INVERSE,
 240};
 241
 242enum global_blend_mode {
 243        ALPHA_GLOBAL,
 244        ALPHA_PER_PIX,
 245        ALPHA_PER_PIX_GLOBAL,
 246};
 247
 248enum alpha_cal_mode {
 249        ALPHA_SATURATION,
 250        ALPHA_NO_SATURATION,
 251};
 252
 253enum color_mode {
 254        ALPHA_SRC_PRE_MUL,
 255        ALPHA_SRC_NO_PRE_MUL,
 256};
 257
 258enum factor_mode {
 259        ALPHA_ZERO,
 260        ALPHA_ONE,
 261        ALPHA_SRC,
 262        ALPHA_SRC_INVERSE,
 263        ALPHA_SRC_GLOBAL,
 264};
 265
 266enum scale_mode {
 267        SCALE_NONE = 0x0,
 268        SCALE_UP   = 0x1,
 269        SCALE_DOWN = 0x2
 270};
 271
 272enum lb_mode {
 273        LB_YUV_3840X5 = 0x0,
 274        LB_YUV_2560X8 = 0x1,
 275        LB_RGB_3840X2 = 0x2,
 276        LB_RGB_2560X4 = 0x3,
 277        LB_RGB_1920X5 = 0x4,
 278        LB_RGB_1280X8 = 0x5
 279};
 280
 281enum sacle_up_mode {
 282        SCALE_UP_BIL = 0x0,
 283        SCALE_UP_BIC = 0x1
 284};
 285
 286enum scale_down_mode {
 287        SCALE_DOWN_BIL = 0x0,
 288        SCALE_DOWN_AVG = 0x1
 289};
 290
 291enum dither_down_mode {
 292        RGB888_TO_RGB565 = 0x0,
 293        RGB888_TO_RGB666 = 0x1
 294};
 295
 296enum dither_down_mode_sel {
 297        DITHER_DOWN_ALLEGRO = 0x0,
 298        DITHER_DOWN_FRC = 0x1
 299};
 300
 301enum vop_pol {
 302        HSYNC_POSITIVE = 0,
 303        VSYNC_POSITIVE = 1,
 304        DEN_NEGATIVE   = 2
 305};
 306
 307#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 308#define SCL_FT_DEFAULT_FIXPOINT_SHIFT   12
 309#define SCL_MAX_VSKIPLINES              4
 310#define MIN_SCL_FT_AFTER_VSKIP          1
 311
 312static inline uint16_t scl_cal_scale(int src, int dst, int shift)
 313{
 314        return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
 315}
 316
 317static inline uint16_t scl_cal_scale2(int src, int dst)
 318{
 319        return ((src - 1) << 12) / (dst - 1);
 320}
 321
 322#define GET_SCL_FT_BILI_DN(src, dst)    scl_cal_scale(src, dst, 12)
 323#define GET_SCL_FT_BILI_UP(src, dst)    scl_cal_scale(src, dst, 16)
 324#define GET_SCL_FT_BIC(src, dst)        scl_cal_scale(src, dst, 16)
 325
 326static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
 327                                             int vskiplines)
 328{
 329        int act_height;
 330
 331        act_height = DIV_ROUND_UP(src_h, vskiplines);
 332
 333        if (act_height == dst_h)
 334                return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
 335
 336        return GET_SCL_FT_BILI_DN(act_height, dst_h);
 337}
 338
 339static inline enum scale_mode scl_get_scl_mode(int src, int dst)
 340{
 341        if (src < dst)
 342                return SCALE_UP;
 343        else if (src > dst)
 344                return SCALE_DOWN;
 345
 346        return SCALE_NONE;
 347}
 348
 349static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
 350{
 351        uint32_t vskiplines;
 352
 353        for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
 354                if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
 355                        break;
 356
 357        return vskiplines;
 358}
 359
 360static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
 361{
 362        int lb_mode;
 363
 364        if (is_yuv) {
 365                if (width > 1280)
 366                        lb_mode = LB_YUV_3840X5;
 367                else
 368                        lb_mode = LB_YUV_2560X8;
 369        } else {
 370                if (width > 2560)
 371                        lb_mode = LB_RGB_3840X2;
 372                else if (width > 1920)
 373                        lb_mode = LB_RGB_2560X4;
 374                else
 375                        lb_mode = LB_RGB_1920X5;
 376        }
 377
 378        return lb_mode;
 379}
 380
 381extern const struct component_ops vop_component_ops;
 382#endif /* _ROCKCHIP_DRM_VOP_H */
 383