linux/drivers/net/ethernet/smsc/epic100.c
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   1/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
   2/*
   3        Written/copyright 1997-2001 by Donald Becker.
   4
   5        This software may be used and distributed according to the terms of
   6        the GNU General Public License (GPL), incorporated herein by reference.
   7        Drivers based on or derived from this code fall under the GPL and must
   8        retain the authorship, copyright and license notice.  This file is not
   9        a complete program and may only be used when the entire operating
  10        system is licensed under the GPL.
  11
  12        This driver is for the SMC83c170/175 "EPIC" series, as used on the
  13        SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
  14
  15        The author may be reached as becker@scyld.com, or C/O
  16        Scyld Computing Corporation
  17        410 Severn Ave., Suite 210
  18        Annapolis MD 21403
  19
  20        Information and updates available at
  21        http://www.scyld.com/network/epic100.html
  22        [this link no longer provides anything useful -jgarzik]
  23
  24        ---------------------------------------------------------------------
  25
  26*/
  27
  28#define DRV_NAME        "epic100"
  29#define DRV_VERSION     "2.1"
  30#define DRV_RELDATE     "Sept 11, 2006"
  31
  32/* The user-configurable values.
  33   These may be modified when a driver module is loaded.*/
  34
  35static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */
  36
  37/* Used to pass the full-duplex flag, etc. */
  38#define MAX_UNITS 8             /* More are supported, limit only on options */
  39static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  40static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  41
  42/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  43   Setting to > 1518 effectively disables this feature. */
  44static int rx_copybreak;
  45
  46/* Operational parameters that are set at compile time. */
  47
  48/* Keep the ring sizes a power of two for operational efficiency.
  49   The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  50   Making the Tx ring too large decreases the effectiveness of channel
  51   bonding and packet priority.
  52   There are no ill effects from too-large receive rings. */
  53#define TX_RING_SIZE    256
  54#define TX_QUEUE_LEN    240             /* Limit ring entries actually used.  */
  55#define RX_RING_SIZE    256
  56#define TX_TOTAL_SIZE   TX_RING_SIZE*sizeof(struct epic_tx_desc)
  57#define RX_TOTAL_SIZE   RX_RING_SIZE*sizeof(struct epic_rx_desc)
  58
  59/* Operational parameters that usually are not changed. */
  60/* Time in jiffies before concluding the transmitter is hung. */
  61#define TX_TIMEOUT  (2*HZ)
  62
  63#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/
  64
  65/* Bytes transferred to chip before transmission starts. */
  66/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
  67#define TX_FIFO_THRESH 256
  68#define RX_FIFO_THRESH 1                /* 0-3, 0==32, 64,96, or 3==128 bytes  */
  69
  70#include <linux/module.h>
  71#include <linux/kernel.h>
  72#include <linux/string.h>
  73#include <linux/timer.h>
  74#include <linux/errno.h>
  75#include <linux/ioport.h>
  76#include <linux/interrupt.h>
  77#include <linux/pci.h>
  78#include <linux/delay.h>
  79#include <linux/netdevice.h>
  80#include <linux/etherdevice.h>
  81#include <linux/skbuff.h>
  82#include <linux/init.h>
  83#include <linux/spinlock.h>
  84#include <linux/ethtool.h>
  85#include <linux/mii.h>
  86#include <linux/crc32.h>
  87#include <linux/bitops.h>
  88#include <asm/io.h>
  89#include <linux/uaccess.h>
  90#include <asm/byteorder.h>
  91
  92/* These identify the driver base version and may not be removed. */
  93static char version[] =
  94DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>";
  95static char version2[] =
  96"  (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")";
  97
  98MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
  99MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
 100MODULE_LICENSE("GPL");
 101
 102module_param(debug, int, 0);
 103module_param(rx_copybreak, int, 0);
 104module_param_array(options, int, NULL, 0);
 105module_param_array(full_duplex, int, NULL, 0);
 106MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
 107MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
 108MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
 109MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
 110
 111/*
 112                                Theory of Operation
 113
 114I. Board Compatibility
 115
 116This device driver is designed for the SMC "EPIC/100", the SMC
 117single-chip Ethernet controllers for PCI.  This chip is used on
 118the SMC EtherPower II boards.
 119
 120II. Board-specific settings
 121
 122PCI bus devices are configured by the system at boot time, so no jumpers
 123need to be set on the board.  The system BIOS will assign the
 124PCI INTA signal to a (preferably otherwise unused) system IRQ line.
 125Note: Kernel versions earlier than 1.3.73 do not support shared PCI
 126interrupt lines.
 127
 128III. Driver operation
 129
 130IIIa. Ring buffers
 131
 132IVb. References
 133
 134http://www.smsc.com/media/Downloads_Public/discontinued/83c171.pdf
 135http://www.smsc.com/media/Downloads_Public/discontinued/83c175.pdf
 136http://scyld.com/expert/NWay.html
 137http://www.national.com/pf/DP/DP83840A.html
 138
 139IVc. Errata
 140
 141*/
 142
 143
 144enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
 145
 146#define EPIC_TOTAL_SIZE 0x100
 147#define USE_IO_OPS 1
 148
 149#ifdef USE_IO_OPS
 150#define EPIC_BAR        0
 151#else
 152#define EPIC_BAR        1
 153#endif
 154
 155typedef enum {
 156        SMSC_83C170_0,
 157        SMSC_83C170,
 158        SMSC_83C175,
 159} chip_t;
 160
 161
 162struct epic_chip_info {
 163        const char *name;
 164        int drv_flags;                          /* Driver use, intended as capability flags. */
 165};
 166
 167
 168/* indexed by chip_t */
 169static const struct epic_chip_info pci_id_tbl[] = {
 170        { "SMSC EPIC/100 83c170",       TYPE2_INTR | NO_MII | MII_PWRDWN },
 171        { "SMSC EPIC/100 83c170",       TYPE2_INTR },
 172        { "SMSC EPIC/C 83c175",         TYPE2_INTR | MII_PWRDWN },
 173};
 174
 175
 176static const struct pci_device_id epic_pci_tbl[] = {
 177        { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
 178        { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
 179        { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
 180          PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
 181        { 0,}
 182};
 183MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
 184
 185#define ew16(reg, val)  iowrite16(val, ioaddr + (reg))
 186#define ew32(reg, val)  iowrite32(val, ioaddr + (reg))
 187#define er8(reg)        ioread8(ioaddr + (reg))
 188#define er16(reg)       ioread16(ioaddr + (reg))
 189#define er32(reg)       ioread32(ioaddr + (reg))
 190
 191/* Offsets to registers, using the (ugh) SMC names. */
 192enum epic_registers {
 193  COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
 194  PCIBurstCnt=0x18,
 195  TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28,     /* Rx error counters. */
 196  MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
 197  LAN0=64,                                              /* MAC address. */
 198  MC0=80,                                               /* Multicast filter table. */
 199  RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
 200  PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
 201};
 202
 203/* Interrupt register bits, using my own meaningful names. */
 204enum IntrStatus {
 205        TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
 206        PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
 207        RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
 208        TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
 209        RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
 210};
 211enum CommandBits {
 212        StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
 213        StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
 214};
 215
 216#define EpicRemoved     0xffffffff      /* Chip failed or removed (CardBus) */
 217
 218#define EpicNapiEvent   (TxEmpty | TxDone | \
 219                         RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
 220#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
 221
 222static const u16 media2miictl[16] = {
 223        0, 0x0C00, 0x0C00, 0x2000,  0x0100, 0x2100, 0, 0,
 224        0, 0, 0, 0,  0, 0, 0, 0 };
 225
 226/*
 227 * The EPIC100 Rx and Tx buffer descriptors.  Note that these
 228 * really ARE host-endian; it's not a misannotation.  We tell
 229 * the card to byteswap them internally on big-endian hosts -
 230 * look for #ifdef __BIG_ENDIAN in epic_open().
 231 */
 232
 233struct epic_tx_desc {
 234        u32 txstatus;
 235        u32 bufaddr;
 236        u32 buflength;
 237        u32 next;
 238};
 239
 240struct epic_rx_desc {
 241        u32 rxstatus;
 242        u32 bufaddr;
 243        u32 buflength;
 244        u32 next;
 245};
 246
 247enum desc_status_bits {
 248        DescOwn=0x8000,
 249};
 250
 251#define PRIV_ALIGN      15      /* Required alignment mask */
 252struct epic_private {
 253        struct epic_rx_desc *rx_ring;
 254        struct epic_tx_desc *tx_ring;
 255        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 256        struct sk_buff* tx_skbuff[TX_RING_SIZE];
 257        /* The addresses of receive-in-place skbuffs. */
 258        struct sk_buff* rx_skbuff[RX_RING_SIZE];
 259
 260        dma_addr_t tx_ring_dma;
 261        dma_addr_t rx_ring_dma;
 262
 263        /* Ring pointers. */
 264        spinlock_t lock;                                /* Group with Tx control cache line. */
 265        spinlock_t napi_lock;
 266        struct napi_struct napi;
 267        unsigned int cur_tx, dirty_tx;
 268
 269        unsigned int cur_rx, dirty_rx;
 270        u32 irq_mask;
 271        unsigned int rx_buf_sz;                         /* Based on MTU+slack. */
 272
 273        void __iomem *ioaddr;
 274        struct pci_dev *pci_dev;                        /* PCI bus location. */
 275        int chip_id, chip_flags;
 276
 277        struct timer_list timer;                        /* Media selection timer. */
 278        int tx_threshold;
 279        unsigned char mc_filter[8];
 280        signed char phys[4];                            /* MII device addresses. */
 281        u16 advertising;                                        /* NWay media advertisement */
 282        int mii_phy_cnt;
 283        u32 ethtool_ops_nesting;
 284        struct mii_if_info mii;
 285        unsigned int tx_full:1;                         /* The Tx queue is full. */
 286        unsigned int default_port:4;            /* Last dev->if_port value. */
 287};
 288
 289static int epic_open(struct net_device *dev);
 290static int read_eeprom(struct epic_private *, int);
 291static int mdio_read(struct net_device *dev, int phy_id, int location);
 292static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
 293static void epic_restart(struct net_device *dev);
 294static void epic_timer(struct timer_list *t);
 295static void epic_tx_timeout(struct net_device *dev, unsigned int txqueue);
 296static void epic_init_ring(struct net_device *dev);
 297static netdev_tx_t epic_start_xmit(struct sk_buff *skb,
 298                                   struct net_device *dev);
 299static int epic_rx(struct net_device *dev, int budget);
 300static int epic_poll(struct napi_struct *napi, int budget);
 301static irqreturn_t epic_interrupt(int irq, void *dev_instance);
 302static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 303static const struct ethtool_ops netdev_ethtool_ops;
 304static int epic_close(struct net_device *dev);
 305static struct net_device_stats *epic_get_stats(struct net_device *dev);
 306static void set_rx_mode(struct net_device *dev);
 307
 308static const struct net_device_ops epic_netdev_ops = {
 309        .ndo_open               = epic_open,
 310        .ndo_stop               = epic_close,
 311        .ndo_start_xmit         = epic_start_xmit,
 312        .ndo_tx_timeout         = epic_tx_timeout,
 313        .ndo_get_stats          = epic_get_stats,
 314        .ndo_set_rx_mode        = set_rx_mode,
 315        .ndo_do_ioctl           = netdev_ioctl,
 316        .ndo_set_mac_address    = eth_mac_addr,
 317        .ndo_validate_addr      = eth_validate_addr,
 318};
 319
 320static int epic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 321{
 322        static int card_idx = -1;
 323        void __iomem *ioaddr;
 324        int chip_idx = (int) ent->driver_data;
 325        struct net_device *dev;
 326        struct epic_private *ep;
 327        int i, ret, option = 0, duplex = 0;
 328        void *ring_space;
 329        dma_addr_t ring_dma;
 330
 331/* when built into the kernel, we only print version if device is found */
 332#ifndef MODULE
 333        pr_info_once("%s%s\n", version, version2);
 334#endif
 335
 336        card_idx++;
 337
 338        ret = pci_enable_device(pdev);
 339        if (ret)
 340                goto out;
 341
 342        if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
 343                dev_err(&pdev->dev, "no PCI region space\n");
 344                ret = -ENODEV;
 345                goto err_out_disable;
 346        }
 347
 348        pci_set_master(pdev);
 349
 350        ret = pci_request_regions(pdev, DRV_NAME);
 351        if (ret < 0)
 352                goto err_out_disable;
 353
 354        ret = -ENOMEM;
 355
 356        dev = alloc_etherdev(sizeof (*ep));
 357        if (!dev)
 358                goto err_out_free_res;
 359
 360        SET_NETDEV_DEV(dev, &pdev->dev);
 361
 362        ioaddr = pci_iomap(pdev, EPIC_BAR, 0);
 363        if (!ioaddr) {
 364                dev_err(&pdev->dev, "ioremap failed\n");
 365                goto err_out_free_netdev;
 366        }
 367
 368        pci_set_drvdata(pdev, dev);
 369        ep = netdev_priv(dev);
 370        ep->ioaddr = ioaddr;
 371        ep->mii.dev = dev;
 372        ep->mii.mdio_read = mdio_read;
 373        ep->mii.mdio_write = mdio_write;
 374        ep->mii.phy_id_mask = 0x1f;
 375        ep->mii.reg_num_mask = 0x1f;
 376
 377        ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
 378        if (!ring_space)
 379                goto err_out_iounmap;
 380        ep->tx_ring = ring_space;
 381        ep->tx_ring_dma = ring_dma;
 382
 383        ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
 384        if (!ring_space)
 385                goto err_out_unmap_tx;
 386        ep->rx_ring = ring_space;
 387        ep->rx_ring_dma = ring_dma;
 388
 389        if (dev->mem_start) {
 390                option = dev->mem_start;
 391                duplex = (dev->mem_start & 16) ? 1 : 0;
 392        } else if (card_idx >= 0  &&  card_idx < MAX_UNITS) {
 393                if (options[card_idx] >= 0)
 394                        option = options[card_idx];
 395                if (full_duplex[card_idx] >= 0)
 396                        duplex = full_duplex[card_idx];
 397        }
 398
 399        spin_lock_init(&ep->lock);
 400        spin_lock_init(&ep->napi_lock);
 401
 402        /* Bring the chip out of low-power mode. */
 403        ew32(GENCTL, 0x4200);
 404        /* Magic?!  If we don't set this bit the MII interface won't work. */
 405        /* This magic is documented in SMSC app note 7.15 */
 406        for (i = 16; i > 0; i--)
 407                ew32(TEST1, 0x0008);
 408
 409        /* Turn on the MII transceiver. */
 410        ew32(MIICfg, 0x12);
 411        if (chip_idx == 1)
 412                ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);
 413        ew32(GENCTL, 0x0200);
 414
 415        /* Note: the '175 does not have a serial EEPROM. */
 416        for (i = 0; i < 3; i++)
 417                ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(er16(LAN0 + i*4));
 418
 419        if (debug > 2) {
 420                dev_dbg(&pdev->dev, "EEPROM contents:\n");
 421                for (i = 0; i < 64; i++)
 422                        pr_cont(" %4.4x%s", read_eeprom(ep, i),
 423                                   i % 16 == 15 ? "\n" : "");
 424        }
 425
 426        ep->pci_dev = pdev;
 427        ep->chip_id = chip_idx;
 428        ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
 429        ep->irq_mask =
 430                (ep->chip_flags & TYPE2_INTR ?  PCIBusErr175 : PCIBusErr170)
 431                 | CntFull | TxUnderrun | EpicNapiEvent;
 432
 433        /* Find the connected MII xcvrs.
 434           Doing this in open() would allow detecting external xcvrs later, but
 435           takes much time and no cards have external MII. */
 436        {
 437                int phy, phy_idx = 0;
 438                for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
 439                        int mii_status = mdio_read(dev, phy, MII_BMSR);
 440                        if (mii_status != 0xffff  &&  mii_status != 0x0000) {
 441                                ep->phys[phy_idx++] = phy;
 442                                dev_info(&pdev->dev,
 443                                        "MII transceiver #%d control "
 444                                        "%4.4x status %4.4x.\n",
 445                                        phy, mdio_read(dev, phy, 0), mii_status);
 446                        }
 447                }
 448                ep->mii_phy_cnt = phy_idx;
 449                if (phy_idx != 0) {
 450                        phy = ep->phys[0];
 451                        ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
 452                        dev_info(&pdev->dev,
 453                                "Autonegotiation advertising %4.4x link "
 454                                   "partner %4.4x.\n",
 455                                   ep->mii.advertising, mdio_read(dev, phy, 5));
 456                } else if ( ! (ep->chip_flags & NO_MII)) {
 457                        dev_warn(&pdev->dev,
 458                                "***WARNING***: No MII transceiver found!\n");
 459                        /* Use the known PHY address of the EPII. */
 460                        ep->phys[0] = 3;
 461                }
 462                ep->mii.phy_id = ep->phys[0];
 463        }
 464
 465        /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
 466        if (ep->chip_flags & MII_PWRDWN)
 467                ew32(NVCTL, er32(NVCTL) & ~0x483c);
 468        ew32(GENCTL, 0x0008);
 469
 470        /* The lower four bits are the media type. */
 471        if (duplex) {
 472                ep->mii.force_media = ep->mii.full_duplex = 1;
 473                dev_info(&pdev->dev, "Forced full duplex requested.\n");
 474        }
 475        dev->if_port = ep->default_port = option;
 476
 477        /* The Epic-specific entries in the device structure. */
 478        dev->netdev_ops = &epic_netdev_ops;
 479        dev->ethtool_ops = &netdev_ethtool_ops;
 480        dev->watchdog_timeo = TX_TIMEOUT;
 481        netif_napi_add(dev, &ep->napi, epic_poll, 64);
 482
 483        ret = register_netdev(dev);
 484        if (ret < 0)
 485                goto err_out_unmap_rx;
 486
 487        netdev_info(dev, "%s at %lx, IRQ %d, %pM\n",
 488                    pci_id_tbl[chip_idx].name,
 489                    (long)pci_resource_start(pdev, EPIC_BAR), pdev->irq,
 490                    dev->dev_addr);
 491
 492out:
 493        return ret;
 494
 495err_out_unmap_rx:
 496        pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
 497err_out_unmap_tx:
 498        pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
 499err_out_iounmap:
 500        pci_iounmap(pdev, ioaddr);
 501err_out_free_netdev:
 502        free_netdev(dev);
 503err_out_free_res:
 504        pci_release_regions(pdev);
 505err_out_disable:
 506        pci_disable_device(pdev);
 507        goto out;
 508}
 509
 510/* Serial EEPROM section. */
 511
 512/*  EEPROM_Ctrl bits. */
 513#define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 514#define EE_CS                   0x02    /* EEPROM chip select. */
 515#define EE_DATA_WRITE   0x08    /* EEPROM chip data in. */
 516#define EE_WRITE_0              0x01
 517#define EE_WRITE_1              0x09
 518#define EE_DATA_READ    0x10    /* EEPROM chip data out. */
 519#define EE_ENB                  (0x0001 | EE_CS)
 520
 521/* Delay between EEPROM clock transitions.
 522   This serves to flush the operation to the PCI bus.
 523 */
 524
 525#define eeprom_delay()  er32(EECTL)
 526
 527/* The EEPROM commands include the alway-set leading bit. */
 528#define EE_WRITE_CMD    (5 << 6)
 529#define EE_READ64_CMD   (6 << 6)
 530#define EE_READ256_CMD  (6 << 8)
 531#define EE_ERASE_CMD    (7 << 6)
 532
 533static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
 534{
 535        void __iomem *ioaddr = ep->ioaddr;
 536
 537        ew32(INTMASK, 0x00000000);
 538}
 539
 540static inline void __epic_pci_commit(void __iomem *ioaddr)
 541{
 542#ifndef USE_IO_OPS
 543        er32(INTMASK);
 544#endif
 545}
 546
 547static inline void epic_napi_irq_off(struct net_device *dev,
 548                                     struct epic_private *ep)
 549{
 550        void __iomem *ioaddr = ep->ioaddr;
 551
 552        ew32(INTMASK, ep->irq_mask & ~EpicNapiEvent);
 553        __epic_pci_commit(ioaddr);
 554}
 555
 556static inline void epic_napi_irq_on(struct net_device *dev,
 557                                    struct epic_private *ep)
 558{
 559        void __iomem *ioaddr = ep->ioaddr;
 560
 561        /* No need to commit possible posted write */
 562        ew32(INTMASK, ep->irq_mask | EpicNapiEvent);
 563}
 564
 565static int read_eeprom(struct epic_private *ep, int location)
 566{
 567        void __iomem *ioaddr = ep->ioaddr;
 568        int i;
 569        int retval = 0;
 570        int read_cmd = location |
 571                (er32(EECTL) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
 572
 573        ew32(EECTL, EE_ENB & ~EE_CS);
 574        ew32(EECTL, EE_ENB);
 575
 576        /* Shift the read command bits out. */
 577        for (i = 12; i >= 0; i--) {
 578                short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
 579                ew32(EECTL, EE_ENB | dataval);
 580                eeprom_delay();
 581                ew32(EECTL, EE_ENB | dataval | EE_SHIFT_CLK);
 582                eeprom_delay();
 583        }
 584        ew32(EECTL, EE_ENB);
 585
 586        for (i = 16; i > 0; i--) {
 587                ew32(EECTL, EE_ENB | EE_SHIFT_CLK);
 588                eeprom_delay();
 589                retval = (retval << 1) | ((er32(EECTL) & EE_DATA_READ) ? 1 : 0);
 590                ew32(EECTL, EE_ENB);
 591                eeprom_delay();
 592        }
 593
 594        /* Terminate the EEPROM access. */
 595        ew32(EECTL, EE_ENB & ~EE_CS);
 596        return retval;
 597}
 598
 599#define MII_READOP              1
 600#define MII_WRITEOP             2
 601static int mdio_read(struct net_device *dev, int phy_id, int location)
 602{
 603        struct epic_private *ep = netdev_priv(dev);
 604        void __iomem *ioaddr = ep->ioaddr;
 605        int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
 606        int i;
 607
 608        ew32(MIICtrl, read_cmd);
 609        /* Typical operation takes 25 loops. */
 610        for (i = 400; i > 0; i--) {
 611                barrier();
 612                if ((er32(MIICtrl) & MII_READOP) == 0) {
 613                        /* Work around read failure bug. */
 614                        if (phy_id == 1 && location < 6 &&
 615                            er16(MIIData) == 0xffff) {
 616                                ew32(MIICtrl, read_cmd);
 617                                continue;
 618                        }
 619                        return er16(MIIData);
 620                }
 621        }
 622        return 0xffff;
 623}
 624
 625static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
 626{
 627        struct epic_private *ep = netdev_priv(dev);
 628        void __iomem *ioaddr = ep->ioaddr;
 629        int i;
 630
 631        ew16(MIIData, value);
 632        ew32(MIICtrl, (phy_id << 9) | (loc << 4) | MII_WRITEOP);
 633        for (i = 10000; i > 0; i--) {
 634                barrier();
 635                if ((er32(MIICtrl) & MII_WRITEOP) == 0)
 636                        break;
 637        }
 638}
 639
 640
 641static int epic_open(struct net_device *dev)
 642{
 643        struct epic_private *ep = netdev_priv(dev);
 644        void __iomem *ioaddr = ep->ioaddr;
 645        const int irq = ep->pci_dev->irq;
 646        int rc, i;
 647
 648        /* Soft reset the chip. */
 649        ew32(GENCTL, 0x4001);
 650
 651        napi_enable(&ep->napi);
 652        rc = request_irq(irq, epic_interrupt, IRQF_SHARED, dev->name, dev);
 653        if (rc) {
 654                napi_disable(&ep->napi);
 655                return rc;
 656        }
 657
 658        epic_init_ring(dev);
 659
 660        ew32(GENCTL, 0x4000);
 661        /* This magic is documented in SMSC app note 7.15 */
 662        for (i = 16; i > 0; i--)
 663                ew32(TEST1, 0x0008);
 664
 665        /* Pull the chip out of low-power mode, enable interrupts, and set for
 666           PCI read multiple.  The MIIcfg setting and strange write order are
 667           required by the details of which bits are reset and the transceiver
 668           wiring on the Ositech CardBus card.
 669        */
 670#if 0
 671        ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12);
 672#endif
 673        if (ep->chip_flags & MII_PWRDWN)
 674                ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);
 675
 676        /* Tell the chip to byteswap descriptors on big-endian hosts */
 677#ifdef __BIG_ENDIAN
 678        ew32(GENCTL, 0x4432 | (RX_FIFO_THRESH << 8));
 679        er32(GENCTL);
 680        ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8));
 681#else
 682        ew32(GENCTL, 0x4412 | (RX_FIFO_THRESH << 8));
 683        er32(GENCTL);
 684        ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8));
 685#endif
 686
 687        udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
 688
 689        for (i = 0; i < 3; i++)
 690                ew32(LAN0 + i*4, le16_to_cpu(((__le16*)dev->dev_addr)[i]));
 691
 692        ep->tx_threshold = TX_FIFO_THRESH;
 693        ew32(TxThresh, ep->tx_threshold);
 694
 695        if (media2miictl[dev->if_port & 15]) {
 696                if (ep->mii_phy_cnt)
 697                        mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
 698                if (dev->if_port == 1) {
 699                        if (debug > 1)
 700                                netdev_info(dev, "Using the 10base2 transceiver, MII status %4.4x.\n",
 701                                            mdio_read(dev, ep->phys[0], MII_BMSR));
 702                }
 703        } else {
 704                int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
 705                if (mii_lpa != 0xffff) {
 706                        if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
 707                                ep->mii.full_duplex = 1;
 708                        else if (! (mii_lpa & LPA_LPACK))
 709                                mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
 710                        if (debug > 1)
 711                                netdev_info(dev, "Setting %s-duplex based on MII xcvr %d register read of %4.4x.\n",
 712                                            ep->mii.full_duplex ? "full"
 713                                                                : "half",
 714                                            ep->phys[0], mii_lpa);
 715                }
 716        }
 717
 718        ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79);
 719        ew32(PRxCDAR, ep->rx_ring_dma);
 720        ew32(PTxCDAR, ep->tx_ring_dma);
 721
 722        /* Start the chip's Rx process. */
 723        set_rx_mode(dev);
 724        ew32(COMMAND, StartRx | RxQueued);
 725
 726        netif_start_queue(dev);
 727
 728        /* Enable interrupts by setting the interrupt mask. */
 729        ew32(INTMASK, RxError | RxHeader | EpicNapiEvent | CntFull |
 730             ((ep->chip_flags & TYPE2_INTR) ? PCIBusErr175 : PCIBusErr170) |
 731             TxUnderrun);
 732
 733        if (debug > 1) {
 734                netdev_dbg(dev, "epic_open() ioaddr %p IRQ %d status %4.4x %s-duplex.\n",
 735                           ioaddr, irq, er32(GENCTL),
 736                           ep->mii.full_duplex ? "full" : "half");
 737        }
 738
 739        /* Set the timer to switch to check for link beat and perhaps switch
 740           to an alternate media type. */
 741        timer_setup(&ep->timer, epic_timer, 0);
 742        ep->timer.expires = jiffies + 3*HZ;
 743        add_timer(&ep->timer);
 744
 745        return rc;
 746}
 747
 748/* Reset the chip to recover from a PCI transaction error.
 749   This may occur at interrupt time. */
 750static void epic_pause(struct net_device *dev)
 751{
 752        struct net_device_stats *stats = &dev->stats;
 753        struct epic_private *ep = netdev_priv(dev);
 754        void __iomem *ioaddr = ep->ioaddr;
 755
 756        netif_stop_queue (dev);
 757
 758        /* Disable interrupts by clearing the interrupt mask. */
 759        ew32(INTMASK, 0x00000000);
 760        /* Stop the chip's Tx and Rx DMA processes. */
 761        ew16(COMMAND, StopRx | StopTxDMA | StopRxDMA);
 762
 763        /* Update the error counts. */
 764        if (er16(COMMAND) != 0xffff) {
 765                stats->rx_missed_errors += er8(MPCNT);
 766                stats->rx_frame_errors  += er8(ALICNT);
 767                stats->rx_crc_errors    += er8(CRCCNT);
 768        }
 769
 770        /* Remove the packets on the Rx queue. */
 771        epic_rx(dev, RX_RING_SIZE);
 772}
 773
 774static void epic_restart(struct net_device *dev)
 775{
 776        struct epic_private *ep = netdev_priv(dev);
 777        void __iomem *ioaddr = ep->ioaddr;
 778        int i;
 779
 780        /* Soft reset the chip. */
 781        ew32(GENCTL, 0x4001);
 782
 783        netdev_dbg(dev, "Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
 784                   ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
 785        udelay(1);
 786
 787        /* This magic is documented in SMSC app note 7.15 */
 788        for (i = 16; i > 0; i--)
 789                ew32(TEST1, 0x0008);
 790
 791#ifdef __BIG_ENDIAN
 792        ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8));
 793#else
 794        ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8));
 795#endif
 796        ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12);
 797        if (ep->chip_flags & MII_PWRDWN)
 798                ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);
 799
 800        for (i = 0; i < 3; i++)
 801                ew32(LAN0 + i*4, le16_to_cpu(((__le16*)dev->dev_addr)[i]));
 802
 803        ep->tx_threshold = TX_FIFO_THRESH;
 804        ew32(TxThresh, ep->tx_threshold);
 805        ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79);
 806        ew32(PRxCDAR, ep->rx_ring_dma +
 807             (ep->cur_rx % RX_RING_SIZE) * sizeof(struct epic_rx_desc));
 808        ew32(PTxCDAR, ep->tx_ring_dma +
 809             (ep->dirty_tx % TX_RING_SIZE) * sizeof(struct epic_tx_desc));
 810
 811        /* Start the chip's Rx process. */
 812        set_rx_mode(dev);
 813        ew32(COMMAND, StartRx | RxQueued);
 814
 815        /* Enable interrupts by setting the interrupt mask. */
 816        ew32(INTMASK, RxError | RxHeader | EpicNapiEvent | CntFull |
 817             ((ep->chip_flags & TYPE2_INTR) ? PCIBusErr175 : PCIBusErr170) |
 818             TxUnderrun);
 819
 820        netdev_dbg(dev, "epic_restart() done, cmd status %4.4x, ctl %4.4x interrupt %4.4x.\n",
 821                   er32(COMMAND), er32(GENCTL), er32(INTSTAT));
 822}
 823
 824static void check_media(struct net_device *dev)
 825{
 826        struct epic_private *ep = netdev_priv(dev);
 827        void __iomem *ioaddr = ep->ioaddr;
 828        int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
 829        int negotiated = mii_lpa & ep->mii.advertising;
 830        int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
 831
 832        if (ep->mii.force_media)
 833                return;
 834        if (mii_lpa == 0xffff)          /* Bogus read */
 835                return;
 836        if (ep->mii.full_duplex != duplex) {
 837                ep->mii.full_duplex = duplex;
 838                netdev_info(dev, "Setting %s-duplex based on MII #%d link partner capability of %4.4x.\n",
 839                            ep->mii.full_duplex ? "full" : "half",
 840                            ep->phys[0], mii_lpa);
 841                ew32(TxCtrl, ep->mii.full_duplex ? 0x7F : 0x79);
 842        }
 843}
 844
 845static void epic_timer(struct timer_list *t)
 846{
 847        struct epic_private *ep = from_timer(ep, t, timer);
 848        struct net_device *dev = ep->mii.dev;
 849        void __iomem *ioaddr = ep->ioaddr;
 850        int next_tick = 5*HZ;
 851
 852        if (debug > 3) {
 853                netdev_dbg(dev, "Media monitor tick, Tx status %8.8x.\n",
 854                           er32(TxSTAT));
 855                netdev_dbg(dev, "Other registers are IntMask %4.4x IntStatus %4.4x RxStatus %4.4x.\n",
 856                           er32(INTMASK), er32(INTSTAT), er32(RxSTAT));
 857        }
 858
 859        check_media(dev);
 860
 861        ep->timer.expires = jiffies + next_tick;
 862        add_timer(&ep->timer);
 863}
 864
 865static void epic_tx_timeout(struct net_device *dev, unsigned int txqueue)
 866{
 867        struct epic_private *ep = netdev_priv(dev);
 868        void __iomem *ioaddr = ep->ioaddr;
 869
 870        if (debug > 0) {
 871                netdev_warn(dev, "Transmit timeout using MII device, Tx status %4.4x.\n",
 872                            er16(TxSTAT));
 873                if (debug > 1) {
 874                        netdev_dbg(dev, "Tx indices: dirty_tx %d, cur_tx %d.\n",
 875                                   ep->dirty_tx, ep->cur_tx);
 876                }
 877        }
 878        if (er16(TxSTAT) & 0x10) {              /* Tx FIFO underflow. */
 879                dev->stats.tx_fifo_errors++;
 880                ew32(COMMAND, RestartTx);
 881        } else {
 882                epic_restart(dev);
 883                ew32(COMMAND, TxQueued);
 884        }
 885
 886        netif_trans_update(dev); /* prevent tx timeout */
 887        dev->stats.tx_errors++;
 888        if (!ep->tx_full)
 889                netif_wake_queue(dev);
 890}
 891
 892/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
 893static void epic_init_ring(struct net_device *dev)
 894{
 895        struct epic_private *ep = netdev_priv(dev);
 896        int i;
 897
 898        ep->tx_full = 0;
 899        ep->dirty_tx = ep->cur_tx = 0;
 900        ep->cur_rx = ep->dirty_rx = 0;
 901        ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
 902
 903        /* Initialize all Rx descriptors. */
 904        for (i = 0; i < RX_RING_SIZE; i++) {
 905                ep->rx_ring[i].rxstatus = 0;
 906                ep->rx_ring[i].buflength = ep->rx_buf_sz;
 907                ep->rx_ring[i].next = ep->rx_ring_dma +
 908                                      (i+1)*sizeof(struct epic_rx_desc);
 909                ep->rx_skbuff[i] = NULL;
 910        }
 911        /* Mark the last entry as wrapping the ring. */
 912        ep->rx_ring[i-1].next = ep->rx_ring_dma;
 913
 914        /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
 915        for (i = 0; i < RX_RING_SIZE; i++) {
 916                struct sk_buff *skb = netdev_alloc_skb(dev, ep->rx_buf_sz + 2);
 917                ep->rx_skbuff[i] = skb;
 918                if (skb == NULL)
 919                        break;
 920                skb_reserve(skb, 2);    /* 16 byte align the IP header. */
 921                ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
 922                        skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
 923                ep->rx_ring[i].rxstatus = DescOwn;
 924        }
 925        ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
 926
 927        /* The Tx buffer descriptor is filled in as needed, but we
 928           do need to clear the ownership bit. */
 929        for (i = 0; i < TX_RING_SIZE; i++) {
 930                ep->tx_skbuff[i] = NULL;
 931                ep->tx_ring[i].txstatus = 0x0000;
 932                ep->tx_ring[i].next = ep->tx_ring_dma +
 933                        (i+1)*sizeof(struct epic_tx_desc);
 934        }
 935        ep->tx_ring[i-1].next = ep->tx_ring_dma;
 936}
 937
 938static netdev_tx_t epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
 939{
 940        struct epic_private *ep = netdev_priv(dev);
 941        void __iomem *ioaddr = ep->ioaddr;
 942        int entry, free_count;
 943        u32 ctrl_word;
 944        unsigned long flags;
 945
 946        if (skb_padto(skb, ETH_ZLEN))
 947                return NETDEV_TX_OK;
 948
 949        /* Caution: the write order is important here, set the field with the
 950           "ownership" bit last. */
 951
 952        /* Calculate the next Tx descriptor entry. */
 953        spin_lock_irqsave(&ep->lock, flags);
 954        free_count = ep->cur_tx - ep->dirty_tx;
 955        entry = ep->cur_tx % TX_RING_SIZE;
 956
 957        ep->tx_skbuff[entry] = skb;
 958        ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
 959                                                    skb->len, PCI_DMA_TODEVICE);
 960        if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
 961                ctrl_word = 0x100000; /* No interrupt */
 962        } else if (free_count == TX_QUEUE_LEN/2) {
 963                ctrl_word = 0x140000; /* Tx-done intr. */
 964        } else if (free_count < TX_QUEUE_LEN - 1) {
 965                ctrl_word = 0x100000; /* No Tx-done intr. */
 966        } else {
 967                /* Leave room for an additional entry. */
 968                ctrl_word = 0x140000; /* Tx-done intr. */
 969                ep->tx_full = 1;
 970        }
 971        ep->tx_ring[entry].buflength = ctrl_word | skb->len;
 972        ep->tx_ring[entry].txstatus =
 973                ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
 974                            | DescOwn;
 975
 976        ep->cur_tx++;
 977        if (ep->tx_full)
 978                netif_stop_queue(dev);
 979
 980        spin_unlock_irqrestore(&ep->lock, flags);
 981        /* Trigger an immediate transmit demand. */
 982        ew32(COMMAND, TxQueued);
 983
 984        if (debug > 4)
 985                netdev_dbg(dev, "Queued Tx packet size %d to slot %d, flag %2.2x Tx status %8.8x.\n",
 986                           skb->len, entry, ctrl_word, er32(TxSTAT));
 987
 988        return NETDEV_TX_OK;
 989}
 990
 991static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
 992                          int status)
 993{
 994        struct net_device_stats *stats = &dev->stats;
 995
 996#ifndef final_version
 997        /* There was an major error, log it. */
 998        if (debug > 1)
 999                netdev_dbg(dev, "Transmit error, Tx status %8.8x.\n",
1000                           status);
1001#endif
1002        stats->tx_errors++;
1003        if (status & 0x1050)
1004                stats->tx_aborted_errors++;
1005        if (status & 0x0008)
1006                stats->tx_carrier_errors++;
1007        if (status & 0x0040)
1008                stats->tx_window_errors++;
1009        if (status & 0x0010)
1010                stats->tx_fifo_errors++;
1011}
1012
1013static void epic_tx(struct net_device *dev, struct epic_private *ep)
1014{
1015        unsigned int dirty_tx, cur_tx;
1016
1017        /*
1018         * Note: if this lock becomes a problem we can narrow the locked
1019         * region at the cost of occasionally grabbing the lock more times.
1020         */
1021        cur_tx = ep->cur_tx;
1022        for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1023                struct sk_buff *skb;
1024                int entry = dirty_tx % TX_RING_SIZE;
1025                int txstatus = ep->tx_ring[entry].txstatus;
1026
1027                if (txstatus & DescOwn)
1028                        break;  /* It still hasn't been Txed */
1029
1030                if (likely(txstatus & 0x0001)) {
1031                        dev->stats.collisions += (txstatus >> 8) & 15;
1032                        dev->stats.tx_packets++;
1033                        dev->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1034                } else
1035                        epic_tx_error(dev, ep, txstatus);
1036
1037                /* Free the original skb. */
1038                skb = ep->tx_skbuff[entry];
1039                pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1040                                 skb->len, PCI_DMA_TODEVICE);
1041                dev_consume_skb_irq(skb);
1042                ep->tx_skbuff[entry] = NULL;
1043        }
1044
1045#ifndef final_version
1046        if (cur_tx - dirty_tx > TX_RING_SIZE) {
1047                netdev_warn(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1048                            dirty_tx, cur_tx, ep->tx_full);
1049                dirty_tx += TX_RING_SIZE;
1050        }
1051#endif
1052        ep->dirty_tx = dirty_tx;
1053        if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1054                /* The ring is no longer full, allow new TX entries. */
1055                ep->tx_full = 0;
1056                netif_wake_queue(dev);
1057        }
1058}
1059
1060/* The interrupt handler does all of the Rx thread work and cleans up
1061   after the Tx thread. */
1062static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1063{
1064        struct net_device *dev = dev_instance;
1065        struct epic_private *ep = netdev_priv(dev);
1066        void __iomem *ioaddr = ep->ioaddr;
1067        unsigned int handled = 0;
1068        int status;
1069
1070        status = er32(INTSTAT);
1071        /* Acknowledge all of the current interrupt sources ASAP. */
1072        ew32(INTSTAT, status & EpicNormalEvent);
1073
1074        if (debug > 4) {
1075                netdev_dbg(dev, "Interrupt, status=%#8.8x new intstat=%#8.8x.\n",
1076                           status, er32(INTSTAT));
1077        }
1078
1079        if ((status & IntrSummary) == 0)
1080                goto out;
1081
1082        handled = 1;
1083
1084        if (status & EpicNapiEvent) {
1085                spin_lock(&ep->napi_lock);
1086                if (napi_schedule_prep(&ep->napi)) {
1087                        epic_napi_irq_off(dev, ep);
1088                        __napi_schedule(&ep->napi);
1089                }
1090                spin_unlock(&ep->napi_lock);
1091        }
1092        status &= ~EpicNapiEvent;
1093
1094        /* Check uncommon events all at once. */
1095        if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1096                struct net_device_stats *stats = &dev->stats;
1097
1098                if (status == EpicRemoved)
1099                        goto out;
1100
1101                /* Always update the error counts to avoid overhead later. */
1102                stats->rx_missed_errors += er8(MPCNT);
1103                stats->rx_frame_errors  += er8(ALICNT);
1104                stats->rx_crc_errors    += er8(CRCCNT);
1105
1106                if (status & TxUnderrun) { /* Tx FIFO underflow. */
1107                        stats->tx_fifo_errors++;
1108                        ew32(TxThresh, ep->tx_threshold += 128);
1109                        /* Restart the transmit process. */
1110                        ew32(COMMAND, RestartTx);
1111                }
1112                if (status & PCIBusErr170) {
1113                        netdev_err(dev, "PCI Bus Error! status %4.4x.\n",
1114                                   status);
1115                        epic_pause(dev);
1116                        epic_restart(dev);
1117                }
1118                /* Clear all error sources. */
1119                ew32(INTSTAT, status & 0x7f18);
1120        }
1121
1122out:
1123        if (debug > 3) {
1124                netdev_dbg(dev, "exit interrupt, intr_status=%#4.4x.\n",
1125                           status);
1126        }
1127
1128        return IRQ_RETVAL(handled);
1129}
1130
1131static int epic_rx(struct net_device *dev, int budget)
1132{
1133        struct epic_private *ep = netdev_priv(dev);
1134        int entry = ep->cur_rx % RX_RING_SIZE;
1135        int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1136        int work_done = 0;
1137
1138        if (debug > 4)
1139                netdev_dbg(dev, " In epic_rx(), entry %d %8.8x.\n", entry,
1140                           ep->rx_ring[entry].rxstatus);
1141
1142        if (rx_work_limit > budget)
1143                rx_work_limit = budget;
1144
1145        /* If we own the next entry, it's a new packet. Send it up. */
1146        while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
1147                int status = ep->rx_ring[entry].rxstatus;
1148
1149                if (debug > 4)
1150                        netdev_dbg(dev, "  epic_rx() status was %8.8x.\n",
1151                                   status);
1152                if (--rx_work_limit < 0)
1153                        break;
1154                if (status & 0x2006) {
1155                        if (debug > 2)
1156                                netdev_dbg(dev, "epic_rx() error status was %8.8x.\n",
1157                                           status);
1158                        if (status & 0x2000) {
1159                                netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %4.4x!\n",
1160                                            status);
1161                                dev->stats.rx_length_errors++;
1162                        } else if (status & 0x0006)
1163                                /* Rx Frame errors are counted in hardware. */
1164                                dev->stats.rx_errors++;
1165                } else {
1166                        /* Malloc up new buffer, compatible with net-2e. */
1167                        /* Omit the four octet CRC from the length. */
1168                        short pkt_len = (status >> 16) - 4;
1169                        struct sk_buff *skb;
1170
1171                        if (pkt_len > PKT_BUF_SZ - 4) {
1172                                netdev_err(dev, "Oversized Ethernet frame, status %x %d bytes.\n",
1173                                           status, pkt_len);
1174                                pkt_len = 1514;
1175                        }
1176                        /* Check if the packet is long enough to accept without copying
1177                           to a minimally-sized skbuff. */
1178                        if (pkt_len < rx_copybreak &&
1179                            (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1180                                skb_reserve(skb, 2);    /* 16 byte align the IP header */
1181                                pci_dma_sync_single_for_cpu(ep->pci_dev,
1182                                                            ep->rx_ring[entry].bufaddr,
1183                                                            ep->rx_buf_sz,
1184                                                            PCI_DMA_FROMDEVICE);
1185                                skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1186                                skb_put(skb, pkt_len);
1187                                pci_dma_sync_single_for_device(ep->pci_dev,
1188                                                               ep->rx_ring[entry].bufaddr,
1189                                                               ep->rx_buf_sz,
1190                                                               PCI_DMA_FROMDEVICE);
1191                        } else {
1192                                pci_unmap_single(ep->pci_dev,
1193                                        ep->rx_ring[entry].bufaddr,
1194                                        ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1195                                skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1196                                ep->rx_skbuff[entry] = NULL;
1197                        }
1198                        skb->protocol = eth_type_trans(skb, dev);
1199                        netif_receive_skb(skb);
1200                        dev->stats.rx_packets++;
1201                        dev->stats.rx_bytes += pkt_len;
1202                }
1203                work_done++;
1204                entry = (++ep->cur_rx) % RX_RING_SIZE;
1205        }
1206
1207        /* Refill the Rx ring buffers. */
1208        for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1209                entry = ep->dirty_rx % RX_RING_SIZE;
1210                if (ep->rx_skbuff[entry] == NULL) {
1211                        struct sk_buff *skb;
1212                        skb = ep->rx_skbuff[entry] = netdev_alloc_skb(dev, ep->rx_buf_sz + 2);
1213                        if (skb == NULL)
1214                                break;
1215                        skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
1216                        ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1217                                skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1218                        work_done++;
1219                }
1220                /* AV: shouldn't we add a barrier here? */
1221                ep->rx_ring[entry].rxstatus = DescOwn;
1222        }
1223        return work_done;
1224}
1225
1226static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1227{
1228        void __iomem *ioaddr = ep->ioaddr;
1229        int status;
1230
1231        status = er32(INTSTAT);
1232
1233        if (status == EpicRemoved)
1234                return;
1235        if (status & RxOverflow)        /* Missed a Rx frame. */
1236                dev->stats.rx_errors++;
1237        if (status & (RxOverflow | RxFull))
1238                ew16(COMMAND, RxQueued);
1239}
1240
1241static int epic_poll(struct napi_struct *napi, int budget)
1242{
1243        struct epic_private *ep = container_of(napi, struct epic_private, napi);
1244        struct net_device *dev = ep->mii.dev;
1245        void __iomem *ioaddr = ep->ioaddr;
1246        int work_done;
1247
1248        epic_tx(dev, ep);
1249
1250        work_done = epic_rx(dev, budget);
1251
1252        epic_rx_err(dev, ep);
1253
1254        if (work_done < budget && napi_complete_done(napi, work_done)) {
1255                unsigned long flags;
1256
1257                spin_lock_irqsave(&ep->napi_lock, flags);
1258
1259                ew32(INTSTAT, EpicNapiEvent);
1260                epic_napi_irq_on(dev, ep);
1261                spin_unlock_irqrestore(&ep->napi_lock, flags);
1262        }
1263
1264        return work_done;
1265}
1266
1267static int epic_close(struct net_device *dev)
1268{
1269        struct epic_private *ep = netdev_priv(dev);
1270        struct pci_dev *pdev = ep->pci_dev;
1271        void __iomem *ioaddr = ep->ioaddr;
1272        struct sk_buff *skb;
1273        int i;
1274
1275        netif_stop_queue(dev);
1276        napi_disable(&ep->napi);
1277
1278        if (debug > 1)
1279                netdev_dbg(dev, "Shutting down ethercard, status was %2.2x.\n",
1280                           er32(INTSTAT));
1281
1282        del_timer_sync(&ep->timer);
1283
1284        epic_disable_int(dev, ep);
1285
1286        free_irq(pdev->irq, dev);
1287
1288        epic_pause(dev);
1289
1290        /* Free all the skbuffs in the Rx queue. */
1291        for (i = 0; i < RX_RING_SIZE; i++) {
1292                skb = ep->rx_skbuff[i];
1293                ep->rx_skbuff[i] = NULL;
1294                ep->rx_ring[i].rxstatus = 0;            /* Not owned by Epic chip. */
1295                ep->rx_ring[i].buflength = 0;
1296                if (skb) {
1297                        pci_unmap_single(pdev, ep->rx_ring[i].bufaddr,
1298                                         ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1299                        dev_kfree_skb(skb);
1300                }
1301                ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1302        }
1303        for (i = 0; i < TX_RING_SIZE; i++) {
1304                skb = ep->tx_skbuff[i];
1305                ep->tx_skbuff[i] = NULL;
1306                if (!skb)
1307                        continue;
1308                pci_unmap_single(pdev, ep->tx_ring[i].bufaddr, skb->len,
1309                                 PCI_DMA_TODEVICE);
1310                dev_kfree_skb(skb);
1311        }
1312
1313        /* Green! Leave the chip in low-power mode. */
1314        ew32(GENCTL, 0x0008);
1315
1316        return 0;
1317}
1318
1319static struct net_device_stats *epic_get_stats(struct net_device *dev)
1320{
1321        struct epic_private *ep = netdev_priv(dev);
1322        void __iomem *ioaddr = ep->ioaddr;
1323
1324        if (netif_running(dev)) {
1325                struct net_device_stats *stats = &dev->stats;
1326
1327                stats->rx_missed_errors += er8(MPCNT);
1328                stats->rx_frame_errors  += er8(ALICNT);
1329                stats->rx_crc_errors    += er8(CRCCNT);
1330        }
1331
1332        return &dev->stats;
1333}
1334
1335/* Set or clear the multicast filter for this adaptor.
1336   Note that we only use exclusion around actually queueing the
1337   new frame, not around filling ep->setup_frame.  This is non-deterministic
1338   when re-entered but still correct. */
1339
1340static void set_rx_mode(struct net_device *dev)
1341{
1342        struct epic_private *ep = netdev_priv(dev);
1343        void __iomem *ioaddr = ep->ioaddr;
1344        unsigned char mc_filter[8];              /* Multicast hash filter */
1345        int i;
1346
1347        if (dev->flags & IFF_PROMISC) {                 /* Set promiscuous. */
1348                ew32(RxCtrl, 0x002c);
1349                /* Unconditionally log net taps. */
1350                memset(mc_filter, 0xff, sizeof(mc_filter));
1351        } else if ((!netdev_mc_empty(dev)) || (dev->flags & IFF_ALLMULTI)) {
1352                /* There is apparently a chip bug, so the multicast filter
1353                   is never enabled. */
1354                /* Too many to filter perfectly -- accept all multicasts. */
1355                memset(mc_filter, 0xff, sizeof(mc_filter));
1356                ew32(RxCtrl, 0x000c);
1357        } else if (netdev_mc_empty(dev)) {
1358                ew32(RxCtrl, 0x0004);
1359                return;
1360        } else {                                        /* Never executed, for now. */
1361                struct netdev_hw_addr *ha;
1362
1363                memset(mc_filter, 0, sizeof(mc_filter));
1364                netdev_for_each_mc_addr(ha, dev) {
1365                        unsigned int bit_nr =
1366                                ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;
1367                        mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1368                }
1369        }
1370        /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1371        if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1372                for (i = 0; i < 4; i++)
1373                        ew16(MC0 + i*4, ((u16 *)mc_filter)[i]);
1374                memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1375        }
1376}
1377
1378static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1379{
1380        struct epic_private *np = netdev_priv(dev);
1381
1382        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1383        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1384        strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1385}
1386
1387static int netdev_get_link_ksettings(struct net_device *dev,
1388                                     struct ethtool_link_ksettings *cmd)
1389{
1390        struct epic_private *np = netdev_priv(dev);
1391
1392        spin_lock_irq(&np->lock);
1393        mii_ethtool_get_link_ksettings(&np->mii, cmd);
1394        spin_unlock_irq(&np->lock);
1395
1396        return 0;
1397}
1398
1399static int netdev_set_link_ksettings(struct net_device *dev,
1400                                     const struct ethtool_link_ksettings *cmd)
1401{
1402        struct epic_private *np = netdev_priv(dev);
1403        int rc;
1404
1405        spin_lock_irq(&np->lock);
1406        rc = mii_ethtool_set_link_ksettings(&np->mii, cmd);
1407        spin_unlock_irq(&np->lock);
1408
1409        return rc;
1410}
1411
1412static int netdev_nway_reset(struct net_device *dev)
1413{
1414        struct epic_private *np = netdev_priv(dev);
1415        return mii_nway_restart(&np->mii);
1416}
1417
1418static u32 netdev_get_link(struct net_device *dev)
1419{
1420        struct epic_private *np = netdev_priv(dev);
1421        return mii_link_ok(&np->mii);
1422}
1423
1424static u32 netdev_get_msglevel(struct net_device *dev)
1425{
1426        return debug;
1427}
1428
1429static void netdev_set_msglevel(struct net_device *dev, u32 value)
1430{
1431        debug = value;
1432}
1433
1434static int ethtool_begin(struct net_device *dev)
1435{
1436        struct epic_private *ep = netdev_priv(dev);
1437        void __iomem *ioaddr = ep->ioaddr;
1438
1439        if (ep->ethtool_ops_nesting == U32_MAX)
1440                return -EBUSY;
1441        /* power-up, if interface is down */
1442        if (!ep->ethtool_ops_nesting++ && !netif_running(dev)) {
1443                ew32(GENCTL, 0x0200);
1444                ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);
1445        }
1446        return 0;
1447}
1448
1449static void ethtool_complete(struct net_device *dev)
1450{
1451        struct epic_private *ep = netdev_priv(dev);
1452        void __iomem *ioaddr = ep->ioaddr;
1453
1454        /* power-down, if interface is down */
1455        if (!--ep->ethtool_ops_nesting && !netif_running(dev)) {
1456                ew32(GENCTL, 0x0008);
1457                ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000);
1458        }
1459}
1460
1461static const struct ethtool_ops netdev_ethtool_ops = {
1462        .get_drvinfo            = netdev_get_drvinfo,
1463        .nway_reset             = netdev_nway_reset,
1464        .get_link               = netdev_get_link,
1465        .get_msglevel           = netdev_get_msglevel,
1466        .set_msglevel           = netdev_set_msglevel,
1467        .begin                  = ethtool_begin,
1468        .complete               = ethtool_complete,
1469        .get_link_ksettings     = netdev_get_link_ksettings,
1470        .set_link_ksettings     = netdev_set_link_ksettings,
1471};
1472
1473static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1474{
1475        struct epic_private *np = netdev_priv(dev);
1476        void __iomem *ioaddr = np->ioaddr;
1477        struct mii_ioctl_data *data = if_mii(rq);
1478        int rc;
1479
1480        /* power-up, if interface is down */
1481        if (! netif_running(dev)) {
1482                ew32(GENCTL, 0x0200);
1483                ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);
1484        }
1485
1486        /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1487        spin_lock_irq(&np->lock);
1488        rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1489        spin_unlock_irq(&np->lock);
1490
1491        /* power-down, if interface is down */
1492        if (! netif_running(dev)) {
1493                ew32(GENCTL, 0x0008);
1494                ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000);
1495        }
1496        return rc;
1497}
1498
1499
1500static void epic_remove_one(struct pci_dev *pdev)
1501{
1502        struct net_device *dev = pci_get_drvdata(pdev);
1503        struct epic_private *ep = netdev_priv(dev);
1504
1505        pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1506        pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1507        unregister_netdev(dev);
1508        pci_iounmap(pdev, ep->ioaddr);
1509        pci_release_regions(pdev);
1510        free_netdev(dev);
1511        pci_disable_device(pdev);
1512        /* pci_power_off(pdev, -1); */
1513}
1514
1515
1516#ifdef CONFIG_PM
1517
1518static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1519{
1520        struct net_device *dev = pci_get_drvdata(pdev);
1521        struct epic_private *ep = netdev_priv(dev);
1522        void __iomem *ioaddr = ep->ioaddr;
1523
1524        if (!netif_running(dev))
1525                return 0;
1526        epic_pause(dev);
1527        /* Put the chip into low-power mode. */
1528        ew32(GENCTL, 0x0008);
1529        /* pci_power_off(pdev, -1); */
1530        return 0;
1531}
1532
1533
1534static int epic_resume (struct pci_dev *pdev)
1535{
1536        struct net_device *dev = pci_get_drvdata(pdev);
1537
1538        if (!netif_running(dev))
1539                return 0;
1540        epic_restart(dev);
1541        /* pci_power_on(pdev); */
1542        return 0;
1543}
1544
1545#endif /* CONFIG_PM */
1546
1547
1548static struct pci_driver epic_driver = {
1549        .name           = DRV_NAME,
1550        .id_table       = epic_pci_tbl,
1551        .probe          = epic_init_one,
1552        .remove         = epic_remove_one,
1553#ifdef CONFIG_PM
1554        .suspend        = epic_suspend,
1555        .resume         = epic_resume,
1556#endif /* CONFIG_PM */
1557};
1558
1559
1560static int __init epic_init (void)
1561{
1562/* when a module, this is printed whether or not devices are found in probe */
1563#ifdef MODULE
1564        pr_info("%s%s\n", version, version2);
1565#endif
1566
1567        return pci_register_driver(&epic_driver);
1568}
1569
1570
1571static void __exit epic_cleanup (void)
1572{
1573        pci_unregister_driver (&epic_driver);
1574}
1575
1576
1577module_init(epic_init);
1578module_exit(epic_cleanup);
1579