1
2#ifndef _LMC_VAR_H_
3#define _LMC_VAR_H_
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15
16#include <linux/timer.h>
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21
22typedef struct lmc___softc lmc_softc_t;
23typedef struct lmc___media lmc_media_t;
24typedef struct lmc___ctl lmc_ctl_t;
25
26#define lmc_csrptr_t unsigned long
27
28#define LMC_REG_RANGE 0x80
29
30#define LMC_PRINTF_FMT "%s"
31#define LMC_PRINTF_ARGS (sc->lmc_device->name)
32
33#define TX_TIMEOUT (2*HZ)
34
35#define LMC_TXDESCS 32
36#define LMC_RXDESCS 32
37
38#define LMC_LINK_UP 1
39#define LMC_LINK_DOWN 0
40
41
42#define LMC_CSR_READ(sc, csr) \
43 inl((sc)->lmc_csrs.csr)
44#define LMC_CSR_WRITE(sc, reg, val) \
45 outl((val), (sc)->lmc_csrs.reg)
46
47
48
49
50
51
52
53#define DELAY(n) SLOW_DOWN_IO
54
55#define lmc_delay() inl(sc->lmc_csrs.csr_9)
56
57
58#define LMC_MII_SYNC(sc) do {int n=32; while( n >= 0 ) { \
59 LMC_CSR_WRITE((sc), csr_9, 0x20000); \
60 lmc_delay(); \
61 LMC_CSR_WRITE((sc), csr_9, 0x30000); \
62 lmc_delay(); \
63 n--; }} while(0)
64
65struct lmc_regfile_t {
66 lmc_csrptr_t csr_busmode;
67 lmc_csrptr_t csr_txpoll;
68 lmc_csrptr_t csr_rxpoll;
69 lmc_csrptr_t csr_rxlist;
70 lmc_csrptr_t csr_txlist;
71 lmc_csrptr_t csr_status;
72 lmc_csrptr_t csr_command;
73 lmc_csrptr_t csr_intr;
74 lmc_csrptr_t csr_missed_frames;
75 lmc_csrptr_t csr_9;
76 lmc_csrptr_t csr_10;
77 lmc_csrptr_t csr_11;
78 lmc_csrptr_t csr_12;
79 lmc_csrptr_t csr_13;
80 lmc_csrptr_t csr_14;
81 lmc_csrptr_t csr_15;
82};
83
84#define csr_enetrom csr_9
85#define csr_reserved csr_10
86#define csr_full_duplex csr_11
87#define csr_bootrom csr_10
88#define csr_gp csr_12
89#define csr_watchdog csr_15
90#define csr_gp_timer csr_11
91#define csr_srom_mii csr_9
92#define csr_sia_status csr_12
93#define csr_sia_connectivity csr_13
94#define csr_sia_tx_rx csr_14
95#define csr_sia_general csr_15
96
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100
101#define LMC_TDES_FIRST_BUFFER_SIZE ((u32)(0x000007FF))
102#define LMC_TDES_SECOND_BUFFER_SIZE ((u32)(0x003FF800))
103#define LMC_TDES_HASH_FILTERING ((u32)(0x00400000))
104#define LMC_TDES_DISABLE_PADDING ((u32)(0x00800000))
105#define LMC_TDES_SECOND_ADDR_CHAINED ((u32)(0x01000000))
106#define LMC_TDES_END_OF_RING ((u32)(0x02000000))
107#define LMC_TDES_ADD_CRC_DISABLE ((u32)(0x04000000))
108#define LMC_TDES_SETUP_PACKET ((u32)(0x08000000))
109#define LMC_TDES_INVERSE_FILTERING ((u32)(0x10000000))
110#define LMC_TDES_FIRST_SEGMENT ((u32)(0x20000000))
111#define LMC_TDES_LAST_SEGMENT ((u32)(0x40000000))
112#define LMC_TDES_INTERRUPT_ON_COMPLETION ((u32)(0x80000000))
113
114#define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER 11
115#define TDES_COLLISION_COUNT_BIT_NUMBER 3
116
117
118
119#define LMC_RDES_OVERFLOW ((u32)(0x00000001))
120#define LMC_RDES_CRC_ERROR ((u32)(0x00000002))
121#define LMC_RDES_DRIBBLING_BIT ((u32)(0x00000004))
122#define LMC_RDES_REPORT_ON_MII_ERR ((u32)(0x00000008))
123#define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u32)(0x00000010))
124#define LMC_RDES_FRAME_TYPE ((u32)(0x00000020))
125#define LMC_RDES_COLLISION_SEEN ((u32)(0x00000040))
126#define LMC_RDES_FRAME_TOO_LONG ((u32)(0x00000080))
127#define LMC_RDES_LAST_DESCRIPTOR ((u32)(0x00000100))
128#define LMC_RDES_FIRST_DESCRIPTOR ((u32)(0x00000200))
129#define LMC_RDES_MULTICAST_FRAME ((u32)(0x00000400))
130#define LMC_RDES_RUNT_FRAME ((u32)(0x00000800))
131#define LMC_RDES_DATA_TYPE ((u32)(0x00003000))
132#define LMC_RDES_LENGTH_ERROR ((u32)(0x00004000))
133#define LMC_RDES_ERROR_SUMMARY ((u32)(0x00008000))
134#define LMC_RDES_FRAME_LENGTH ((u32)(0x3FFF0000))
135#define LMC_RDES_OWN_BIT ((u32)(0x80000000))
136
137#define RDES_FRAME_LENGTH_BIT_NUMBER 16
138
139#define LMC_RDES_ERROR_MASK ( (u32)( \
140 LMC_RDES_OVERFLOW \
141 | LMC_RDES_DRIBBLING_BIT \
142 | LMC_RDES_REPORT_ON_MII_ERR \
143 | LMC_RDES_COLLISION_SEEN ) )
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149
150typedef struct {
151 u32 n;
152 u32 m;
153 u32 v;
154 u32 x;
155 u32 r;
156 u32 f;
157 u32 exact;
158} lmc_av9110_t;
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162
163struct lmc___ctl {
164 u32 cardtype;
165 u32 clock_source;
166 u32 clock_rate;
167 u32 crc_length;
168 u32 cable_length;
169 u32 scrambler_onoff;
170 u32 cable_type;
171 u32 keepalive_onoff;
172 u32 ticks;
173 union {
174 lmc_av9110_t ssi;
175 } cardspec;
176 u32 circuit_type;
177};
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193
194struct tulip_desc_t {
195 s32 status;
196 s32 length;
197 u32 buffer1;
198 u32 buffer2;
199};
200
201
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203
204
205struct lmc___media {
206 void (* init)(lmc_softc_t * const);
207 void (* defaults)(lmc_softc_t * const);
208 void (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
209 void (* set_clock_source)(lmc_softc_t * const, int);
210 void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
211 void (* set_cable_length)(lmc_softc_t * const, int);
212 void (* set_scrambler)(lmc_softc_t * const, int);
213 int (* get_link_status)(lmc_softc_t * const);
214 void (* set_link_status)(lmc_softc_t * const, int);
215 void (* set_crc_length)(lmc_softc_t * const, int);
216 void (* set_circuit_type)(lmc_softc_t * const, int);
217 void (* watchdog)(lmc_softc_t * const);
218};
219
220
221#define STATCHECK 0xBEEFCAFE
222
223struct lmc_extra_statistics
224{
225 u32 version_size;
226 u32 lmc_cardtype;
227
228 u32 tx_ProcTimeout;
229 u32 tx_IntTimeout;
230 u32 tx_NoCompleteCnt;
231 u32 tx_MaxXmtsB4Int;
232 u32 tx_TimeoutCnt;
233 u32 tx_OutOfSyncPtr;
234 u32 tx_tbusy0;
235 u32 tx_tbusy1;
236 u32 tx_tbusy_calls;
237 u32 resetCount;
238 u32 lmc_txfull;
239 u32 tbusy;
240 u32 dirtyTx;
241 u32 lmc_next_tx;
242 u32 otherTypeCnt;
243 u32 lastType;
244 u32 lastTypeOK;
245 u32 txLoopCnt;
246 u32 usedXmtDescripCnt;
247 u32 txIndexCnt;
248 u32 rxIntLoopCnt;
249
250 u32 rx_SmallPktCnt;
251 u32 rx_BadPktSurgeCnt;
252 u32 rx_BuffAllocErr;
253 u32 tx_lossOfClockCnt;
254
255
256 u32 framingBitErrorCount;
257 u32 lineCodeViolationCount;
258
259 u32 lossOfFrameCount;
260 u32 changeOfFrameAlignmentCount;
261 u32 severelyErroredFrameCount;
262
263 u32 check;
264};
265
266typedef struct lmc_xinfo {
267 u32 Magic0;
268
269 u32 PciCardType;
270 u32 PciSlotNumber;
271
272 u16 DriverMajorVersion;
273 u16 DriverMinorVersion;
274 u16 DriverSubVersion;
275
276 u16 XilinxRevisionNumber;
277 u16 MaxFrameSize;
278
279 u16 t1_alarm1_status;
280 u16 t1_alarm2_status;
281
282 int link_status;
283 u32 mii_reg16;
284
285 u32 Magic1;
286} LMC_XINFO;
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291
292struct lmc___softc {
293 char *name;
294 u8 board_idx;
295 struct lmc_extra_statistics extra_stats;
296 struct net_device *lmc_device;
297
298 int hang, rxdesc, bad_packet, some_counter;
299 u32 txgo;
300 struct lmc_regfile_t lmc_csrs;
301 volatile u32 lmc_txtick;
302 volatile u32 lmc_rxtick;
303 u32 lmc_flags;
304 u32 lmc_intrmask;
305 u32 lmc_cmdmode;
306 u32 lmc_busmode;
307 u32 lmc_gpio_io;
308 u32 lmc_gpio;
309 struct sk_buff* lmc_txq[LMC_TXDESCS];
310 struct sk_buff* lmc_rxq[LMC_RXDESCS];
311 volatile
312 struct tulip_desc_t lmc_rxring[LMC_RXDESCS];
313 volatile
314 struct tulip_desc_t lmc_txring[LMC_TXDESCS];
315 unsigned int lmc_next_rx, lmc_next_tx;
316 volatile
317 unsigned int lmc_taint_tx, lmc_taint_rx;
318 int lmc_tx_start, lmc_txfull;
319 int lmc_txbusy;
320 u16 lmc_miireg16;
321 int lmc_ok;
322 int last_link_status;
323 int lmc_cardtype;
324 u32 last_frameerr;
325 lmc_media_t *lmc_media;
326 struct timer_list timer;
327 lmc_ctl_t ictl;
328 u32 TxDescriptControlInit;
329
330 int tx_TimeoutInd;
331 int tx_TimeoutDisplay;
332 unsigned int lastlmc_taint_tx;
333 int lasttx_packets;
334 u32 tx_clockState;
335 u32 lmc_crcSize;
336 LMC_XINFO lmc_xinfo;
337 char lmc_yel, lmc_blue, lmc_red;
338 char lmc_timing;
339 int got_irq;
340
341 char last_led_err[4];
342
343 u32 last_int;
344 u32 num_int;
345
346 spinlock_t lmc_lock;
347 u16 if_type;
348
349
350 u8 failed_ring;
351 u8 failed_recv_alloc;
352
353
354 u32 check;
355};
356
357#define LMC_PCI_TIME 1
358#define LMC_EXT_TIME 0
359
360#define PKT_BUF_SZ 1542
361
362
363#define TIMER_INT 0x00000800
364#define TP_LINK_FAIL 0x00001000
365#define TP_LINK_PASS 0x00000010
366#define NORMAL_INT 0x00010000
367#define ABNORMAL_INT 0x00008000
368#define RX_JABBER_INT 0x00000200
369#define RX_DIED 0x00000100
370#define RX_NOBUFF 0x00000080
371#define RX_INT 0x00000040
372#define TX_FIFO_UNDER 0x00000020
373#define TX_JABBER 0x00000008
374#define TX_NOBUFF 0x00000004
375#define TX_DIED 0x00000002
376#define TX_INT 0x00000001
377
378
379#define OPERATION_MODE 0x00000200
380#define PROMISC_MODE 0x00000040
381#define RECEIVE_ALL 0x40000000
382#define PASS_BAD_FRAMES 0x00000008
383
384
385#define LMC_DEC_ST 0x00002000
386#define LMC_DEC_SR 0x00000002
387
388
389#define RECV_WATCHDOG_DISABLE 0x00000010
390#define JABBER_DISABLE 0x00000001
391
392
393
394
395
396#define TULIP_CMD_RECEIVEALL 0x40000000L
397#define TULIP_CMD_MUSTBEONE 0x02000000L
398#define TULIP_CMD_TXTHRSHLDCTL 0x00400000L
399#define TULIP_CMD_STOREFWD 0x00200000L
400#define TULIP_CMD_NOHEARTBEAT 0x00080000L
401#define TULIP_CMD_PORTSELECT 0x00040000L
402#define TULIP_CMD_FULLDUPLEX 0x00000200L
403#define TULIP_CMD_OPERMODE 0x00000C00L
404#define TULIP_CMD_PROMISCUOUS 0x00000041L
405#define TULIP_CMD_PASSBADPKT 0x00000008L
406#define TULIP_CMD_THRESHOLDCTL 0x0000C000L
407
408#define TULIP_GP_PINSET 0x00000100L
409#define TULIP_BUSMODE_SWRESET 0x00000001L
410#define TULIP_WATCHDOG_TXDISABLE 0x00000001L
411#define TULIP_WATCHDOG_RXDISABLE 0x00000010L
412
413#define TULIP_STS_NORMALINTR 0x00010000L
414#define TULIP_STS_ABNRMLINTR 0x00008000L
415#define TULIP_STS_ERI 0x00004000L
416#define TULIP_STS_SYSERROR 0x00002000L
417#define TULIP_STS_GTE 0x00000800L
418#define TULIP_STS_ETI 0x00000400L
419#define TULIP_STS_RXWT 0x00000200L
420#define TULIP_STS_RXSTOPPED 0x00000100L
421#define TULIP_STS_RXNOBUF 0x00000080L
422#define TULIP_STS_RXINTR 0x00000040L
423#define TULIP_STS_TXUNDERFLOW 0x00000020L
424#define TULIP_STS_TXJABER 0x00000008L
425#define TULIP_STS_TXNOBUF 0x00000004L
426#define TULIP_STS_TXSTOPPED 0x00000002L
427#define TULIP_STS_TXINTR 0x00000001L
428
429#define TULIP_STS_RXS_STOPPED 0x00000000L
430
431#define TULIP_STS_RXSTOPPED 0x00000100L
432#define TULIP_STS_RXNOBUF 0x00000080L
433
434#define TULIP_CMD_TXRUN 0x00002000L
435#define TULIP_CMD_RXRUN 0x00000002L
436#define TULIP_DSTS_TxDEFERRED 0x00000001
437#define TULIP_DSTS_OWNER 0x80000000
438#define TULIP_DSTS_RxMIIERR 0x00000008
439#define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
440
441#define TULIP_DEFAULT_INTR_MASK (TULIP_STS_NORMALINTR \
442 | TULIP_STS_RXINTR \
443 | TULIP_STS_TXINTR \
444 | TULIP_STS_ABNRMLINTR \
445 | TULIP_STS_SYSERROR \
446 | TULIP_STS_TXSTOPPED \
447 | TULIP_STS_TXUNDERFLOW\
448 | TULIP_STS_RXSTOPPED )
449
450#define DESC_OWNED_BY_SYSTEM ((u32)(0x00000000))
451#define DESC_OWNED_BY_DC21X4 ((u32)(0x80000000))
452
453#ifndef TULIP_CMD_RECEIVEALL
454#define TULIP_CMD_RECEIVEALL 0x40000000L
455#endif
456
457
458#define LMC_ADAP_HSSI 2
459#define LMC_ADAP_DS3 3
460#define LMC_ADAP_SSI 4
461#define LMC_ADAP_T1 5
462
463#define LMC_MTU 1500
464
465#define LMC_CRC_LEN_16 2
466#define LMC_CRC_LEN_32 4
467
468#endif
469