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40#ifndef _PMC8001_REG_H_
41#define _PMC8001_REG_H_
42
43#include <linux/types.h>
44#include <scsi/libsas.h>
45
46
47
48#define OPC_INB_ECHO 1
49#define OPC_INB_PHYSTART 4
50#define OPC_INB_PHYSTOP 5
51#define OPC_INB_SSPINIIOSTART 6
52#define OPC_INB_SSPINITMSTART 7
53#define OPC_INB_SSPINIEXTIOSTART 8
54#define OPC_INB_DEV_HANDLE_ACCEPT 9
55#define OPC_INB_SSPTGTIOSTART 10
56#define OPC_INB_SSPTGTRSPSTART 11
57#define OPC_INB_SSPINIEDCIOSTART 12
58#define OPC_INB_SSPINIEXTEDCIOSTART 13
59#define OPC_INB_SSPTGTEDCIOSTART 14
60#define OPC_INB_SSP_ABORT 15
61#define OPC_INB_DEREG_DEV_HANDLE 16
62#define OPC_INB_GET_DEV_HANDLE 17
63#define OPC_INB_SMP_REQUEST 18
64
65#define OPC_INB_SMP_RESPONSE 19
66#define OPC_INB_SMP_ABORT 20
67#define OPC_INB_REG_DEV 22
68#define OPC_INB_SATA_HOST_OPSTART 23
69#define OPC_INB_SATA_ABORT 24
70#define OPC_INB_LOCAL_PHY_CONTROL 25
71#define OPC_INB_GET_DEV_INFO 26
72#define OPC_INB_FW_FLASH_UPDATE 32
73#define OPC_INB_GPIO 34
74#define OPC_INB_SAS_DIAG_MODE_START_END 35
75#define OPC_INB_SAS_DIAG_EXECUTE 36
76#define OPC_INB_SAS_HW_EVENT_ACK 37
77#define OPC_INB_GET_TIME_STAMP 38
78#define OPC_INB_PORT_CONTROL 39
79#define OPC_INB_GET_NVMD_DATA 40
80#define OPC_INB_SET_NVMD_DATA 41
81#define OPC_INB_SET_DEVICE_STATE 42
82#define OPC_INB_GET_DEVICE_STATE 43
83#define OPC_INB_SET_DEV_INFO 44
84#define OPC_INB_SAS_RE_INITIALIZE 45
85
86
87#define OPC_OUB_ECHO 1
88#define OPC_OUB_HW_EVENT 4
89#define OPC_OUB_SSP_COMP 5
90#define OPC_OUB_SMP_COMP 6
91#define OPC_OUB_LOCAL_PHY_CNTRL 7
92#define OPC_OUB_DEV_REGIST 10
93#define OPC_OUB_DEREG_DEV 11
94#define OPC_OUB_GET_DEV_HANDLE 12
95#define OPC_OUB_SATA_COMP 13
96#define OPC_OUB_SATA_EVENT 14
97#define OPC_OUB_SSP_EVENT 15
98#define OPC_OUB_DEV_HANDLE_ARRIV 16
99
100#define OPC_OUB_SMP_RECV_EVENT 17
101#define OPC_OUB_SSP_RECV_EVENT 18
102#define OPC_OUB_DEV_INFO 19
103#define OPC_OUB_FW_FLASH_UPDATE 20
104#define OPC_OUB_GPIO_RESPONSE 22
105#define OPC_OUB_GPIO_EVENT 23
106#define OPC_OUB_GENERAL_EVENT 24
107#define OPC_OUB_SSP_ABORT_RSP 26
108#define OPC_OUB_SATA_ABORT_RSP 27
109#define OPC_OUB_SAS_DIAG_MODE_START_END 28
110#define OPC_OUB_SAS_DIAG_EXECUTE 29
111#define OPC_OUB_GET_TIME_STAMP 30
112#define OPC_OUB_SAS_HW_EVENT_ACK 31
113#define OPC_OUB_PORT_CONTROL 32
114#define OPC_OUB_SKIP_ENTRY 33
115#define OPC_OUB_SMP_ABORT_RSP 34
116#define OPC_OUB_GET_NVMD_DATA 35
117#define OPC_OUB_SET_NVMD_DATA 36
118#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37
119#define OPC_OUB_SET_DEVICE_STATE 38
120#define OPC_OUB_GET_DEVICE_STATE 39
121#define OPC_OUB_SET_DEV_INFO 40
122#define OPC_OUB_SAS_RE_INITIALIZE 41
123
124
125#define SPINHOLD_DISABLE (0x00 << 14)
126#define SPINHOLD_ENABLE (0x01 << 14)
127#define LINKMODE_SAS (0x01 << 12)
128#define LINKMODE_DSATA (0x02 << 12)
129#define LINKMODE_AUTO (0x03 << 12)
130#define LINKRATE_15 (0x01 << 8)
131#define LINKRATE_30 (0x02 << 8)
132#define LINKRATE_60 (0x04 << 8)
133
134
135#define GSM_SM_BASE 0x4F0000
136struct mpi_msg_hdr{
137 __le32 header;
138
139
140
141
142
143
144
145
146} __attribute__((packed, aligned(4)));
147
148
149
150
151
152
153struct phy_start_req {
154 __le32 tag;
155 __le32 ase_sh_lm_slr_phyid;
156 struct sas_identify_frame sas_identify;
157 u32 reserved[5];
158} __attribute__((packed, aligned(4)));
159
160
161
162
163
164
165struct phy_stop_req {
166 __le32 tag;
167 __le32 phy_id;
168 u32 reserved[13];
169} __attribute__((packed, aligned(4)));
170
171
172
173struct set_dev_bits_fis {
174 u8 fis_type;
175 u8 n_i_pmport;
176
177
178
179
180 u8 status;
181 u8 error;
182 u32 _r_a;
183} __attribute__ ((packed));
184
185struct pio_setup_fis {
186 u8 fis_type;
187 u8 i_d_pmPort;
188
189
190
191
192
193
194 u8 status;
195 u8 error;
196 u8 lbal;
197 u8 lbam;
198 u8 lbah;
199 u8 device;
200 u8 lbal_exp;
201 u8 lbam_exp;
202 u8 lbah_exp;
203 u8 _r_a;
204 u8 sector_count;
205 u8 sector_count_exp;
206 u8 _r_b;
207 u8 e_status;
208 u8 _r_c[2];
209 u8 transfer_count;
210} __attribute__ ((packed));
211
212
213
214
215
216struct sata_completion_resp {
217 __le32 tag;
218 __le32 status;
219 __le32 param;
220 u32 sata_resp[12];
221} __attribute__((packed, aligned(4)));
222
223
224
225
226
227
228struct hw_event_resp {
229 __le32 lr_evt_status_phyid_portid;
230 __le32 evt_param;
231 __le32 npip_portstate;
232 struct sas_identify_frame sas_identify;
233 struct dev_to_host_fis sata_fis;
234} __attribute__((packed, aligned(4)));
235
236
237
238
239
240
241
242struct reg_dev_req {
243 __le32 tag;
244 __le32 phyid_portid;
245 __le32 dtype_dlr_retry;
246 __le32 firstburstsize_ITNexustimeout;
247 u8 sas_addr[SAS_ADDR_SIZE];
248 __le32 upper_device_id;
249 u32 reserved[8];
250} __attribute__((packed, aligned(4)));
251
252
253
254
255
256
257
258
259struct dereg_dev_req {
260 __le32 tag;
261 __le32 device_id;
262 u32 reserved[13];
263} __attribute__((packed, aligned(4)));
264
265
266
267
268
269
270
271struct dev_reg_resp {
272 __le32 tag;
273 __le32 status;
274 __le32 device_id;
275 u32 reserved[12];
276} __attribute__((packed, aligned(4)));
277
278
279
280
281
282
283struct local_phy_ctl_req {
284 __le32 tag;
285 __le32 phyop_phyid;
286 u32 reserved1[13];
287} __attribute__((packed, aligned(4)));
288
289
290
291
292
293
294struct local_phy_ctl_resp {
295 __le32 tag;
296 __le32 phyop_phyid;
297 __le32 status;
298 u32 reserved[12];
299} __attribute__((packed, aligned(4)));
300
301
302#define OP_BITS 0x0000FF00
303#define ID_BITS 0x000000FF
304
305
306
307
308
309
310struct port_ctl_req {
311 __le32 tag;
312 __le32 portop_portid;
313 __le32 param0;
314 __le32 param1;
315 u32 reserved1[11];
316} __attribute__((packed, aligned(4)));
317
318
319
320
321
322
323
324struct hw_event_ack_req {
325 __le32 tag;
326 __le32 sea_phyid_portid;
327 __le32 param0;
328 __le32 param1;
329 u32 reserved1[11];
330} __attribute__((packed, aligned(4)));
331
332
333
334
335
336
337struct ssp_completion_resp {
338 __le32 tag;
339 __le32 status;
340 __le32 param;
341 __le32 ssptag_rescv_rescpad;
342 struct ssp_response_iu ssp_resp_iu;
343 __le32 residual_count;
344} __attribute__((packed, aligned(4)));
345
346
347#define SSP_RESCV_BIT 0x00010000
348
349
350
351
352
353
354struct sata_event_resp {
355 __le32 tag;
356 __le32 event;
357 __le32 port_id;
358 __le32 device_id;
359 u32 reserved[11];
360} __attribute__((packed, aligned(4)));
361
362
363
364
365
366
367struct ssp_event_resp {
368 __le32 tag;
369 __le32 event;
370 __le32 port_id;
371 __le32 device_id;
372 u32 reserved[11];
373} __attribute__((packed, aligned(4)));
374
375
376
377
378
379struct general_event_resp {
380 __le32 status;
381 __le32 inb_IOMB_payload[14];
382} __attribute__((packed, aligned(4)));
383
384
385#define GENERAL_EVENT_PAYLOAD 14
386#define OPCODE_BITS 0x00000fff
387
388
389
390
391
392struct smp_req {
393 __le32 tag;
394 __le32 device_id;
395 __le32 len_ip_ir;
396
397
398
399
400
401 u8 smp_req16[16];
402 union {
403 u8 smp_req[32];
404 struct {
405 __le64 long_req_addr;
406 __le32 long_req_size;
407 u32 _r_a;
408 __le64 long_resp_addr;
409 __le32 long_resp_size;
410 u32 _r_b;
411 } long_smp_req;
412 };
413} __attribute__((packed, aligned(4)));
414
415
416
417
418struct smp_completion_resp {
419 __le32 tag;
420 __le32 status;
421 __le32 param;
422 __le32 _r_a[12];
423} __attribute__((packed, aligned(4)));
424
425
426
427
428
429struct task_abort_req {
430 __le32 tag;
431 __le32 device_id;
432 __le32 tag_to_abort;
433 __le32 abort_all;
434 u32 reserved[11];
435} __attribute__((packed, aligned(4)));
436
437
438#define ABORT_MASK 0x3
439#define ABORT_SINGLE 0x0
440#define ABORT_ALL 0x1
441
442
443
444
445
446struct task_abort_resp {
447 __le32 tag;
448 __le32 status;
449 __le32 scp;
450 u32 reserved[12];
451} __attribute__((packed, aligned(4)));
452
453
454
455
456
457
458struct sas_diag_start_end_req {
459 __le32 tag;
460 __le32 operation_phyid;
461 u32 reserved[13];
462} __attribute__((packed, aligned(4)));
463
464
465
466
467
468
469struct sas_diag_execute_req{
470 __le32 tag;
471 __le32 cmdtype_cmddesc_phyid;
472 __le32 pat1_pat2;
473 __le32 threshold;
474 __le32 codepat_errmsk;
475 __le32 pmon;
476 __le32 pERF1CTL;
477 u32 reserved[8];
478} __attribute__((packed, aligned(4)));
479
480
481#define SAS_DIAG_PARAM_BYTES 24
482
483
484
485
486
487struct set_dev_state_req {
488 __le32 tag;
489 __le32 device_id;
490 __le32 nds;
491 u32 reserved[12];
492} __attribute__((packed, aligned(4)));
493
494
495
496
497struct sas_re_initialization_req {
498
499 __le32 tag;
500 __le32 SSAHOLT;
501
502
503
504
505
506 __le32 reserved_maxPorts;
507 __le32 open_reject_cmdretries_data_retries;
508
509
510 __le32 sata_hol_tmo;
511 u32 reserved1[10];
512} __attribute__((packed, aligned(4)));
513
514
515
516
517
518
519struct sata_start_req {
520 __le32 tag;
521 __le32 device_id;
522 __le32 data_len;
523 __le32 ncqtag_atap_dir_m;
524 struct host_to_dev_fis sata_fis;
525 u32 reserved1;
526 u32 reserved2;
527 u32 addr_low;
528 u32 addr_high;
529 __le32 len;
530 __le32 esgl;
531} __attribute__((packed, aligned(4)));
532
533
534
535
536
537struct ssp_ini_tm_start_req {
538 __le32 tag;
539 __le32 device_id;
540 __le32 relate_tag;
541 __le32 tmf;
542 u8 lun[8];
543 __le32 ds_ads_m;
544 u32 reserved[8];
545} __attribute__((packed, aligned(4)));
546
547
548struct ssp_info_unit {
549 u8 lun[8];
550 u8 reserved1;
551 u8 efb_prio_attr;
552
553
554
555 u8 reserved2;
556 u8 additional_cdb_len;
557
558
559 u8 cdb[16];
560} __attribute__((packed, aligned(4)));
561
562
563
564
565
566
567struct ssp_ini_io_start_req {
568 __le32 tag;
569 __le32 device_id;
570 __le32 data_len;
571 __le32 dir_m_tlr;
572 struct ssp_info_unit ssp_iu;
573 __le32 addr_low;
574 __le32 addr_high;
575 __le32 len;
576 __le32 esgl;
577} __attribute__((packed, aligned(4)));
578
579
580
581
582
583
584struct fw_flash_Update_req {
585 __le32 tag;
586 __le32 cur_image_offset;
587 __le32 cur_image_len;
588 __le32 total_image_len;
589 u32 reserved0[7];
590 __le32 sgl_addr_lo;
591 __le32 sgl_addr_hi;
592 __le32 len;
593 __le32 ext_reserved;
594} __attribute__((packed, aligned(4)));
595
596
597#define FWFLASH_IOMB_RESERVED_LEN 0x07
598
599
600
601
602
603struct fw_flash_Update_resp {
604 __le32 tag;
605 __le32 status;
606 u32 reserved[13];
607} __attribute__((packed, aligned(4)));
608
609
610
611
612
613
614struct get_nvm_data_req {
615 __le32 tag;
616 __le32 len_ir_vpdd;
617 __le32 vpd_offset;
618 u32 reserved[8];
619 __le32 resp_addr_lo;
620 __le32 resp_addr_hi;
621 __le32 resp_len;
622 u32 reserved1;
623} __attribute__((packed, aligned(4)));
624
625
626struct set_nvm_data_req {
627 __le32 tag;
628 __le32 len_ir_vpdd;
629 __le32 vpd_offset;
630 __le32 reserved[8];
631 __le32 resp_addr_lo;
632 __le32 resp_addr_hi;
633 __le32 resp_len;
634 u32 reserved1;
635} __attribute__((packed, aligned(4)));
636
637
638#define TWI_DEVICE 0x0
639#define C_SEEPROM 0x1
640#define VPD_FLASH 0x4
641#define AAP1_RDUMP 0x5
642#define IOP_RDUMP 0x6
643#define EXPAN_ROM 0x7
644
645#define IPMode 0x80000000
646#define NVMD_TYPE 0x0000000F
647#define NVMD_STAT 0x0000FFFF
648#define NVMD_LEN 0xFF000000
649
650
651
652
653struct get_nvm_data_resp {
654 __le32 tag;
655 __le32 ir_tda_bn_dps_das_nvm;
656 __le32 dlen_status;
657 __le32 nvm_data[12];
658} __attribute__((packed, aligned(4)));
659
660
661
662
663
664
665
666struct sas_diag_start_end_resp {
667 __le32 tag;
668 __le32 status;
669 u32 reserved[13];
670} __attribute__((packed, aligned(4)));
671
672
673
674
675
676
677
678struct sas_diag_execute_resp {
679 __le32 tag;
680 __le32 cmdtype_cmddesc_phyid;
681 __le32 Status;
682 __le32 ReportData;
683 u32 reserved[11];
684} __attribute__((packed, aligned(4)));
685
686
687
688
689
690
691
692struct set_dev_state_resp {
693 __le32 tag;
694 __le32 status;
695 __le32 device_id;
696 __le32 pds_nds;
697 u32 reserved[11];
698} __attribute__((packed, aligned(4)));
699
700
701#define NDS_BITS 0x0F
702#define PDS_BITS 0xF0
703
704
705
706
707
708#define HW_EVENT_RESET_START 0x01
709#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
710#define HW_EVENT_PHY_STOP_STATUS 0x03
711#define HW_EVENT_SAS_PHY_UP 0x04
712#define HW_EVENT_SATA_PHY_UP 0x05
713#define HW_EVENT_SATA_SPINUP_HOLD 0x06
714#define HW_EVENT_PHY_DOWN 0x07
715#define HW_EVENT_PORT_INVALID 0x08
716#define HW_EVENT_BROADCAST_CHANGE 0x09
717#define HW_EVENT_PHY_ERROR 0x0A
718#define HW_EVENT_BROADCAST_SES 0x0B
719#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
720#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
721#define HW_EVENT_MALFUNCTION 0x0E
722#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
723#define HW_EVENT_BROADCAST_EXP 0x10
724#define HW_EVENT_PHY_START_STATUS 0x11
725#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
726#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
727#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
728#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
729#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
730#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
731#define HW_EVENT_PORT_RECOVER 0x18
732#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
733#define HW_EVENT_PORT_RESET_COMPLETE 0x20
734#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
735
736
737#define PORT_NOT_ESTABLISHED 0x00
738#define PORT_VALID 0x01
739#define PORT_LOSTCOMM 0x02
740#define PORT_IN_RESET 0x04
741#define PORT_INVALID 0x08
742
743
744
745
746
747#define IO_SUCCESS 0x00
748#define IO_ABORTED 0x01
749#define IO_OVERFLOW 0x02
750#define IO_UNDERFLOW 0x03
751#define IO_FAILED 0x04
752#define IO_ABORT_RESET 0x05
753#define IO_NOT_VALID 0x06
754#define IO_NO_DEVICE 0x07
755#define IO_ILLEGAL_PARAMETER 0x08
756#define IO_LINK_FAILURE 0x09
757#define IO_PROG_ERROR 0x0A
758#define IO_EDC_IN_ERROR 0x0B
759#define IO_EDC_OUT_ERROR 0x0C
760#define IO_ERROR_HW_TIMEOUT 0x0D
761#define IO_XFER_ERROR_BREAK 0x0E
762#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
763#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
764#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
765#define IO_OPEN_CNX_ERROR_BREAK 0x12
766#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
767#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
768#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
769#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
770#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
771#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
772#define IO_XFER_ERROR_NAK_RECEIVED 0x19
773#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
774#define IO_XFER_ERROR_PEER_ABORTED 0x1B
775#define IO_XFER_ERROR_RX_FRAME 0x1C
776#define IO_XFER_ERROR_DMA 0x1D
777#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
778#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
779#define IO_XFER_ERROR_SATA 0x20
780#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
781#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
782#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
783#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
784#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
785#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
786#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
787#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
788
789#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
790#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
791#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
792
793#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
794#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
795#define IO_XFER_CMD_FRAME_ISSUED 0x36
796#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
797#define IO_PORT_IN_RESET 0x38
798#define IO_DS_NON_OPERATIONAL 0x39
799#define IO_DS_IN_RECOVERY 0x3A
800#define IO_TM_TAG_NOT_FOUND 0x3B
801#define IO_XFER_PIO_SETUP_ERROR 0x3C
802#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
803#define IO_DS_IN_ERROR 0x3E
804#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
805#define IO_ABORT_IN_PROGRESS 0x40
806#define IO_ABORT_DELAYED 0x41
807#define IO_INVALID_LENGTH 0x42
808
809
810
811
812
813#define IO_ERROR_UNKNOWN_GENERIC 0x43
814
815
816
817#define SPC_MSGU_CFG_TABLE_UPDATE 0x01
818#define SPC_MSGU_CFG_TABLE_RESET 0x02
819#define SPC_MSGU_CFG_TABLE_FREEZE 0x04
820#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08
821#define MSGU_IBDB_SET 0x04
822#define MSGU_HOST_INT_STATUS 0x08
823#define MSGU_HOST_INT_MASK 0x0C
824#define MSGU_IOPIB_INT_STATUS 0x18
825#define MSGU_IOPIB_INT_MASK 0x1C
826#define MSGU_IBDB_CLEAR 0x20
827#define MSGU_MSGU_CONTROL 0x24
828#define MSGU_ODR 0x3C
829#define MSGU_ODCR 0x40
830#define MSGU_SCRATCH_PAD_0 0x44
831#define MSGU_SCRATCH_PAD_1 0x48
832#define MSGU_SCRATCH_PAD_2 0x4C
833#define MSGU_SCRATCH_PAD_3 0x50
834#define MSGU_HOST_SCRATCH_PAD_0 0x54
835#define MSGU_HOST_SCRATCH_PAD_1 0x58
836#define MSGU_HOST_SCRATCH_PAD_2 0x5C
837#define MSGU_HOST_SCRATCH_PAD_3 0x60
838#define MSGU_HOST_SCRATCH_PAD_4 0x64
839#define MSGU_HOST_SCRATCH_PAD_5 0x68
840#define MSGU_HOST_SCRATCH_PAD_6 0x6C
841#define MSGU_HOST_SCRATCH_PAD_7 0x70
842#define MSGU_ODMR 0x74
843
844
845#define ODMR_MASK_ALL 0xFFFFFFFF
846
847#define ODMR_CLEAR_ALL 0
848
849
850#define ODCR_CLEAR_ALL 0xFFFFFFFF
851
852
853#define MSIX_TABLE_OFFSET 0x2000
854#define MSIX_TABLE_ELEMENT_SIZE 0x10
855#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
856#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
857#define MSIX_INTERRUPT_DISABLE 0x1
858#define MSIX_INTERRUPT_ENABLE 0x0
859
860
861
862#define SCRATCH_PAD1_POR 0x00
863#define SCRATCH_PAD1_SFR 0x01
864#define SCRATCH_PAD1_ERR 0x02
865#define SCRATCH_PAD1_RDY 0x03
866#define SCRATCH_PAD1_RST 0x04
867#define SCRATCH_PAD1_AAP1RDY_RST 0x08
868#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0
869
870#define SCRATCH_PAD1_RESERVED 0x000003F8
871
872
873
874#define SCRATCH_PAD2_POR 0x00
875#define SCRATCH_PAD2_SFR 0x01
876#define SCRATCH_PAD2_ERR 0x02
877#define SCRATCH_PAD2_RDY 0x03
878#define SCRATCH_PAD2_FWRDY_RST 0x04
879#define SCRATCH_PAD2_IOPRDY_RST 0x08
880#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4
881
882#define SCRATCH_PAD2_RESERVED 0x000003FC
883
884
885#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00
886#define SCRATCH_PAD_STATE_MASK 0x00000003
887
888
889#define MAIN_SIGNATURE_OFFSET 0x00
890#define MAIN_INTERFACE_REVISION 0x04
891#define MAIN_FW_REVISION 0x08
892#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C
893#define MAIN_MAX_SGL_OFFSET 0x10
894#define MAIN_CNTRL_CAP_OFFSET 0x14
895#define MAIN_GST_OFFSET 0x18
896#define MAIN_IBQ_OFFSET 0x1C
897#define MAIN_OBQ_OFFSET 0x20
898#define MAIN_IQNPPD_HPPD_OFFSET 0x24
899#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28
900#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C
901#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30
902#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34
903#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38
904#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C
905#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40
906#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44
907#define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48
908#define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C
909#define MAIN_EVENT_LOG_ADDR_HI 0x50
910#define MAIN_EVENT_LOG_ADDR_LO 0x54
911#define MAIN_EVENT_LOG_BUFF_SIZE 0x58
912#define MAIN_EVENT_LOG_OPTION 0x5C
913#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60
914#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64
915#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68
916#define MAIN_IOP_EVENT_LOG_OPTION 0x6C
917#define MAIN_FATAL_ERROR_INTERRUPT 0x70
918#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74
919#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78
920#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C
921#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80
922#define MAIN_HDA_FLAGS_OFFSET 0x84
923#define MAIN_ANALOG_SETUP_OFFSET 0x88
924
925
926#define GST_GSTLEN_MPIS_OFFSET 0x00
927#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
928#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
929#define GST_MSGUTCNT_OFFSET 0x0C
930#define GST_IOPTCNT_OFFSET 0x10
931#define GST_PHYSTATE_OFFSET 0x18
932#define GST_PHYSTATE0_OFFSET 0x18
933#define GST_PHYSTATE1_OFFSET 0x1C
934#define GST_PHYSTATE2_OFFSET 0x20
935#define GST_PHYSTATE3_OFFSET 0x24
936#define GST_PHYSTATE4_OFFSET 0x28
937#define GST_PHYSTATE5_OFFSET 0x2C
938#define GST_PHYSTATE6_OFFSET 0x30
939#define GST_PHYSTATE7_OFFSET 0x34
940#define GST_RERRINFO_OFFSET 0x44
941
942
943#define GST_MPI_STATE_UNINIT 0x00
944#define GST_MPI_STATE_INIT 0x01
945#define GST_MPI_STATE_TERMINATION 0x02
946#define GST_MPI_STATE_ERROR 0x03
947#define GST_MPI_STATE_MASK 0x07
948
949#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
950#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
951
952#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
953#define PCIE_EVENT_INTERRUPT 0x003044
954#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
955#define PCIE_ERROR_INTERRUPT 0x00304C
956
957#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
958
959
960
961#define SPC_REG_RESET 0x000000
962
963
964#define SPC_REG_RESET_OSSP 0x00000001
965#define SPC_REG_RESET_RAAE 0x00000002
966#define SPC_REG_RESET_PCS_SPBC 0x00000004
967#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
968#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
969#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
970#define SPC_REG_RESET_PCS_LM 0x00000040
971#define SPC_REG_RESET_PCS 0x00000080
972#define SPC_REG_RESET_GSM 0x00000100
973#define SPC_REG_RESET_DDR2 0x00010000
974#define SPC_REG_RESET_BDMA_CORE 0x00020000
975#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
976#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
977#define SPC_REG_RESET_PCIE_PWR 0x00100000
978#define SPC_REG_RESET_PCIE_SFT 0x00200000
979#define SPC_REG_RESET_PCS_SXCBI 0x00400000
980#define SPC_REG_RESET_LMS_SXCBI 0x00800000
981#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
982#define SPC_REG_RESET_PMIC_CORE 0x02000000
983#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
984#define SPC_REG_RESET_DEVICE 0x80000000
985
986
987#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
988
989#define MBIC_AAP1_ADDR_BASE 0x060000
990#define MBIC_IOP_ADDR_BASE 0x070000
991#define GSM_ADDR_BASE 0x0700000
992
993#define GSM_CONFIG_RESET 0x00000000
994#define RAM_ECC_DB_ERR 0x00000018
995#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
996#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
997#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
998#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
999#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1000#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1001
1002#define RB6_ACCESS_REG 0x6A0000
1003#define HDAC_EXEC_CMD 0x0002
1004#define HDA_C_PA 0xcb
1005#define HDA_SEQ_ID_BITS 0x00ff0000
1006#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1007#define MBIC_AAP1_ADDR_BASE 0x060000
1008#define MBIC_IOP_ADDR_BASE 0x070000
1009#define GSM_ADDR_BASE 0x0700000
1010#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1011#define GSM_CONFIG_RESET_VALUE 0x00003b00
1012#define GPIO_ADDR_BASE 0x00090000
1013#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1014
1015
1016#define SPC_RB6_OFFSET 0x80C0
1017
1018#define RB6_MAGIC_NUMBER_RST 0x1234
1019
1020
1021#define DEVREG_SUCCESS 0x00
1022#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1023#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1024#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1025#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1026#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1027#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1028#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1029
1030#define GSM_BASE 0x4F0000
1031#define SHIFT_REG_64K_MASK 0xffff0000
1032#define SHIFT_REG_BIT_SHIFT 8
1033#endif
1034
1035