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13#ifndef _TB_REGS
14#define _TB_REGS
15
16#include <linux/types.h>
17
18
19#define TB_ROUTE_SHIFT 8
20
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24
25
26#define TB_MAX_CONFIG_RW_LENGTH 60
27
28enum tb_switch_cap {
29 TB_SWITCH_CAP_TMU = 0x03,
30 TB_SWITCH_CAP_VSE = 0x05,
31};
32
33enum tb_switch_vse_cap {
34 TB_VSE_CAP_PLUG_EVENTS = 0x01,
35 TB_VSE_CAP_TIME2 = 0x03,
36 TB_VSE_CAP_IECS = 0x04,
37 TB_VSE_CAP_LINK_CONTROLLER = 0x06,
38};
39
40enum tb_port_cap {
41 TB_PORT_CAP_PHY = 0x01,
42 TB_PORT_CAP_TIME1 = 0x03,
43 TB_PORT_CAP_ADAP = 0x04,
44 TB_PORT_CAP_VSE = 0x05,
45 TB_PORT_CAP_USB4 = 0x06,
46};
47
48enum tb_port_state {
49 TB_PORT_DISABLED = 0,
50 TB_PORT_CONNECTING = 1,
51 TB_PORT_UP = 2,
52 TB_PORT_UNPLUGGED = 7,
53};
54
55
56
57struct tb_cap_basic {
58 u8 next;
59
60 u8 cap;
61} __packed;
62
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70
71struct tb_cap_extended_short {
72 u8 next;
73 u8 cap;
74 u8 vsec_id;
75 u8 length;
76} __packed;
77
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86
87struct tb_cap_extended_long {
88 u8 zero1;
89 u8 cap;
90 u8 vsec_id;
91 u8 zero2;
92 u16 next;
93 u16 length;
94} __packed;
95
96
97
98struct tb_cap_link_controller {
99 struct tb_cap_extended_long cap_header;
100 u32 count:4;
101 u32 unknown1:4;
102 u32 base_offset:8;
103
104
105
106 u32 length:12;
107 u32 unknown2:4;
108} __packed;
109
110struct tb_cap_phy {
111 struct tb_cap_basic cap_header;
112 u32 unknown1:16;
113 u32 unknown2:14;
114 bool disable:1;
115 u32 unknown3:11;
116 enum tb_port_state state:4;
117 u32 unknown4:2;
118} __packed;
119
120struct tb_eeprom_ctl {
121 bool clock:1;
122 bool access_low:1;
123 bool data_out:1;
124 bool data_in:1;
125 bool access_high:1;
126 bool not_present:1;
127 bool unknown1:1;
128 bool present:1;
129 u32 unknown2:24;
130} __packed;
131
132struct tb_cap_plug_events {
133 struct tb_cap_extended_short cap_header;
134 u32 __unknown1:2;
135 u32 plug_events:5;
136 u32 __unknown2:25;
137 u32 __unknown3;
138 u32 __unknown4;
139 struct tb_eeprom_ctl eeprom_ctl;
140 u32 __unknown5[7];
141 u32 drom_offset;
142} __packed;
143
144
145
146
147struct tb_regs_switch_header {
148
149 u16 vendor_id;
150 u16 device_id;
151
152 u32 first_cap_offset:8;
153 u32 upstream_port_number:6;
154 u32 max_port_number:6;
155 u32 depth:3;
156 u32 __unknown1:1;
157 u32 revision:8;
158
159 u32 route_lo;
160
161 u32 route_hi:31;
162 bool enabled:1;
163
164 u32 plug_events_delay:8;
165
166
167
168
169 u32 cmuv:8;
170 u32 __unknown4:8;
171 u32 thunderbolt_version:8;
172} __packed;
173
174
175#define USB4_VERSION_1_0 0x20
176
177#define ROUTER_CS_1 0x01
178#define ROUTER_CS_4 0x04
179#define ROUTER_CS_5 0x05
180#define ROUTER_CS_5_SLP BIT(0)
181#define ROUTER_CS_5_C3S BIT(23)
182#define ROUTER_CS_5_PTO BIT(24)
183#define ROUTER_CS_5_UTO BIT(25)
184#define ROUTER_CS_5_HCO BIT(26)
185#define ROUTER_CS_5_CV BIT(31)
186#define ROUTER_CS_6 0x06
187#define ROUTER_CS_6_SLPR BIT(0)
188#define ROUTER_CS_6_TNS BIT(1)
189#define ROUTER_CS_6_HCI BIT(18)
190#define ROUTER_CS_6_CR BIT(25)
191#define ROUTER_CS_7 0x07
192#define ROUTER_CS_9 0x09
193#define ROUTER_CS_25 0x19
194#define ROUTER_CS_26 0x1a
195#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24)
196#define ROUTER_CS_26_STATUS_SHIFT 24
197#define ROUTER_CS_26_ONS BIT(30)
198#define ROUTER_CS_26_OV BIT(31)
199
200
201#define TMU_RTR_CS_0 0x00
202#define TMU_RTR_CS_0_TD BIT(27)
203#define TMU_RTR_CS_0_UCAP BIT(30)
204#define TMU_RTR_CS_1 0x01
205#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16)
206#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16
207#define TMU_RTR_CS_2 0x02
208#define TMU_RTR_CS_3 0x03
209#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
210#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16)
211#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16
212#define TMU_RTR_CS_22 0x16
213#define TMU_RTR_CS_24 0x18
214
215enum tb_port_type {
216 TB_TYPE_INACTIVE = 0x000000,
217 TB_TYPE_PORT = 0x000001,
218 TB_TYPE_NHI = 0x000002,
219
220
221 TB_TYPE_DP_HDMI_IN = 0x0e0101,
222 TB_TYPE_DP_HDMI_OUT = 0x0e0102,
223 TB_TYPE_PCIE_DOWN = 0x100101,
224 TB_TYPE_PCIE_UP = 0x100102,
225 TB_TYPE_USB3_DOWN = 0x200101,
226 TB_TYPE_USB3_UP = 0x200102,
227};
228
229
230struct tb_regs_port_header {
231
232 u16 vendor_id;
233 u16 device_id;
234
235 u32 first_cap_offset:8;
236 u32 max_counters:11;
237 u32 __unknown1:5;
238 u32 revision:8;
239
240 enum tb_port_type type:24;
241 u32 thunderbolt_version:8;
242
243 u32 __unknown2:20;
244 u32 port_number:6;
245 u32 __unknown3:6;
246
247 u32 nfc_credits;
248
249 u32 max_in_hop_id:11;
250 u32 max_out_hop_id:11;
251 u32 __unknown4:10;
252
253 u32 __unknown5;
254
255 u32 __unknown6;
256
257} __packed;
258
259
260#define ADP_CS_4 0x04
261#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
262#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)
263#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20
264#define ADP_CS_4_LCK BIT(31)
265#define ADP_CS_5 0x05
266#define ADP_CS_5_LCA_MASK GENMASK(28, 22)
267#define ADP_CS_5_LCA_SHIFT 22
268
269
270#define TMU_ADP_CS_3 0x03
271#define TMU_ADP_CS_3_UDM BIT(29)
272
273
274#define LANE_ADP_CS_0 0x00
275#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20)
276#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20
277#define LANE_ADP_CS_1 0x01
278#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4)
279#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4
280#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
281#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
282#define LANE_ADP_CS_1_LB BIT(15)
283#define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16)
284#define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16
285#define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
286#define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
287#define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20)
288#define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20
289
290
291#define PORT_CS_18 0x12
292#define PORT_CS_18_BE BIT(8)
293#define PORT_CS_19 0x13
294#define PORT_CS_19_PC BIT(3)
295
296
297#define ADP_DP_CS_0 0x00
298#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)
299#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16
300#define ADP_DP_CS_0_AE BIT(30)
301#define ADP_DP_CS_0_VE BIT(31)
302#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
303#define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
304#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
305#define ADP_DP_CS_2 0x02
306#define ADP_DP_CS_2_HDP BIT(6)
307#define ADP_DP_CS_3 0x03
308#define ADP_DP_CS_3_HDPC BIT(9)
309#define DP_LOCAL_CAP 0x04
310#define DP_REMOTE_CAP 0x05
311#define DP_STATUS_CTRL 0x06
312#define DP_STATUS_CTRL_CMHS BIT(25)
313#define DP_STATUS_CTRL_UF BIT(26)
314#define DP_COMMON_CAP 0x07
315
316
317
318
319#define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
320#define DP_COMMON_CAP_RATE_SHIFT 8
321#define DP_COMMON_CAP_RATE_RBR 0x0
322#define DP_COMMON_CAP_RATE_HBR 0x1
323#define DP_COMMON_CAP_RATE_HBR2 0x2
324#define DP_COMMON_CAP_RATE_HBR3 0x3
325#define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12)
326#define DP_COMMON_CAP_LANES_SHIFT 12
327#define DP_COMMON_CAP_1_LANE 0x0
328#define DP_COMMON_CAP_2_LANES 0x1
329#define DP_COMMON_CAP_4_LANES 0x2
330#define DP_COMMON_CAP_DPRX_DONE BIT(31)
331
332
333#define ADP_PCIE_CS_0 0x00
334#define ADP_PCIE_CS_0_PE BIT(31)
335
336
337#define ADP_USB3_CS_0 0x00
338#define ADP_USB3_CS_0_V BIT(30)
339#define ADP_USB3_CS_0_PE BIT(31)
340
341
342struct tb_regs_hop {
343
344 u32 next_hop:11;
345
346
347
348 u32 out_port:6;
349 u32 initial_credits:8;
350 u32 unknown1:6;
351 bool enable:1;
352
353
354 u32 weight:4;
355 u32 unknown2:4;
356 u32 priority:3;
357 bool drop_packages:1;
358 u32 counter:11;
359 bool counter_enable:1;
360 bool ingress_fc:1;
361 bool egress_fc:1;
362 bool ingress_shared_buffer:1;
363 bool egress_shared_buffer:1;
364 bool pending:1;
365 u32 unknown3:3;
366} __packed;
367
368
369#define TB_LC_DESC 0x02
370#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
371#define TB_LC_DESC_SIZE_SHIFT 8
372#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
373#define TB_LC_DESC_PORT_SIZE_SHIFT 16
374#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
375#define TB_LC_FUSE 0x03
376#define TB_LC_SNK_ALLOCATION 0x10
377#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
378#define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
379#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
380#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
381#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
382
383
384#define TB_LC_PORT_ATTR 0x8d
385#define TB_LC_PORT_ATTR_BE BIT(12)
386
387#define TB_LC_SX_CTRL 0x96
388#define TB_LC_SX_CTRL_L1C BIT(16)
389#define TB_LC_SX_CTRL_L2C BIT(20)
390#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
391#define TB_LC_SX_CTRL_SLP BIT(31)
392
393#endif
394