linux/drivers/tty/serial/owl-uart.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Actions Semi Owl family serial console
   4 *
   5 * Copyright 2013 Actions Semi Inc.
   6 * Author: Actions Semi, Inc.
   7 *
   8 * Copyright (c) 2016-2017 Andreas Färber
   9 */
  10
  11#include <linux/clk.h>
  12#include <linux/console.h>
  13#include <linux/delay.h>
  14#include <linux/io.h>
  15#include <linux/module.h>
  16#include <linux/of.h>
  17#include <linux/platform_device.h>
  18#include <linux/serial.h>
  19#include <linux/serial_core.h>
  20#include <linux/tty.h>
  21#include <linux/tty_flip.h>
  22
  23#define OWL_UART_PORT_NUM 7
  24#define OWL_UART_DEV_NAME "ttyOWL"
  25
  26#define OWL_UART_CTL    0x000
  27#define OWL_UART_RXDAT  0x004
  28#define OWL_UART_TXDAT  0x008
  29#define OWL_UART_STAT   0x00c
  30
  31#define OWL_UART_CTL_DWLS_MASK          GENMASK(1, 0)
  32#define OWL_UART_CTL_DWLS_5BITS         (0x0 << 0)
  33#define OWL_UART_CTL_DWLS_6BITS         (0x1 << 0)
  34#define OWL_UART_CTL_DWLS_7BITS         (0x2 << 0)
  35#define OWL_UART_CTL_DWLS_8BITS         (0x3 << 0)
  36#define OWL_UART_CTL_STPS_2BITS         BIT(2)
  37#define OWL_UART_CTL_PRS_MASK           GENMASK(6, 4)
  38#define OWL_UART_CTL_PRS_NONE           (0x0 << 4)
  39#define OWL_UART_CTL_PRS_ODD            (0x4 << 4)
  40#define OWL_UART_CTL_PRS_MARK           (0x5 << 4)
  41#define OWL_UART_CTL_PRS_EVEN           (0x6 << 4)
  42#define OWL_UART_CTL_PRS_SPACE          (0x7 << 4)
  43#define OWL_UART_CTL_AFE                BIT(12)
  44#define OWL_UART_CTL_TRFS_TX            BIT(14)
  45#define OWL_UART_CTL_EN                 BIT(15)
  46#define OWL_UART_CTL_RXDE               BIT(16)
  47#define OWL_UART_CTL_TXDE               BIT(17)
  48#define OWL_UART_CTL_RXIE               BIT(18)
  49#define OWL_UART_CTL_TXIE               BIT(19)
  50#define OWL_UART_CTL_LBEN               BIT(20)
  51
  52#define OWL_UART_STAT_RIP               BIT(0)
  53#define OWL_UART_STAT_TIP               BIT(1)
  54#define OWL_UART_STAT_RXER              BIT(2)
  55#define OWL_UART_STAT_TFER              BIT(3)
  56#define OWL_UART_STAT_RXST              BIT(4)
  57#define OWL_UART_STAT_RFEM              BIT(5)
  58#define OWL_UART_STAT_TFFU              BIT(6)
  59#define OWL_UART_STAT_CTSS              BIT(7)
  60#define OWL_UART_STAT_RTSS              BIT(8)
  61#define OWL_UART_STAT_TFES              BIT(10)
  62#define OWL_UART_STAT_TRFL_MASK         GENMASK(16, 11)
  63#define OWL_UART_STAT_UTBB              BIT(17)
  64
  65static struct uart_driver owl_uart_driver;
  66
  67struct owl_uart_info {
  68        unsigned int tx_fifosize;
  69};
  70
  71struct owl_uart_port {
  72        struct uart_port port;
  73        struct clk *clk;
  74};
  75
  76#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
  77
  78static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
  79
  80static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
  81{
  82        writel(val, port->membase + off);
  83}
  84
  85static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
  86{
  87        return readl(port->membase + off);
  88}
  89
  90static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  91{
  92        u32 ctl;
  93
  94        ctl = owl_uart_read(port, OWL_UART_CTL);
  95
  96        if (mctrl & TIOCM_LOOP)
  97                ctl |= OWL_UART_CTL_LBEN;
  98        else
  99                ctl &= ~OWL_UART_CTL_LBEN;
 100
 101        owl_uart_write(port, ctl, OWL_UART_CTL);
 102}
 103
 104static unsigned int owl_uart_get_mctrl(struct uart_port *port)
 105{
 106        unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
 107        u32 stat, ctl;
 108
 109        ctl = owl_uart_read(port, OWL_UART_CTL);
 110        stat = owl_uart_read(port, OWL_UART_STAT);
 111        if (stat & OWL_UART_STAT_RTSS)
 112                mctrl |= TIOCM_RTS;
 113        if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
 114                mctrl |= TIOCM_CTS;
 115        return mctrl;
 116}
 117
 118static unsigned int owl_uart_tx_empty(struct uart_port *port)
 119{
 120        unsigned long flags;
 121        u32 val;
 122        unsigned int ret;
 123
 124        spin_lock_irqsave(&port->lock, flags);
 125
 126        val = owl_uart_read(port, OWL_UART_STAT);
 127        ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
 128
 129        spin_unlock_irqrestore(&port->lock, flags);
 130
 131        return ret;
 132}
 133
 134static void owl_uart_stop_rx(struct uart_port *port)
 135{
 136        u32 val;
 137
 138        val = owl_uart_read(port, OWL_UART_CTL);
 139        val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
 140        owl_uart_write(port, val, OWL_UART_CTL);
 141
 142        val = owl_uart_read(port, OWL_UART_STAT);
 143        val |= OWL_UART_STAT_RIP;
 144        owl_uart_write(port, val, OWL_UART_STAT);
 145}
 146
 147static void owl_uart_stop_tx(struct uart_port *port)
 148{
 149        u32 val;
 150
 151        val = owl_uart_read(port, OWL_UART_CTL);
 152        val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
 153        owl_uart_write(port, val, OWL_UART_CTL);
 154
 155        val = owl_uart_read(port, OWL_UART_STAT);
 156        val |= OWL_UART_STAT_TIP;
 157        owl_uart_write(port, val, OWL_UART_STAT);
 158}
 159
 160static void owl_uart_start_tx(struct uart_port *port)
 161{
 162        u32 val;
 163
 164        if (uart_tx_stopped(port)) {
 165                owl_uart_stop_tx(port);
 166                return;
 167        }
 168
 169        val = owl_uart_read(port, OWL_UART_STAT);
 170        val |= OWL_UART_STAT_TIP;
 171        owl_uart_write(port, val, OWL_UART_STAT);
 172
 173        val = owl_uart_read(port, OWL_UART_CTL);
 174        val |= OWL_UART_CTL_TXIE;
 175        owl_uart_write(port, val, OWL_UART_CTL);
 176}
 177
 178static void owl_uart_send_chars(struct uart_port *port)
 179{
 180        struct circ_buf *xmit = &port->state->xmit;
 181        unsigned int ch;
 182
 183        if (uart_tx_stopped(port))
 184                return;
 185
 186        if (port->x_char) {
 187                while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
 188                        cpu_relax();
 189                owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
 190                port->icount.tx++;
 191                port->x_char = 0;
 192        }
 193
 194        while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
 195                if (uart_circ_empty(xmit))
 196                        break;
 197
 198                ch = xmit->buf[xmit->tail];
 199                owl_uart_write(port, ch, OWL_UART_TXDAT);
 200                xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
 201                port->icount.tx++;
 202        }
 203
 204        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 205                uart_write_wakeup(port);
 206
 207        if (uart_circ_empty(xmit))
 208                owl_uart_stop_tx(port);
 209}
 210
 211static void owl_uart_receive_chars(struct uart_port *port)
 212{
 213        u32 stat, val;
 214
 215        val = owl_uart_read(port, OWL_UART_CTL);
 216        val &= ~OWL_UART_CTL_TRFS_TX;
 217        owl_uart_write(port, val, OWL_UART_CTL);
 218
 219        stat = owl_uart_read(port, OWL_UART_STAT);
 220        while (!(stat & OWL_UART_STAT_RFEM)) {
 221                char flag = TTY_NORMAL;
 222
 223                if (stat & OWL_UART_STAT_RXER)
 224                        port->icount.overrun++;
 225
 226                if (stat & OWL_UART_STAT_RXST) {
 227                        /* We are not able to distinguish the error type. */
 228                        port->icount.brk++;
 229                        port->icount.frame++;
 230
 231                        stat &= port->read_status_mask;
 232                        if (stat & OWL_UART_STAT_RXST)
 233                                flag = TTY_PARITY;
 234                } else
 235                        port->icount.rx++;
 236
 237                val = owl_uart_read(port, OWL_UART_RXDAT);
 238                val &= 0xff;
 239
 240                if ((stat & port->ignore_status_mask) == 0)
 241                        tty_insert_flip_char(&port->state->port, val, flag);
 242
 243                stat = owl_uart_read(port, OWL_UART_STAT);
 244        }
 245
 246        spin_unlock(&port->lock);
 247        tty_flip_buffer_push(&port->state->port);
 248        spin_lock(&port->lock);
 249}
 250
 251static irqreturn_t owl_uart_irq(int irq, void *dev_id)
 252{
 253        struct uart_port *port = dev_id;
 254        unsigned long flags;
 255        u32 stat;
 256
 257        spin_lock_irqsave(&port->lock, flags);
 258
 259        stat = owl_uart_read(port, OWL_UART_STAT);
 260
 261        if (stat & OWL_UART_STAT_RIP)
 262                owl_uart_receive_chars(port);
 263
 264        if (stat & OWL_UART_STAT_TIP)
 265                owl_uart_send_chars(port);
 266
 267        stat = owl_uart_read(port, OWL_UART_STAT);
 268        stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
 269        owl_uart_write(port, stat, OWL_UART_STAT);
 270
 271        spin_unlock_irqrestore(&port->lock, flags);
 272
 273        return IRQ_HANDLED;
 274}
 275
 276static void owl_uart_shutdown(struct uart_port *port)
 277{
 278        u32 val;
 279        unsigned long flags;
 280
 281        spin_lock_irqsave(&port->lock, flags);
 282
 283        val = owl_uart_read(port, OWL_UART_CTL);
 284        val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
 285                | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
 286        owl_uart_write(port, val, OWL_UART_CTL);
 287
 288        spin_unlock_irqrestore(&port->lock, flags);
 289
 290        free_irq(port->irq, port);
 291}
 292
 293static int owl_uart_startup(struct uart_port *port)
 294{
 295        u32 val;
 296        unsigned long flags;
 297        int ret;
 298
 299        ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
 300                        "owl-uart", port);
 301        if (ret)
 302                return ret;
 303
 304        spin_lock_irqsave(&port->lock, flags);
 305
 306        val = owl_uart_read(port, OWL_UART_STAT);
 307        val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
 308                | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
 309        owl_uart_write(port, val, OWL_UART_STAT);
 310
 311        val = owl_uart_read(port, OWL_UART_CTL);
 312        val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
 313        val |= OWL_UART_CTL_EN;
 314        owl_uart_write(port, val, OWL_UART_CTL);
 315
 316        spin_unlock_irqrestore(&port->lock, flags);
 317
 318        return 0;
 319}
 320
 321static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
 322                                     unsigned long baud)
 323{
 324        clk_set_rate(owl_port->clk, baud * 8);
 325}
 326
 327static void owl_uart_set_termios(struct uart_port *port,
 328                                 struct ktermios *termios,
 329                                 struct ktermios *old)
 330{
 331        struct owl_uart_port *owl_port = to_owl_uart_port(port);
 332        unsigned int baud;
 333        u32 ctl;
 334        unsigned long flags;
 335
 336        spin_lock_irqsave(&port->lock, flags);
 337
 338        ctl = owl_uart_read(port, OWL_UART_CTL);
 339
 340        ctl &= ~OWL_UART_CTL_DWLS_MASK;
 341        switch (termios->c_cflag & CSIZE) {
 342        case CS5:
 343                ctl |= OWL_UART_CTL_DWLS_5BITS;
 344                break;
 345        case CS6:
 346                ctl |= OWL_UART_CTL_DWLS_6BITS;
 347                break;
 348        case CS7:
 349                ctl |= OWL_UART_CTL_DWLS_7BITS;
 350                break;
 351        case CS8:
 352        default:
 353                ctl |= OWL_UART_CTL_DWLS_8BITS;
 354                break;
 355        }
 356
 357        if (termios->c_cflag & CSTOPB)
 358                ctl |= OWL_UART_CTL_STPS_2BITS;
 359        else
 360                ctl &= ~OWL_UART_CTL_STPS_2BITS;
 361
 362        ctl &= ~OWL_UART_CTL_PRS_MASK;
 363        if (termios->c_cflag & PARENB) {
 364                if (termios->c_cflag & CMSPAR) {
 365                        if (termios->c_cflag & PARODD)
 366                                ctl |= OWL_UART_CTL_PRS_MARK;
 367                        else
 368                                ctl |= OWL_UART_CTL_PRS_SPACE;
 369                } else if (termios->c_cflag & PARODD)
 370                        ctl |= OWL_UART_CTL_PRS_ODD;
 371                else
 372                        ctl |= OWL_UART_CTL_PRS_EVEN;
 373        } else
 374                ctl |= OWL_UART_CTL_PRS_NONE;
 375
 376        if (termios->c_cflag & CRTSCTS)
 377                ctl |= OWL_UART_CTL_AFE;
 378        else
 379                ctl &= ~OWL_UART_CTL_AFE;
 380
 381        owl_uart_write(port, ctl, OWL_UART_CTL);
 382
 383        baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
 384        owl_uart_change_baudrate(owl_port, baud);
 385
 386        /* Don't rewrite B0 */
 387        if (tty_termios_baud_rate(termios))
 388                tty_termios_encode_baud_rate(termios, baud, baud);
 389
 390        port->read_status_mask |= OWL_UART_STAT_RXER;
 391        if (termios->c_iflag & INPCK)
 392                port->read_status_mask |= OWL_UART_STAT_RXST;
 393
 394        uart_update_timeout(port, termios->c_cflag, baud);
 395
 396        spin_unlock_irqrestore(&port->lock, flags);
 397}
 398
 399static void owl_uart_release_port(struct uart_port *port)
 400{
 401        struct platform_device *pdev = to_platform_device(port->dev);
 402        struct resource *res;
 403
 404        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 405        if (!res)
 406                return;
 407
 408        if (port->flags & UPF_IOREMAP) {
 409                devm_release_mem_region(port->dev, port->mapbase,
 410                        resource_size(res));
 411                devm_iounmap(port->dev, port->membase);
 412                port->membase = NULL;
 413        }
 414}
 415
 416static int owl_uart_request_port(struct uart_port *port)
 417{
 418        struct platform_device *pdev = to_platform_device(port->dev);
 419        struct resource *res;
 420
 421        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 422        if (!res)
 423                return -ENXIO;
 424
 425        if (!devm_request_mem_region(port->dev, port->mapbase,
 426                        resource_size(res), dev_name(port->dev)))
 427                return -EBUSY;
 428
 429        if (port->flags & UPF_IOREMAP) {
 430                port->membase = devm_ioremap(port->dev, port->mapbase,
 431                                resource_size(res));
 432                if (!port->membase)
 433                        return -EBUSY;
 434        }
 435
 436        return 0;
 437}
 438
 439static const char *owl_uart_type(struct uart_port *port)
 440{
 441        return (port->type == PORT_OWL) ? "owl-uart" : NULL;
 442}
 443
 444static int owl_uart_verify_port(struct uart_port *port,
 445                                struct serial_struct *ser)
 446{
 447        if (port->type != PORT_OWL)
 448                return -EINVAL;
 449
 450        if (port->irq != ser->irq)
 451                return -EINVAL;
 452
 453        return 0;
 454}
 455
 456static void owl_uart_config_port(struct uart_port *port, int flags)
 457{
 458        if (flags & UART_CONFIG_TYPE) {
 459                port->type = PORT_OWL;
 460                owl_uart_request_port(port);
 461        }
 462}
 463
 464static const struct uart_ops owl_uart_ops = {
 465        .set_mctrl = owl_uart_set_mctrl,
 466        .get_mctrl = owl_uart_get_mctrl,
 467        .tx_empty = owl_uart_tx_empty,
 468        .start_tx = owl_uart_start_tx,
 469        .stop_rx = owl_uart_stop_rx,
 470        .stop_tx = owl_uart_stop_tx,
 471        .startup = owl_uart_startup,
 472        .shutdown = owl_uart_shutdown,
 473        .set_termios = owl_uart_set_termios,
 474        .type = owl_uart_type,
 475        .config_port = owl_uart_config_port,
 476        .request_port = owl_uart_request_port,
 477        .release_port = owl_uart_release_port,
 478        .verify_port = owl_uart_verify_port,
 479};
 480
 481#ifdef CONFIG_SERIAL_OWL_CONSOLE
 482
 483static void owl_console_putchar(struct uart_port *port, int ch)
 484{
 485        if (!port->membase)
 486                return;
 487
 488        while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
 489                cpu_relax();
 490
 491        owl_uart_write(port, ch, OWL_UART_TXDAT);
 492}
 493
 494static void owl_uart_port_write(struct uart_port *port, const char *s,
 495                                u_int count)
 496{
 497        u32 old_ctl, val;
 498        unsigned long flags;
 499        int locked;
 500
 501        local_irq_save(flags);
 502
 503        if (port->sysrq)
 504                locked = 0;
 505        else if (oops_in_progress)
 506                locked = spin_trylock(&port->lock);
 507        else {
 508                spin_lock(&port->lock);
 509                locked = 1;
 510        }
 511
 512        old_ctl = owl_uart_read(port, OWL_UART_CTL);
 513        val = old_ctl | OWL_UART_CTL_TRFS_TX;
 514        /* disable IRQ */
 515        val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
 516        owl_uart_write(port, val, OWL_UART_CTL);
 517
 518        uart_console_write(port, s, count, owl_console_putchar);
 519
 520        /* wait until all contents have been sent out */
 521        while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
 522                cpu_relax();
 523
 524        /* clear IRQ pending */
 525        val = owl_uart_read(port, OWL_UART_STAT);
 526        val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
 527        owl_uart_write(port, val, OWL_UART_STAT);
 528
 529        owl_uart_write(port, old_ctl, OWL_UART_CTL);
 530
 531        if (locked)
 532                spin_unlock(&port->lock);
 533
 534        local_irq_restore(flags);
 535}
 536
 537static void owl_uart_console_write(struct console *co, const char *s,
 538                                   u_int count)
 539{
 540        struct owl_uart_port *owl_port;
 541
 542        owl_port = owl_uart_ports[co->index];
 543        if (!owl_port)
 544                return;
 545
 546        owl_uart_port_write(&owl_port->port, s, count);
 547}
 548
 549static int owl_uart_console_setup(struct console *co, char *options)
 550{
 551        struct owl_uart_port *owl_port;
 552        int baud = 115200;
 553        int bits = 8;
 554        int parity = 'n';
 555        int flow = 'n';
 556
 557        if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
 558                return -EINVAL;
 559
 560        owl_port = owl_uart_ports[co->index];
 561        if (!owl_port || !owl_port->port.membase)
 562                return -ENODEV;
 563
 564        if (options)
 565                uart_parse_options(options, &baud, &parity, &bits, &flow);
 566
 567        return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
 568}
 569
 570static struct console owl_uart_console = {
 571        .name = OWL_UART_DEV_NAME,
 572        .write = owl_uart_console_write,
 573        .device = uart_console_device,
 574        .setup = owl_uart_console_setup,
 575        .flags = CON_PRINTBUFFER,
 576        .index = -1,
 577        .data = &owl_uart_driver,
 578};
 579
 580static int __init owl_uart_console_init(void)
 581{
 582        register_console(&owl_uart_console);
 583
 584        return 0;
 585}
 586console_initcall(owl_uart_console_init);
 587
 588static void owl_uart_early_console_write(struct console *co,
 589                                         const char *s,
 590                                         u_int count)
 591{
 592        struct earlycon_device *dev = co->data;
 593
 594        owl_uart_port_write(&dev->port, s, count);
 595}
 596
 597static int __init
 598owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
 599{
 600        if (!device->port.membase)
 601                return -ENODEV;
 602
 603        device->con->write = owl_uart_early_console_write;
 604
 605        return 0;
 606}
 607OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
 608                    owl_uart_early_console_setup);
 609
 610#define OWL_UART_CONSOLE (&owl_uart_console)
 611#else
 612#define OWL_UART_CONSOLE NULL
 613#endif
 614
 615static struct uart_driver owl_uart_driver = {
 616        .owner = THIS_MODULE,
 617        .driver_name = "owl-uart",
 618        .dev_name = OWL_UART_DEV_NAME,
 619        .nr = OWL_UART_PORT_NUM,
 620        .cons = OWL_UART_CONSOLE,
 621};
 622
 623static const struct owl_uart_info owl_s500_info = {
 624        .tx_fifosize = 16,
 625};
 626
 627static const struct owl_uart_info owl_s900_info = {
 628        .tx_fifosize = 32,
 629};
 630
 631static const struct of_device_id owl_uart_dt_matches[] = {
 632        { .compatible = "actions,s500-uart", .data = &owl_s500_info },
 633        { .compatible = "actions,s900-uart", .data = &owl_s900_info },
 634        { }
 635};
 636MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
 637
 638static int owl_uart_probe(struct platform_device *pdev)
 639{
 640        const struct of_device_id *match;
 641        const struct owl_uart_info *info = NULL;
 642        struct resource *res_mem;
 643        struct owl_uart_port *owl_port;
 644        int ret, irq;
 645
 646        if (pdev->dev.of_node) {
 647                pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
 648                match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
 649                if (match)
 650                        info = match->data;
 651        }
 652
 653        if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
 654                dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
 655                return -EINVAL;
 656        }
 657
 658        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 659        if (!res_mem) {
 660                dev_err(&pdev->dev, "could not get mem\n");
 661                return -ENODEV;
 662        }
 663
 664        irq = platform_get_irq(pdev, 0);
 665        if (irq < 0)
 666                return irq;
 667
 668        if (owl_uart_ports[pdev->id]) {
 669                dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
 670                return -EBUSY;
 671        }
 672
 673        owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
 674        if (!owl_port)
 675                return -ENOMEM;
 676
 677        owl_port->clk = devm_clk_get(&pdev->dev, NULL);
 678        if (IS_ERR(owl_port->clk)) {
 679                dev_err(&pdev->dev, "could not get clk\n");
 680                return PTR_ERR(owl_port->clk);
 681        }
 682
 683        ret = clk_prepare_enable(owl_port->clk);
 684        if (ret) {
 685                dev_err(&pdev->dev, "could not enable clk\n");
 686                return ret;
 687        }
 688
 689        owl_port->port.dev = &pdev->dev;
 690        owl_port->port.line = pdev->id;
 691        owl_port->port.type = PORT_OWL;
 692        owl_port->port.iotype = UPIO_MEM;
 693        owl_port->port.mapbase = res_mem->start;
 694        owl_port->port.irq = irq;
 695        owl_port->port.uartclk = clk_get_rate(owl_port->clk);
 696        if (owl_port->port.uartclk == 0) {
 697                dev_err(&pdev->dev, "clock rate is zero\n");
 698                return -EINVAL;
 699        }
 700        owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
 701        owl_port->port.x_char = 0;
 702        owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
 703        owl_port->port.ops = &owl_uart_ops;
 704
 705        owl_uart_ports[pdev->id] = owl_port;
 706        platform_set_drvdata(pdev, owl_port);
 707
 708        ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
 709        if (ret)
 710                owl_uart_ports[pdev->id] = NULL;
 711
 712        return ret;
 713}
 714
 715static int owl_uart_remove(struct platform_device *pdev)
 716{
 717        struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
 718
 719        uart_remove_one_port(&owl_uart_driver, &owl_port->port);
 720        owl_uart_ports[pdev->id] = NULL;
 721        clk_disable_unprepare(owl_port->clk);
 722
 723        return 0;
 724}
 725
 726static struct platform_driver owl_uart_platform_driver = {
 727        .probe = owl_uart_probe,
 728        .remove = owl_uart_remove,
 729        .driver = {
 730                .name = "owl-uart",
 731                .of_match_table = owl_uart_dt_matches,
 732        },
 733};
 734
 735static int __init owl_uart_init(void)
 736{
 737        int ret;
 738
 739        ret = uart_register_driver(&owl_uart_driver);
 740        if (ret)
 741                return ret;
 742
 743        ret = platform_driver_register(&owl_uart_platform_driver);
 744        if (ret)
 745                uart_unregister_driver(&owl_uart_driver);
 746
 747        return ret;
 748}
 749
 750static void __exit owl_uart_exit(void)
 751{
 752        platform_driver_unregister(&owl_uart_platform_driver);
 753        uart_unregister_driver(&owl_uart_driver);
 754}
 755
 756module_init(owl_uart_init);
 757module_exit(owl_uart_exit);
 758
 759MODULE_LICENSE("GPL");
 760