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25
26#undef DEBUG
27#undef DEBUG_HARD
28#undef USE_CTRL_O_SYSRQ
29
30#include <linux/module.h>
31#include <linux/tty.h>
32
33#include <linux/tty_flip.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/fcntl.h>
37#include <linux/mm.h>
38#include <linux/kernel.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/console.h>
42#include <linux/adb.h>
43#include <linux/pmu.h>
44#include <linux/bitops.h>
45#include <linux/sysrq.h>
46#include <linux/mutex.h>
47#include <linux/of_address.h>
48#include <linux/of_irq.h>
49#include <asm/sections.h>
50#include <asm/io.h>
51#include <asm/irq.h>
52
53#ifdef CONFIG_PPC_PMAC
54#include <asm/prom.h>
55#include <asm/machdep.h>
56#include <asm/pmac_feature.h>
57#include <asm/dbdma.h>
58#include <asm/macio.h>
59#else
60#include <linux/platform_device.h>
61#define of_machine_is_compatible(x) (0)
62#endif
63
64#include <linux/serial.h>
65#include <linux/serial_core.h>
66
67#include "pmac_zilog.h"
68
69
70#undef HAS_DBDMA
71
72static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
73MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
74MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
75MODULE_LICENSE("GPL");
76
77#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
78#define PMACZILOG_MAJOR TTY_MAJOR
79#define PMACZILOG_MINOR 64
80#define PMACZILOG_NAME "ttyS"
81#else
82#define PMACZILOG_MAJOR 204
83#define PMACZILOG_MINOR 192
84#define PMACZILOG_NAME "ttyPZ"
85#endif
86
87#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
88#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
89#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
90
91
92
93
94
95static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
96static int pmz_ports_count;
97
98static struct uart_driver pmz_uart_reg = {
99 .owner = THIS_MODULE,
100 .driver_name = PMACZILOG_NAME,
101 .dev_name = PMACZILOG_NAME,
102 .major = PMACZILOG_MAJOR,
103 .minor = PMACZILOG_MINOR,
104};
105
106
107
108
109
110
111
112static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
113{
114 int i;
115
116
117 for (i = 0; i < 1000; i++) {
118 unsigned char stat = read_zsreg(uap, R1);
119 if (stat & ALL_SNT)
120 break;
121 udelay(100);
122 }
123
124 ZS_CLEARERR(uap);
125 zssync(uap);
126 ZS_CLEARFIFO(uap);
127 zssync(uap);
128 ZS_CLEARERR(uap);
129
130
131 write_zsreg(uap, R1,
132 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
133
134
135 write_zsreg(uap, R4, regs[R4]);
136
137
138 write_zsreg(uap, R10, regs[R10]);
139
140
141 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
143
144
145 write_zsreg(uap, R15, regs[R15] | EN85C30);
146 write_zsreg(uap, R7, regs[R7P]);
147
148
149 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
150
151
152 write_zsreg(uap, R6, regs[R6]);
153 write_zsreg(uap, R7, regs[R7]);
154
155
156 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
157
158
159 write_zsreg(uap, R11, regs[R11]);
160
161
162 write_zsreg(uap, R12, regs[R12]);
163 write_zsreg(uap, R13, regs[R13]);
164
165
166 write_zsreg(uap, R14, regs[R14]);
167
168
169 write_zsreg(uap, R0, RES_EXT_INT);
170 write_zsreg(uap, R0, RES_EXT_INT);
171
172
173 write_zsreg(uap, R3, regs[R3]);
174 write_zsreg(uap, R5, regs[R5]);
175
176
177 write_zsreg(uap, R1, regs[R1]);
178
179
180 write_zsreg(uap, R9, regs[R9]);
181}
182
183
184
185
186
187
188
189
190
191static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
192{
193 if (!ZS_REGS_HELD(uap)) {
194 if (ZS_TX_ACTIVE(uap)) {
195 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
196 } else {
197 pmz_debug("pmz: maybe_update_regs: updating\n");
198 pmz_load_zsregs(uap, uap->curregs);
199 }
200 }
201}
202
203static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
204{
205 if (enable) {
206 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
207 if (!ZS_IS_EXTCLK(uap))
208 uap->curregs[1] |= EXT_INT_ENAB;
209 } else {
210 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
211 }
212 write_zsreg(uap, R1, uap->curregs[1]);
213}
214
215static bool pmz_receive_chars(struct uart_pmac_port *uap)
216{
217 struct tty_port *port;
218 unsigned char ch, r1, drop, flag;
219 int loops = 0;
220
221
222 if (uap->port.state == NULL) {
223 WARN_ON(1);
224 (void)read_zsdata(uap);
225 return false;
226 }
227 port = &uap->port.state->port;
228
229 while (1) {
230 drop = 0;
231
232 r1 = read_zsreg(uap, R1);
233 ch = read_zsdata(uap);
234
235 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
236 write_zsreg(uap, R0, ERR_RES);
237 zssync(uap);
238 }
239
240 ch &= uap->parity_mask;
241 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
242 uap->flags &= ~PMACZILOG_FLAG_BREAK;
243 }
244
245#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
246#ifdef USE_CTRL_O_SYSRQ
247
248 if (ch == '\x0f') {
249 uap->port.sysrq = jiffies + HZ*5;
250 goto next_char;
251 }
252#endif
253 if (uap->port.sysrq) {
254 int swallow;
255 spin_unlock(&uap->port.lock);
256 swallow = uart_handle_sysrq_char(&uap->port, ch);
257 spin_lock(&uap->port.lock);
258 if (swallow)
259 goto next_char;
260 }
261#endif
262
263
264 if (drop)
265 goto next_char;
266
267 flag = TTY_NORMAL;
268 uap->port.icount.rx++;
269
270 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
271 if (r1 & BRK_ABRT) {
272 pmz_debug("pmz: got break !\n");
273 r1 &= ~(PAR_ERR | CRC_ERR);
274 uap->port.icount.brk++;
275 if (uart_handle_break(&uap->port))
276 goto next_char;
277 }
278 else if (r1 & PAR_ERR)
279 uap->port.icount.parity++;
280 else if (r1 & CRC_ERR)
281 uap->port.icount.frame++;
282 if (r1 & Rx_OVR)
283 uap->port.icount.overrun++;
284 r1 &= uap->port.read_status_mask;
285 if (r1 & BRK_ABRT)
286 flag = TTY_BREAK;
287 else if (r1 & PAR_ERR)
288 flag = TTY_PARITY;
289 else if (r1 & CRC_ERR)
290 flag = TTY_FRAME;
291 }
292
293 if (uap->port.ignore_status_mask == 0xff ||
294 (r1 & uap->port.ignore_status_mask) == 0) {
295 tty_insert_flip_char(port, ch, flag);
296 }
297 if (r1 & Rx_OVR)
298 tty_insert_flip_char(port, 0, TTY_OVERRUN);
299 next_char:
300
301
302
303
304
305
306
307 if ((++loops) > 1000)
308 goto flood;
309 ch = read_zsreg(uap, R0);
310 if (!(ch & Rx_CH_AV))
311 break;
312 }
313
314 return true;
315 flood:
316 pmz_interrupt_control(uap, 0);
317 pmz_error("pmz: rx irq flood !\n");
318 return true;
319}
320
321static void pmz_status_handle(struct uart_pmac_port *uap)
322{
323 unsigned char status;
324
325 status = read_zsreg(uap, R0);
326 write_zsreg(uap, R0, RES_EXT_INT);
327 zssync(uap);
328
329 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
330 if (status & SYNC_HUNT)
331 uap->port.icount.dsr++;
332
333
334
335
336
337
338 if ((status ^ uap->prev_status) & DCD)
339 uart_handle_dcd_change(&uap->port,
340 (status & DCD));
341 if ((status ^ uap->prev_status) & CTS)
342 uart_handle_cts_change(&uap->port,
343 !(status & CTS));
344
345 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
346 }
347
348 if (status & BRK_ABRT)
349 uap->flags |= PMACZILOG_FLAG_BREAK;
350
351 uap->prev_status = status;
352}
353
354static void pmz_transmit_chars(struct uart_pmac_port *uap)
355{
356 struct circ_buf *xmit;
357
358 if (ZS_IS_CONS(uap)) {
359 unsigned char status = read_zsreg(uap, R0);
360
361
362
363
364
365
366
367
368
369 if (!(status & Tx_BUF_EMP))
370 return;
371 }
372
373 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
374
375 if (ZS_REGS_HELD(uap)) {
376 pmz_load_zsregs(uap, uap->curregs);
377 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
378 }
379
380 if (ZS_TX_STOPPED(uap)) {
381 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
382 goto ack_tx_int;
383 }
384
385
386
387
388
389
390
391
392
393 if (!ZS_IS_OPEN(uap))
394 goto ack_tx_int;
395
396 if (uap->port.x_char) {
397 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
398 write_zsdata(uap, uap->port.x_char);
399 zssync(uap);
400 uap->port.icount.tx++;
401 uap->port.x_char = 0;
402 return;
403 }
404
405 if (uap->port.state == NULL)
406 goto ack_tx_int;
407 xmit = &uap->port.state->xmit;
408 if (uart_circ_empty(xmit)) {
409 uart_write_wakeup(&uap->port);
410 goto ack_tx_int;
411 }
412 if (uart_tx_stopped(&uap->port))
413 goto ack_tx_int;
414
415 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
416 write_zsdata(uap, xmit->buf[xmit->tail]);
417 zssync(uap);
418
419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
420 uap->port.icount.tx++;
421
422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
423 uart_write_wakeup(&uap->port);
424
425 return;
426
427ack_tx_int:
428 write_zsreg(uap, R0, RES_Tx_P);
429 zssync(uap);
430}
431
432
433static irqreturn_t pmz_interrupt(int irq, void *dev_id)
434{
435 struct uart_pmac_port *uap = dev_id;
436 struct uart_pmac_port *uap_a;
437 struct uart_pmac_port *uap_b;
438 int rc = IRQ_NONE;
439 bool push;
440 u8 r3;
441
442 uap_a = pmz_get_port_A(uap);
443 uap_b = uap_a->mate;
444
445 spin_lock(&uap_a->port.lock);
446 r3 = read_zsreg(uap_a, R3);
447
448#ifdef DEBUG_HARD
449 pmz_debug("irq, r3: %x\n", r3);
450#endif
451
452 push = false;
453 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
454 if (!ZS_IS_OPEN(uap_a)) {
455 pmz_debug("ChanA interrupt while not open !\n");
456 goto skip_a;
457 }
458 write_zsreg(uap_a, R0, RES_H_IUS);
459 zssync(uap_a);
460 if (r3 & CHAEXT)
461 pmz_status_handle(uap_a);
462 if (r3 & CHARxIP)
463 push = pmz_receive_chars(uap_a);
464 if (r3 & CHATxIP)
465 pmz_transmit_chars(uap_a);
466 rc = IRQ_HANDLED;
467 }
468 skip_a:
469 spin_unlock(&uap_a->port.lock);
470 if (push)
471 tty_flip_buffer_push(&uap->port.state->port);
472
473 if (!uap_b)
474 goto out;
475
476 spin_lock(&uap_b->port.lock);
477 push = false;
478 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
479 if (!ZS_IS_OPEN(uap_b)) {
480 pmz_debug("ChanB interrupt while not open !\n");
481 goto skip_b;
482 }
483 write_zsreg(uap_b, R0, RES_H_IUS);
484 zssync(uap_b);
485 if (r3 & CHBEXT)
486 pmz_status_handle(uap_b);
487 if (r3 & CHBRxIP)
488 push = pmz_receive_chars(uap_b);
489 if (r3 & CHBTxIP)
490 pmz_transmit_chars(uap_b);
491 rc = IRQ_HANDLED;
492 }
493 skip_b:
494 spin_unlock(&uap_b->port.lock);
495 if (push)
496 tty_flip_buffer_push(&uap->port.state->port);
497
498 out:
499 return rc;
500}
501
502
503
504
505static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
506{
507 unsigned long flags;
508 u8 status;
509
510 spin_lock_irqsave(&uap->port.lock, flags);
511 status = read_zsreg(uap, R0);
512 spin_unlock_irqrestore(&uap->port.lock, flags);
513
514 return status;
515}
516
517
518
519
520
521static unsigned int pmz_tx_empty(struct uart_port *port)
522{
523 unsigned char status;
524
525 status = pmz_peek_status(to_pmz(port));
526 if (status & Tx_BUF_EMP)
527 return TIOCSER_TEMT;
528 return 0;
529}
530
531
532
533
534
535
536
537static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
538{
539 struct uart_pmac_port *uap = to_pmz(port);
540 unsigned char set_bits, clear_bits;
541
542
543 if (ZS_IS_IRDA(uap))
544 return;
545
546 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
547 return;
548
549 set_bits = clear_bits = 0;
550
551 if (ZS_IS_INTMODEM(uap)) {
552 if (mctrl & TIOCM_RTS)
553 set_bits |= RTS;
554 else
555 clear_bits |= RTS;
556 }
557 if (mctrl & TIOCM_DTR)
558 set_bits |= DTR;
559 else
560 clear_bits |= DTR;
561
562
563 uap->curregs[R5] |= set_bits;
564 uap->curregs[R5] &= ~clear_bits;
565
566 write_zsreg(uap, R5, uap->curregs[R5]);
567 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
568 set_bits, clear_bits, uap->curregs[R5]);
569 zssync(uap);
570}
571
572
573
574
575
576
577static unsigned int pmz_get_mctrl(struct uart_port *port)
578{
579 struct uart_pmac_port *uap = to_pmz(port);
580 unsigned char status;
581 unsigned int ret;
582
583 status = read_zsreg(uap, R0);
584
585 ret = 0;
586 if (status & DCD)
587 ret |= TIOCM_CAR;
588 if (status & SYNC_HUNT)
589 ret |= TIOCM_DSR;
590 if (!(status & CTS))
591 ret |= TIOCM_CTS;
592
593 return ret;
594}
595
596
597
598
599
600
601static void pmz_stop_tx(struct uart_port *port)
602{
603 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
604}
605
606
607
608
609
610static void pmz_start_tx(struct uart_port *port)
611{
612 struct uart_pmac_port *uap = to_pmz(port);
613 unsigned char status;
614
615 pmz_debug("pmz: start_tx()\n");
616
617 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
618 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
619
620 status = read_zsreg(uap, R0);
621
622
623 if (!(status & Tx_BUF_EMP))
624 return;
625
626
627
628
629 if (port->x_char) {
630 write_zsdata(uap, port->x_char);
631 zssync(uap);
632 port->icount.tx++;
633 port->x_char = 0;
634 } else {
635 struct circ_buf *xmit = &port->state->xmit;
636
637 if (uart_circ_empty(xmit))
638 goto out;
639 write_zsdata(uap, xmit->buf[xmit->tail]);
640 zssync(uap);
641 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
642 port->icount.tx++;
643
644 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
645 uart_write_wakeup(&uap->port);
646 }
647 out:
648 pmz_debug("pmz: start_tx() done.\n");
649}
650
651
652
653
654
655
656
657static void pmz_stop_rx(struct uart_port *port)
658{
659 struct uart_pmac_port *uap = to_pmz(port);
660
661 pmz_debug("pmz: stop_rx()()\n");
662
663
664 uap->curregs[R1] &= ~RxINT_MASK;
665 pmz_maybe_update_regs(uap);
666
667 pmz_debug("pmz: stop_rx() done.\n");
668}
669
670
671
672
673
674static void pmz_enable_ms(struct uart_port *port)
675{
676 struct uart_pmac_port *uap = to_pmz(port);
677 unsigned char new_reg;
678
679 if (ZS_IS_IRDA(uap))
680 return;
681 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
682 if (new_reg != uap->curregs[R15]) {
683 uap->curregs[R15] = new_reg;
684
685
686 write_zsreg(uap, R15, uap->curregs[R15]);
687 }
688}
689
690
691
692
693
694static void pmz_break_ctl(struct uart_port *port, int break_state)
695{
696 struct uart_pmac_port *uap = to_pmz(port);
697 unsigned char set_bits, clear_bits, new_reg;
698 unsigned long flags;
699
700 set_bits = clear_bits = 0;
701
702 if (break_state)
703 set_bits |= SND_BRK;
704 else
705 clear_bits |= SND_BRK;
706
707 spin_lock_irqsave(&port->lock, flags);
708
709 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
710 if (new_reg != uap->curregs[R5]) {
711 uap->curregs[R5] = new_reg;
712 write_zsreg(uap, R5, uap->curregs[R5]);
713 }
714
715 spin_unlock_irqrestore(&port->lock, flags);
716}
717
718#ifdef CONFIG_PPC_PMAC
719
720
721
722
723
724
725
726static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
727{
728 int delay = 0;
729 int rc;
730
731 if (state) {
732 rc = pmac_call_feature(
733 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
734 pmz_debug("port power on result: %d\n", rc);
735 if (ZS_IS_INTMODEM(uap)) {
736 rc = pmac_call_feature(
737 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
738 delay = 2500;
739 pmz_debug("modem power result: %d\n", rc);
740 }
741 } else {
742
743
744
745 if (ZS_IS_INTMODEM(uap)) {
746 rc = pmac_call_feature(
747 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
748 pmz_debug("port power off result: %d\n", rc);
749 }
750 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
751 }
752 return delay;
753}
754
755#else
756
757static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
758{
759 return 0;
760}
761
762#endif
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
785{
786 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
787 zssync(uap);
788 udelay(10);
789 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
790 zssync(uap);
791
792 write_zsreg(uap, 4, X1CLK | MONSYNC);
793 write_zsreg(uap, 3, Rx8);
794 write_zsreg(uap, 5, Tx8 | RTS);
795 write_zsreg(uap, 9, NV);
796 write_zsreg(uap, 11, RCBR | TCBR);
797 write_zsreg(uap, 12, 0);
798 write_zsreg(uap, 13, 0);
799 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
800 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
801 write_zsreg(uap, 3, Rx8 | RxENABLE);
802 write_zsreg(uap, 0, RES_EXT_INT);
803 write_zsreg(uap, 0, RES_EXT_INT);
804 write_zsreg(uap, 0, RES_EXT_INT);
805
806
807
808
809
810
811 write_zsreg(uap, 9, NV);
812 write_zsreg(uap, 4, X16CLK | SB_MASK);
813 write_zsreg(uap, 3, Rx8);
814
815 while (read_zsreg(uap, 0) & Rx_CH_AV) {
816 (void)read_zsreg(uap, 8);
817 write_zsreg(uap, 0, RES_EXT_INT);
818 write_zsreg(uap, 0, ERR_RES);
819 }
820}
821
822
823
824
825
826
827
828static int __pmz_startup(struct uart_pmac_port *uap)
829{
830 int pwr_delay = 0;
831
832 memset(&uap->curregs, 0, sizeof(uap->curregs));
833
834
835 pwr_delay = pmz_set_scc_power(uap, 1);
836
837
838 pmz_fix_zero_bug_scc(uap);
839
840
841 uap->curregs[R9] = 0;
842 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
843 zssync(uap);
844 udelay(10);
845 write_zsreg(uap, 9, 0);
846 zssync(uap);
847
848
849 write_zsreg(uap, R1, 0);
850 write_zsreg(uap, R0, ERR_RES);
851 write_zsreg(uap, R0, ERR_RES);
852 write_zsreg(uap, R0, RES_H_IUS);
853 write_zsreg(uap, R0, RES_H_IUS);
854
855
856 uap->curregs[R4] = X16CLK | SB1;
857 uap->curregs[R3] = Rx8;
858 uap->curregs[R5] = Tx8 | RTS;
859 if (!ZS_IS_IRDA(uap))
860 uap->curregs[R5] |= DTR;
861 uap->curregs[R12] = 0;
862 uap->curregs[R13] = 0;
863 uap->curregs[R14] = BRENAB;
864
865
866 uap->curregs[R15] = BRKIE;
867
868
869 uap->curregs[R9] |= NV | MIE;
870
871 pmz_load_zsregs(uap, uap->curregs);
872
873
874 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
875 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
876
877
878 uap->prev_status = read_zsreg(uap, R0);
879
880 return pwr_delay;
881}
882
883static void pmz_irda_reset(struct uart_pmac_port *uap)
884{
885 unsigned long flags;
886
887 spin_lock_irqsave(&uap->port.lock, flags);
888 uap->curregs[R5] |= DTR;
889 write_zsreg(uap, R5, uap->curregs[R5]);
890 zssync(uap);
891 spin_unlock_irqrestore(&uap->port.lock, flags);
892 msleep(110);
893
894 spin_lock_irqsave(&uap->port.lock, flags);
895 uap->curregs[R5] &= ~DTR;
896 write_zsreg(uap, R5, uap->curregs[R5]);
897 zssync(uap);
898 spin_unlock_irqrestore(&uap->port.lock, flags);
899 msleep(10);
900}
901
902
903
904
905
906static int pmz_startup(struct uart_port *port)
907{
908 struct uart_pmac_port *uap = to_pmz(port);
909 unsigned long flags;
910 int pwr_delay = 0;
911
912 pmz_debug("pmz: startup()\n");
913
914 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
915
916
917
918
919 if (!ZS_IS_CONS(uap)) {
920 spin_lock_irqsave(&port->lock, flags);
921 pwr_delay = __pmz_startup(uap);
922 spin_unlock_irqrestore(&port->lock, flags);
923 }
924 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
925 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
926 uap->irq_name, uap)) {
927 pmz_error("Unable to register zs interrupt handler.\n");
928 pmz_set_scc_power(uap, 0);
929 return -ENXIO;
930 }
931
932
933
934
935 if (pwr_delay != 0) {
936 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
937 msleep(pwr_delay);
938 }
939
940
941 if (ZS_IS_IRDA(uap))
942 pmz_irda_reset(uap);
943
944
945 spin_lock_irqsave(&port->lock, flags);
946 pmz_interrupt_control(uap, 1);
947 spin_unlock_irqrestore(&port->lock, flags);
948
949 pmz_debug("pmz: startup() done.\n");
950
951 return 0;
952}
953
954static void pmz_shutdown(struct uart_port *port)
955{
956 struct uart_pmac_port *uap = to_pmz(port);
957 unsigned long flags;
958
959 pmz_debug("pmz: shutdown()\n");
960
961 spin_lock_irqsave(&port->lock, flags);
962
963
964 pmz_interrupt_control(uap, 0);
965
966 if (!ZS_IS_CONS(uap)) {
967
968 uap->curregs[R3] &= ~RxENABLE;
969 uap->curregs[R5] &= ~TxENABLE;
970
971
972 uap->curregs[R5] &= ~SND_BRK;
973 pmz_maybe_update_regs(uap);
974 }
975
976 spin_unlock_irqrestore(&port->lock, flags);
977
978
979 free_irq(uap->port.irq, uap);
980
981 spin_lock_irqsave(&port->lock, flags);
982
983 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
984
985 if (!ZS_IS_CONS(uap))
986 pmz_set_scc_power(uap, 0);
987
988 spin_unlock_irqrestore(&port->lock, flags);
989
990 pmz_debug("pmz: shutdown() done.\n");
991}
992
993
994
995
996static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
997 unsigned int iflag, unsigned long baud)
998{
999 int brg;
1000
1001
1002
1003
1004
1005 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1006 uap->curregs[R4] = X1CLK;
1007 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1008 uap->curregs[R14] = 0;
1009 uap->curregs[R12] = 0;
1010 uap->curregs[R13] = 0;
1011 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1012 } else {
1013 switch (baud) {
1014 case ZS_CLOCK/16:
1015 uap->curregs[R4] = X16CLK;
1016 uap->curregs[R11] = 0;
1017 uap->curregs[R14] = 0;
1018 break;
1019 case ZS_CLOCK/32:
1020 uap->curregs[R4] = X32CLK;
1021 uap->curregs[R11] = 0;
1022 uap->curregs[R14] = 0;
1023 break;
1024 default:
1025 uap->curregs[R4] = X16CLK;
1026 uap->curregs[R11] = TCBR | RCBR;
1027 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1028 uap->curregs[R12] = (brg & 255);
1029 uap->curregs[R13] = ((brg >> 8) & 255);
1030 uap->curregs[R14] = BRENAB;
1031 }
1032 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1033 }
1034
1035
1036 uap->curregs[3] &= ~RxN_MASK;
1037 uap->curregs[5] &= ~TxN_MASK;
1038
1039 switch (cflag & CSIZE) {
1040 case CS5:
1041 uap->curregs[3] |= Rx5;
1042 uap->curregs[5] |= Tx5;
1043 uap->parity_mask = 0x1f;
1044 break;
1045 case CS6:
1046 uap->curregs[3] |= Rx6;
1047 uap->curregs[5] |= Tx6;
1048 uap->parity_mask = 0x3f;
1049 break;
1050 case CS7:
1051 uap->curregs[3] |= Rx7;
1052 uap->curregs[5] |= Tx7;
1053 uap->parity_mask = 0x7f;
1054 break;
1055 case CS8:
1056 default:
1057 uap->curregs[3] |= Rx8;
1058 uap->curregs[5] |= Tx8;
1059 uap->parity_mask = 0xff;
1060 break;
1061 }
1062 uap->curregs[4] &= ~(SB_MASK);
1063 if (cflag & CSTOPB)
1064 uap->curregs[4] |= SB2;
1065 else
1066 uap->curregs[4] |= SB1;
1067 if (cflag & PARENB)
1068 uap->curregs[4] |= PAR_ENAB;
1069 else
1070 uap->curregs[4] &= ~PAR_ENAB;
1071 if (!(cflag & PARODD))
1072 uap->curregs[4] |= PAR_EVEN;
1073 else
1074 uap->curregs[4] &= ~PAR_EVEN;
1075
1076 uap->port.read_status_mask = Rx_OVR;
1077 if (iflag & INPCK)
1078 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1079 if (iflag & (IGNBRK | BRKINT | PARMRK))
1080 uap->port.read_status_mask |= BRK_ABRT;
1081
1082 uap->port.ignore_status_mask = 0;
1083 if (iflag & IGNPAR)
1084 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1085 if (iflag & IGNBRK) {
1086 uap->port.ignore_status_mask |= BRK_ABRT;
1087 if (iflag & IGNPAR)
1088 uap->port.ignore_status_mask |= Rx_OVR;
1089 }
1090
1091 if ((cflag & CREAD) == 0)
1092 uap->port.ignore_status_mask = 0xff;
1093}
1094
1095
1096
1097
1098
1099static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1100{
1101 u8 cmdbyte;
1102 int t, version;
1103
1104 switch (*baud) {
1105
1106 case 2400:
1107 cmdbyte = 0x53;
1108 break;
1109 case 4800:
1110 cmdbyte = 0x52;
1111 break;
1112 case 9600:
1113 cmdbyte = 0x51;
1114 break;
1115 case 19200:
1116 cmdbyte = 0x50;
1117 break;
1118 case 38400:
1119 cmdbyte = 0x4f;
1120 break;
1121 case 57600:
1122 cmdbyte = 0x4e;
1123 break;
1124 case 115200:
1125 cmdbyte = 0x4d;
1126 break;
1127
1128
1129
1130 case 1152000:
1131 cmdbyte = 0;
1132 break;
1133 case 4000000:
1134 cmdbyte = 0;
1135 break;
1136 default:
1137 cmdbyte = 0x51;
1138 *baud = 9600;
1139 break;
1140 }
1141
1142
1143 t = 10000;
1144 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1145 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1146 if (--t <= 0) {
1147 pmz_error("transmitter didn't drain\n");
1148 return;
1149 }
1150 udelay(10);
1151 }
1152
1153
1154 t = 100;
1155 (void)read_zsdata(uap);
1156 (void)read_zsdata(uap);
1157 (void)read_zsdata(uap);
1158 mdelay(10);
1159 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1160 read_zsdata(uap);
1161 mdelay(10);
1162 if (--t <= 0) {
1163 pmz_error("receiver didn't drain\n");
1164 return;
1165 }
1166 }
1167
1168
1169 uap->curregs[R5] |= DTR;
1170 write_zsreg(uap, R5, uap->curregs[R5]);
1171 zssync(uap);
1172 mdelay(1);
1173
1174
1175 pmz_convert_to_zs(uap, CS8, 0, 19200);
1176 pmz_load_zsregs(uap, uap->curregs);
1177 mdelay(1);
1178
1179
1180 write_zsdata(uap, 1);
1181 t = 5000;
1182 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1183 if (--t <= 0) {
1184 pmz_error("irda_setup timed out on get_version byte\n");
1185 goto out;
1186 }
1187 udelay(10);
1188 }
1189 version = read_zsdata(uap);
1190
1191 if (version < 4) {
1192 pmz_info("IrDA: dongle version %d not supported\n", version);
1193 goto out;
1194 }
1195
1196
1197 write_zsdata(uap, cmdbyte);
1198 t = 5000;
1199 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1200 if (--t <= 0) {
1201 pmz_error("irda_setup timed out on speed mode byte\n");
1202 goto out;
1203 }
1204 udelay(10);
1205 }
1206 t = read_zsdata(uap);
1207 if (t != cmdbyte)
1208 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1209
1210 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1211 *baud, version);
1212
1213 (void)read_zsdata(uap);
1214 (void)read_zsdata(uap);
1215 (void)read_zsdata(uap);
1216
1217 out:
1218
1219 uap->curregs[R5] &= ~DTR;
1220 write_zsreg(uap, R5, uap->curregs[R5]);
1221 zssync(uap);
1222
1223 (void)read_zsdata(uap);
1224 (void)read_zsdata(uap);
1225 (void)read_zsdata(uap);
1226}
1227
1228
1229static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1230 struct ktermios *old)
1231{
1232 struct uart_pmac_port *uap = to_pmz(port);
1233 unsigned long baud;
1234
1235 pmz_debug("pmz: set_termios()\n");
1236
1237 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1238
1239
1240
1241
1242
1243
1244
1245
1246 if (ZS_IS_IRDA(uap)) {
1247
1248 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1249 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1250
1251 pmz_irda_setup(uap, &baud);
1252
1253 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1254 pmz_load_zsregs(uap, uap->curregs);
1255 zssync(uap);
1256 } else {
1257 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1258 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1259
1260 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1261 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1262 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1263 } else {
1264 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1265 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1266 }
1267
1268
1269 pmz_maybe_update_regs(uap);
1270 }
1271 uart_update_timeout(port, termios->c_cflag, baud);
1272
1273 pmz_debug("pmz: set_termios() done.\n");
1274}
1275
1276
1277static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1278 struct ktermios *old)
1279{
1280 struct uart_pmac_port *uap = to_pmz(port);
1281 unsigned long flags;
1282
1283 spin_lock_irqsave(&port->lock, flags);
1284
1285
1286 pmz_interrupt_control(uap, 0);
1287
1288
1289 __pmz_set_termios(port, termios, old);
1290
1291
1292 if (ZS_IS_OPEN(uap))
1293 pmz_interrupt_control(uap, 1);
1294
1295 spin_unlock_irqrestore(&port->lock, flags);
1296}
1297
1298static const char *pmz_type(struct uart_port *port)
1299{
1300 struct uart_pmac_port *uap = to_pmz(port);
1301
1302 if (ZS_IS_IRDA(uap))
1303 return "Z85c30 ESCC - Infrared port";
1304 else if (ZS_IS_INTMODEM(uap))
1305 return "Z85c30 ESCC - Internal modem";
1306 return "Z85c30 ESCC - Serial port";
1307}
1308
1309
1310
1311
1312static void pmz_release_port(struct uart_port *port)
1313{
1314}
1315
1316static int pmz_request_port(struct uart_port *port)
1317{
1318 return 0;
1319}
1320
1321
1322static void pmz_config_port(struct uart_port *port, int flags)
1323{
1324}
1325
1326
1327static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1328{
1329 return -EINVAL;
1330}
1331
1332#ifdef CONFIG_CONSOLE_POLL
1333
1334static int pmz_poll_get_char(struct uart_port *port)
1335{
1336 struct uart_pmac_port *uap =
1337 container_of(port, struct uart_pmac_port, port);
1338 int tries = 2;
1339
1340 while (tries) {
1341 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1342 return read_zsdata(uap);
1343 if (tries--)
1344 udelay(5);
1345 }
1346
1347 return NO_POLL_CHAR;
1348}
1349
1350static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1351{
1352 struct uart_pmac_port *uap =
1353 container_of(port, struct uart_pmac_port, port);
1354
1355
1356 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1357 udelay(5);
1358 write_zsdata(uap, c);
1359}
1360
1361#endif
1362
1363static const struct uart_ops pmz_pops = {
1364 .tx_empty = pmz_tx_empty,
1365 .set_mctrl = pmz_set_mctrl,
1366 .get_mctrl = pmz_get_mctrl,
1367 .stop_tx = pmz_stop_tx,
1368 .start_tx = pmz_start_tx,
1369 .stop_rx = pmz_stop_rx,
1370 .enable_ms = pmz_enable_ms,
1371 .break_ctl = pmz_break_ctl,
1372 .startup = pmz_startup,
1373 .shutdown = pmz_shutdown,
1374 .set_termios = pmz_set_termios,
1375 .type = pmz_type,
1376 .release_port = pmz_release_port,
1377 .request_port = pmz_request_port,
1378 .config_port = pmz_config_port,
1379 .verify_port = pmz_verify_port,
1380#ifdef CONFIG_CONSOLE_POLL
1381 .poll_get_char = pmz_poll_get_char,
1382 .poll_put_char = pmz_poll_put_char,
1383#endif
1384};
1385
1386#ifdef CONFIG_PPC_PMAC
1387
1388
1389
1390
1391
1392
1393static int __init pmz_init_port(struct uart_pmac_port *uap)
1394{
1395 struct device_node *np = uap->node;
1396 const char *conn;
1397 const struct slot_names_prop {
1398 int count;
1399 char name[1];
1400 } *slots;
1401 int len;
1402 struct resource r_ports, r_rxdma, r_txdma;
1403
1404
1405
1406
1407 if (of_address_to_resource(np, 0, &r_ports))
1408 return -ENODEV;
1409 uap->port.mapbase = r_ports.start;
1410 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1411
1412 uap->control_reg = uap->port.membase;
1413 uap->data_reg = uap->control_reg + 0x10;
1414
1415
1416
1417
1418#ifdef HAS_DBDMA
1419 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1420 of_address_to_resource(np, 2, &r_rxdma) == 0)
1421 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1422#else
1423 memset(&r_txdma, 0, sizeof(struct resource));
1424 memset(&r_rxdma, 0, sizeof(struct resource));
1425#endif
1426 if (ZS_HAS_DMA(uap)) {
1427 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1428 if (uap->tx_dma_regs == NULL) {
1429 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1430 goto no_dma;
1431 }
1432 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1433 if (uap->rx_dma_regs == NULL) {
1434 iounmap(uap->tx_dma_regs);
1435 uap->tx_dma_regs = NULL;
1436 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1437 goto no_dma;
1438 }
1439 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1440 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1441 }
1442no_dma:
1443
1444
1445
1446
1447 if (of_device_is_compatible(np, "cobalt"))
1448 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1449 conn = of_get_property(np, "AAPL,connector", &len);
1450 if (conn && (strcmp(conn, "infrared") == 0))
1451 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1452 uap->port_type = PMAC_SCC_ASYNC;
1453
1454 slots = of_get_property(np, "slot-names", &len);
1455 if (slots && slots->count > 0) {
1456 if (strcmp(slots->name, "IrDA") == 0)
1457 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1458 else if (strcmp(slots->name, "Modem") == 0)
1459 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1460 }
1461 if (ZS_IS_IRDA(uap))
1462 uap->port_type = PMAC_SCC_IRDA;
1463 if (ZS_IS_INTMODEM(uap)) {
1464 struct device_node* i2c_modem =
1465 of_find_node_by_name(NULL, "i2c-modem");
1466 if (i2c_modem) {
1467 const char* mid =
1468 of_get_property(i2c_modem, "modem-id", NULL);
1469 if (mid) switch(*mid) {
1470 case 0x04 :
1471 case 0x05 :
1472 case 0x07 :
1473 case 0x08 :
1474 case 0x0b :
1475 case 0x0c :
1476 uap->port_type = PMAC_SCC_I2S1;
1477 }
1478 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1479 mid ? (*mid) : 0);
1480 of_node_put(i2c_modem);
1481 } else {
1482 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1483 }
1484 }
1485
1486
1487
1488
1489 uap->port.iotype = UPIO_MEM;
1490 uap->port.irq = irq_of_parse_and_map(np, 0);
1491 uap->port.uartclk = ZS_CLOCK;
1492 uap->port.fifosize = 1;
1493 uap->port.ops = &pmz_pops;
1494 uap->port.type = PORT_PMAC_ZILOG;
1495 uap->port.flags = 0;
1496
1497
1498
1499
1500
1501
1502
1503 if (uap->port.irq == 0 &&
1504 np->parent && np->parent->parent &&
1505 of_device_is_compatible(np->parent->parent, "gatwick")) {
1506
1507 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1508 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1509 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1510 }
1511
1512
1513
1514
1515
1516 pmz_convert_to_zs(uap, CS8, 0, 9600);
1517
1518 return 0;
1519}
1520
1521
1522
1523
1524static void pmz_dispose_port(struct uart_pmac_port *uap)
1525{
1526 struct device_node *np;
1527
1528 np = uap->node;
1529 iounmap(uap->rx_dma_regs);
1530 iounmap(uap->tx_dma_regs);
1531 iounmap(uap->control_reg);
1532 uap->node = NULL;
1533 of_node_put(np);
1534 memset(uap, 0, sizeof(struct uart_pmac_port));
1535}
1536
1537
1538
1539
1540static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1541{
1542 struct uart_pmac_port *uap;
1543 int i;
1544
1545
1546
1547 for (i = 0; i < MAX_ZS_PORTS; i++)
1548 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1549 break;
1550 if (i >= MAX_ZS_PORTS)
1551 return -ENODEV;
1552
1553
1554 uap = &pmz_ports[i];
1555 uap->dev = mdev;
1556 uap->port.dev = &mdev->ofdev.dev;
1557 dev_set_drvdata(&mdev->ofdev.dev, uap);
1558
1559
1560
1561
1562 if (macio_request_resources(uap->dev, "pmac_zilog"))
1563 printk(KERN_WARNING "%pOFn: Failed to request resource"
1564 ", port still active\n",
1565 uap->node);
1566 else
1567 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1568
1569 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1570}
1571
1572
1573
1574
1575
1576static int pmz_detach(struct macio_dev *mdev)
1577{
1578 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1579
1580 if (!uap)
1581 return -ENODEV;
1582
1583 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1584
1585 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1586 macio_release_resources(uap->dev);
1587 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1588 }
1589 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1590 uap->dev = NULL;
1591 uap->port.dev = NULL;
1592
1593 return 0;
1594}
1595
1596
1597static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1598{
1599 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1600
1601 if (uap == NULL) {
1602 printk("HRM... pmz_suspend with NULL uap\n");
1603 return 0;
1604 }
1605
1606 uart_suspend_port(&pmz_uart_reg, &uap->port);
1607
1608 return 0;
1609}
1610
1611
1612static int pmz_resume(struct macio_dev *mdev)
1613{
1614 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1615
1616 if (uap == NULL)
1617 return 0;
1618
1619 uart_resume_port(&pmz_uart_reg, &uap->port);
1620
1621 return 0;
1622}
1623
1624
1625
1626
1627
1628
1629
1630static int __init pmz_probe(void)
1631{
1632 struct device_node *node_p, *node_a, *node_b, *np;
1633 int count = 0;
1634 int rc;
1635
1636
1637
1638
1639 for_each_node_by_name(node_p, "escc") {
1640
1641
1642
1643
1644
1645 node_a = node_b = NULL;
1646 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1647 if (of_node_name_prefix(np, "ch-a"))
1648 node_a = of_node_get(np);
1649 else if (of_node_name_prefix(np, "ch-b"))
1650 node_b = of_node_get(np);
1651 }
1652 if (!node_a && !node_b) {
1653 of_node_put(node_a);
1654 of_node_put(node_b);
1655 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1656 (!node_a) ? 'a' : 'b', node_p);
1657 continue;
1658 }
1659
1660
1661
1662
1663 if (node_b != NULL) {
1664 pmz_ports[count].mate = &pmz_ports[count+1];
1665 pmz_ports[count+1].mate = &pmz_ports[count];
1666 }
1667 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1668 pmz_ports[count].node = node_a;
1669 pmz_ports[count+1].node = node_b;
1670 pmz_ports[count].port.line = count;
1671 pmz_ports[count+1].port.line = count+1;
1672
1673
1674
1675
1676 rc = pmz_init_port(&pmz_ports[count]);
1677 if (rc == 0 && node_b != NULL)
1678 rc = pmz_init_port(&pmz_ports[count+1]);
1679 if (rc != 0) {
1680 of_node_put(node_a);
1681 of_node_put(node_b);
1682 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1683 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1684 continue;
1685 }
1686 count += 2;
1687 }
1688 pmz_ports_count = count;
1689
1690 return 0;
1691}
1692
1693#else
1694
1695extern struct platform_device scc_a_pdev, scc_b_pdev;
1696
1697static int __init pmz_init_port(struct uart_pmac_port *uap)
1698{
1699 struct resource *r_ports;
1700 int irq;
1701
1702 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1703 irq = platform_get_irq(uap->pdev, 0);
1704 if (!r_ports || irq <= 0)
1705 return -ENODEV;
1706
1707 uap->port.mapbase = r_ports->start;
1708 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1709 uap->port.iotype = UPIO_MEM;
1710 uap->port.irq = irq;
1711 uap->port.uartclk = ZS_CLOCK;
1712 uap->port.fifosize = 1;
1713 uap->port.ops = &pmz_pops;
1714 uap->port.type = PORT_PMAC_ZILOG;
1715 uap->port.flags = 0;
1716
1717 uap->control_reg = uap->port.membase;
1718 uap->data_reg = uap->control_reg + 4;
1719 uap->port_type = 0;
1720 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1721
1722 pmz_convert_to_zs(uap, CS8, 0, 9600);
1723
1724 return 0;
1725}
1726
1727static int __init pmz_probe(void)
1728{
1729 int err;
1730
1731 pmz_ports_count = 0;
1732
1733 pmz_ports[0].port.line = 0;
1734 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1735 pmz_ports[0].pdev = &scc_a_pdev;
1736 err = pmz_init_port(&pmz_ports[0]);
1737 if (err)
1738 return err;
1739 pmz_ports_count++;
1740
1741 pmz_ports[0].mate = &pmz_ports[1];
1742 pmz_ports[1].mate = &pmz_ports[0];
1743 pmz_ports[1].port.line = 1;
1744 pmz_ports[1].flags = 0;
1745 pmz_ports[1].pdev = &scc_b_pdev;
1746 err = pmz_init_port(&pmz_ports[1]);
1747 if (err)
1748 return err;
1749 pmz_ports_count++;
1750
1751 return 0;
1752}
1753
1754static void pmz_dispose_port(struct uart_pmac_port *uap)
1755{
1756 memset(uap, 0, sizeof(struct uart_pmac_port));
1757}
1758
1759static int __init pmz_attach(struct platform_device *pdev)
1760{
1761 struct uart_pmac_port *uap;
1762 int i;
1763
1764
1765 for (i = 0; i < pmz_ports_count; i++)
1766 if (pmz_ports[i].pdev == pdev)
1767 break;
1768 if (i >= pmz_ports_count)
1769 return -ENODEV;
1770
1771 uap = &pmz_ports[i];
1772 uap->port.dev = &pdev->dev;
1773 platform_set_drvdata(pdev, uap);
1774
1775 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1776}
1777
1778static int __exit pmz_detach(struct platform_device *pdev)
1779{
1780 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1781
1782 if (!uap)
1783 return -ENODEV;
1784
1785 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1786
1787 uap->port.dev = NULL;
1788
1789 return 0;
1790}
1791
1792#endif
1793
1794#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1795
1796static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1797static int __init pmz_console_setup(struct console *co, char *options);
1798
1799static struct console pmz_console = {
1800 .name = PMACZILOG_NAME,
1801 .write = pmz_console_write,
1802 .device = uart_console_device,
1803 .setup = pmz_console_setup,
1804 .flags = CON_PRINTBUFFER,
1805 .index = -1,
1806 .data = &pmz_uart_reg,
1807};
1808
1809#define PMACZILOG_CONSOLE &pmz_console
1810#else
1811#define PMACZILOG_CONSOLE (NULL)
1812#endif
1813
1814
1815
1816
1817
1818static int __init pmz_register(void)
1819{
1820 pmz_uart_reg.nr = pmz_ports_count;
1821 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1822
1823
1824
1825
1826 return uart_register_driver(&pmz_uart_reg);
1827}
1828
1829#ifdef CONFIG_PPC_PMAC
1830
1831static const struct of_device_id pmz_match[] =
1832{
1833 {
1834 .name = "ch-a",
1835 },
1836 {
1837 .name = "ch-b",
1838 },
1839 {},
1840};
1841MODULE_DEVICE_TABLE (of, pmz_match);
1842
1843static struct macio_driver pmz_driver = {
1844 .driver = {
1845 .name = "pmac_zilog",
1846 .owner = THIS_MODULE,
1847 .of_match_table = pmz_match,
1848 },
1849 .probe = pmz_attach,
1850 .remove = pmz_detach,
1851 .suspend = pmz_suspend,
1852 .resume = pmz_resume,
1853};
1854
1855#else
1856
1857static struct platform_driver pmz_driver = {
1858 .remove = __exit_p(pmz_detach),
1859 .driver = {
1860 .name = "scc",
1861 },
1862};
1863
1864#endif
1865
1866static int __init init_pmz(void)
1867{
1868 int rc, i;
1869 printk(KERN_INFO "%s\n", version);
1870
1871
1872
1873
1874
1875
1876
1877
1878 if (pmz_ports_count == 0)
1879 pmz_probe();
1880
1881
1882
1883
1884 if (pmz_ports_count == 0)
1885 return -ENODEV;
1886
1887
1888
1889
1890 rc = pmz_register();
1891 if (rc) {
1892 printk(KERN_ERR
1893 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1894 "pmac_zilog: Did another serial driver already claim the minors?\n");
1895
1896 for (i=0; i < pmz_ports_count; i++)
1897 pmz_dispose_port(&pmz_ports[i]);
1898 return rc;
1899 }
1900
1901
1902
1903
1904#ifdef CONFIG_PPC_PMAC
1905 return macio_register_driver(&pmz_driver);
1906#else
1907 return platform_driver_probe(&pmz_driver, pmz_attach);
1908#endif
1909}
1910
1911static void __exit exit_pmz(void)
1912{
1913 int i;
1914
1915#ifdef CONFIG_PPC_PMAC
1916
1917 macio_unregister_driver(&pmz_driver);
1918#else
1919 platform_driver_unregister(&pmz_driver);
1920#endif
1921
1922 for (i = 0; i < pmz_ports_count; i++) {
1923 struct uart_pmac_port *uport = &pmz_ports[i];
1924#ifdef CONFIG_PPC_PMAC
1925 if (uport->node != NULL)
1926 pmz_dispose_port(uport);
1927#else
1928 if (uport->pdev != NULL)
1929 pmz_dispose_port(uport);
1930#endif
1931 }
1932
1933 uart_unregister_driver(&pmz_uart_reg);
1934}
1935
1936#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1937
1938static void pmz_console_putchar(struct uart_port *port, int ch)
1939{
1940 struct uart_pmac_port *uap =
1941 container_of(port, struct uart_pmac_port, port);
1942
1943
1944 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1945 udelay(5);
1946 write_zsdata(uap, ch);
1947}
1948
1949
1950
1951
1952
1953static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1954{
1955 struct uart_pmac_port *uap = &pmz_ports[con->index];
1956 unsigned long flags;
1957
1958 spin_lock_irqsave(&uap->port.lock, flags);
1959
1960
1961 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1962 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1963
1964 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1965
1966
1967 write_zsreg(uap, R1, uap->curregs[1]);
1968
1969
1970 spin_unlock_irqrestore(&uap->port.lock, flags);
1971}
1972
1973
1974
1975
1976static int __init pmz_console_setup(struct console *co, char *options)
1977{
1978 struct uart_pmac_port *uap;
1979 struct uart_port *port;
1980 int baud = 38400;
1981 int bits = 8;
1982 int parity = 'n';
1983 int flow = 'n';
1984 unsigned long pwr_delay;
1985
1986
1987
1988
1989 if (of_machine_is_compatible("RackMac1,1")
1990 || of_machine_is_compatible("RackMac1,2")
1991 || of_machine_is_compatible("MacRISC4"))
1992 baud = 57600;
1993
1994
1995
1996
1997
1998
1999 if (co->index >= pmz_ports_count)
2000 co->index = 0;
2001 uap = &pmz_ports[co->index];
2002#ifdef CONFIG_PPC_PMAC
2003 if (uap->node == NULL)
2004 return -ENODEV;
2005#else
2006 if (uap->pdev == NULL)
2007 return -ENODEV;
2008#endif
2009 port = &uap->port;
2010
2011
2012
2013
2014 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2015
2016
2017
2018
2019 spin_lock_init(&port->lock);
2020
2021
2022
2023
2024 pwr_delay = __pmz_startup(uap);
2025 if (pwr_delay)
2026 mdelay(pwr_delay);
2027
2028 if (options)
2029 uart_parse_options(options, &baud, &parity, &bits, &flow);
2030
2031 return uart_set_options(port, co, baud, parity, bits, flow);
2032}
2033
2034static int __init pmz_console_init(void)
2035{
2036
2037 pmz_probe();
2038
2039 if (pmz_ports_count == 0)
2040 return -ENODEV;
2041
2042
2043
2044 register_console(&pmz_console);
2045
2046 return 0;
2047
2048}
2049console_initcall(pmz_console_init);
2050#endif
2051
2052module_init(init_pmz);
2053module_exit(exit_pmz);
2054