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43#include <linux/delay.h>
44#include <linux/device.h>
45#include <linux/dma-mapping.h>
46#include <linux/extcon.h>
47#include <linux/phy/phy.h>
48#include <linux/platform_device.h>
49#include <linux/module.h>
50#include <linux/idr.h>
51#include <linux/interrupt.h>
52#include <linux/io.h>
53#include <linux/kernel.h>
54#include <linux/slab.h>
55#include <linux/pm_runtime.h>
56#include <linux/pinctrl/consumer.h>
57#include <linux/usb/ch9.h>
58#include <linux/usb/gadget.h>
59#include <linux/usb/otg.h>
60#include <linux/usb/chipidea.h>
61#include <linux/usb/of.h>
62#include <linux/of.h>
63#include <linux/regulator/consumer.h>
64#include <linux/usb/ehci_def.h>
65
66#include "ci.h"
67#include "udc.h"
68#include "bits.h"
69#include "host.h"
70#include "otg.h"
71#include "otg_fsm.h"
72
73
74static const u8 ci_regs_nolpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0x38U,
79 [OP_USBCMD] = 0x00U,
80 [OP_USBSTS] = 0x04U,
81 [OP_USBINTR] = 0x08U,
82 [OP_DEVICEADDR] = 0x14U,
83 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_TTCTRL] = 0x1CU,
85 [OP_BURSTSIZE] = 0x20U,
86 [OP_ULPI_VIEWPORT] = 0x30U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
97};
98
99static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_TTCTRL] = 0x1CU,
110 [OP_BURSTSIZE] = 0x20U,
111 [OP_ULPI_VIEWPORT] = 0x30U,
112 [OP_PORTSC] = 0x44U,
113 [OP_DEVLC] = 0x84U,
114 [OP_OTGSC] = 0xC4U,
115 [OP_USBMODE] = 0xC8U,
116 [OP_ENDPTSETUPSTAT] = 0xD8U,
117 [OP_ENDPTPRIME] = 0xDCU,
118 [OP_ENDPTFLUSH] = 0xE0U,
119 [OP_ENDPTSTAT] = 0xE4U,
120 [OP_ENDPTCOMPLETE] = 0xE8U,
121 [OP_ENDPTCTRL] = 0xECU,
122};
123
124static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
125{
126 int i;
127
128 for (i = 0; i < OP_ENDPTCTRL; i++)
129 ci->hw_bank.regmap[i] =
130 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
131 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132
133 for (; i <= OP_LAST; i++)
134 ci->hw_bank.regmap[i] = ci->hw_bank.op +
135 4 * (i - OP_ENDPTCTRL) +
136 (is_lpm
137 ? ci_regs_lpm[OP_ENDPTCTRL]
138 : ci_regs_nolpm[OP_ENDPTCTRL]);
139
140}
141
142static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143{
144 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
145 enum ci_revision rev = CI_REVISION_UNKNOWN;
146
147 if (ver == 0x2) {
148 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 >> __ffs(REVISION);
150 rev += CI_REVISION_20;
151 } else if (ver == 0x0) {
152 rev = CI_REVISION_1X;
153 }
154
155 return rev;
156}
157
158
159
160
161
162
163
164
165u32 hw_read_intr_enable(struct ci_hdrc *ci)
166{
167 return hw_read(ci, OP_USBINTR, ~0);
168}
169
170
171
172
173
174
175
176
177u32 hw_read_intr_status(struct ci_hdrc *ci)
178{
179 return hw_read(ci, OP_USBSTS, ~0);
180}
181
182
183
184
185
186
187
188int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189{
190 const u8 TEST_MODE_MAX = 7;
191
192 if (mode > TEST_MODE_MAX)
193 return -EINVAL;
194
195 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
196 return 0;
197}
198
199
200
201
202
203
204
205
206u8 hw_port_test_get(struct ci_hdrc *ci)
207{
208 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
209}
210
211static void hw_wait_phy_stable(void)
212{
213
214
215
216
217
218
219 usleep_range(2000, 2500);
220}
221
222
223static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224{
225 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
226 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
227
228 if (enable && !lpm)
229 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
230 PORTSC_PHCD(ci->hw_bank.lpm));
231 else if (!enable && lpm)
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 0);
234}
235
236static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
237{
238 u32 reg;
239
240
241 ci->hw_bank.abs = base;
242
243 ci->hw_bank.cap = ci->hw_bank.abs;
244 ci->hw_bank.cap += ci->platdata->capoffset;
245 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246
247 hw_alloc_regmap(ci, false);
248 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
249 __ffs(HCCPARAMS_LEN);
250 ci->hw_bank.lpm = reg;
251 if (reg)
252 hw_alloc_regmap(ci, !!reg);
253 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
254 ci->hw_bank.size += OP_LAST;
255 ci->hw_bank.size /= sizeof(u32);
256
257 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
258 __ffs(DCCPARAMS_DEN);
259 ci->hw_ep_max = reg * 2;
260
261 if (ci->hw_ep_max > ENDPT_MAX)
262 return -ENODEV;
263
264 ci_hdrc_enter_lpm(ci, false);
265
266
267 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268
269
270 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271
272 ci->rev = ci_get_revision(ci);
273
274 dev_dbg(ci->dev,
275 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
276 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277
278
279
280
281
282
283
284 return 0;
285}
286
287void hw_phymode_configure(struct ci_hdrc *ci)
288{
289 u32 portsc, lpm, sts = 0;
290
291 switch (ci->platdata->phy_mode) {
292 case USBPHY_INTERFACE_MODE_UTMI:
293 portsc = PORTSC_PTS(PTS_UTMI);
294 lpm = DEVLC_PTS(PTS_UTMI);
295 break;
296 case USBPHY_INTERFACE_MODE_UTMIW:
297 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
298 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 break;
300 case USBPHY_INTERFACE_MODE_ULPI:
301 portsc = PORTSC_PTS(PTS_ULPI);
302 lpm = DEVLC_PTS(PTS_ULPI);
303 break;
304 case USBPHY_INTERFACE_MODE_SERIAL:
305 portsc = PORTSC_PTS(PTS_SERIAL);
306 lpm = DEVLC_PTS(PTS_SERIAL);
307 sts = 1;
308 break;
309 case USBPHY_INTERFACE_MODE_HSIC:
310 portsc = PORTSC_PTS(PTS_HSIC);
311 lpm = DEVLC_PTS(PTS_HSIC);
312 break;
313 default:
314 return;
315 }
316
317 if (ci->hw_bank.lpm) {
318 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 if (sts)
320 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 } else {
322 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 if (sts)
324 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
325 }
326}
327EXPORT_SYMBOL_GPL(hw_phymode_configure);
328
329
330
331
332
333
334
335
336static int _ci_usb_phy_init(struct ci_hdrc *ci)
337{
338 int ret;
339
340 if (ci->phy) {
341 ret = phy_init(ci->phy);
342 if (ret)
343 return ret;
344
345 ret = phy_power_on(ci->phy);
346 if (ret) {
347 phy_exit(ci->phy);
348 return ret;
349 }
350 } else {
351 ret = usb_phy_init(ci->usb_phy);
352 }
353
354 return ret;
355}
356
357
358
359
360
361
362static void ci_usb_phy_exit(struct ci_hdrc *ci)
363{
364 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
365 return;
366
367 if (ci->phy) {
368 phy_power_off(ci->phy);
369 phy_exit(ci->phy);
370 } else {
371 usb_phy_shutdown(ci->usb_phy);
372 }
373}
374
375
376
377
378
379
380
381static int ci_usb_phy_init(struct ci_hdrc *ci)
382{
383 int ret;
384
385 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
386 return 0;
387
388 switch (ci->platdata->phy_mode) {
389 case USBPHY_INTERFACE_MODE_UTMI:
390 case USBPHY_INTERFACE_MODE_UTMIW:
391 case USBPHY_INTERFACE_MODE_HSIC:
392 ret = _ci_usb_phy_init(ci);
393 if (!ret)
394 hw_wait_phy_stable();
395 else
396 return ret;
397 hw_phymode_configure(ci);
398 break;
399 case USBPHY_INTERFACE_MODE_ULPI:
400 case USBPHY_INTERFACE_MODE_SERIAL:
401 hw_phymode_configure(ci);
402 ret = _ci_usb_phy_init(ci);
403 if (ret)
404 return ret;
405 break;
406 default:
407 ret = _ci_usb_phy_init(ci);
408 if (!ret)
409 hw_wait_phy_stable();
410 }
411
412 return ret;
413}
414
415
416
417
418
419
420
421void ci_platform_configure(struct ci_hdrc *ci)
422{
423 bool is_device_mode, is_host_mode;
424
425 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
426 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427
428 if (is_device_mode) {
429 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430
431 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
433 USBMODE_CI_SDIS);
434 }
435
436 if (is_host_mode) {
437 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438
439 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
440 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
441 USBMODE_CI_SDIS);
442 }
443
444 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 if (ci->hw_bank.lpm)
446 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 else
448 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
449 }
450
451 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
452 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453
454 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455
456 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
457 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
458 ci->platdata->ahb_burst_config);
459
460
461 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
462 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
463 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
464 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465
466 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
467 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
468 ci->platdata->rx_burst_size);
469 }
470}
471
472
473
474
475
476
477
478static int hw_controller_reset(struct ci_hdrc *ci)
479{
480 int count = 0;
481
482 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
483 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
484 udelay(10);
485 if (count++ > 1000)
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490}
491
492
493
494
495
496
497
498int hw_device_reset(struct ci_hdrc *ci)
499{
500 int ret;
501
502
503 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
504 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505
506 ret = hw_controller_reset(ci);
507 if (ret) {
508 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
509 return ret;
510 }
511
512 if (ci->platdata->notify_event) {
513 ret = ci->platdata->notify_event(ci,
514 CI_HDRC_CONTROLLER_RESET_EVENT);
515 if (ret)
516 return ret;
517 }
518
519
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
521 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522
523 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524
525 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
526 dev_err(ci->dev, "cannot enter in %s device mode\n",
527 ci_role(ci)->name);
528 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
529 return -ENODEV;
530 }
531
532 ci_platform_configure(ci);
533
534 return 0;
535}
536
537static irqreturn_t ci_irq(int irq, void *data)
538{
539 struct ci_hdrc *ci = data;
540 irqreturn_t ret = IRQ_NONE;
541 u32 otgsc = 0;
542
543 if (ci->in_lpm) {
544 disable_irq_nosync(irq);
545 ci->wakeup_int = true;
546 pm_runtime_get(ci->dev);
547 return IRQ_HANDLED;
548 }
549
550 if (ci->is_otg) {
551 otgsc = hw_read_otgsc(ci, ~0);
552 if (ci_otg_is_fsm_mode(ci)) {
553 ret = ci_otg_fsm_irq(ci);
554 if (ret == IRQ_HANDLED)
555 return ret;
556 }
557 }
558
559
560
561
562
563 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
564 ci->id_event = true;
565
566 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
567 ci_otg_queue_work(ci);
568 return IRQ_HANDLED;
569 }
570
571
572
573
574
575 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
576 ci->b_sess_valid_event = true;
577
578 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
579 ci_otg_queue_work(ci);
580 return IRQ_HANDLED;
581 }
582
583
584 if (ci->role != CI_ROLE_END)
585 ret = ci_role(ci)->irq(ci);
586
587 return ret;
588}
589
590static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
591 void *ptr)
592{
593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
594 struct ci_hdrc *ci = cbl->ci;
595
596 cbl->connected = event;
597 cbl->changed = true;
598
599 ci_irq(ci->irq, ci);
600 return NOTIFY_DONE;
601}
602
603static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
604{
605 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
606 enum usb_role role;
607 unsigned long flags;
608
609 spin_lock_irqsave(&ci->lock, flags);
610 role = ci_role_to_usb_role(ci);
611 spin_unlock_irqrestore(&ci->lock, flags);
612
613 return role;
614}
615
616static int ci_usb_role_switch_set(struct usb_role_switch *sw,
617 enum usb_role role)
618{
619 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
620 struct ci_hdrc_cable *cable = NULL;
621 enum usb_role current_role = ci_role_to_usb_role(ci);
622 enum ci_role ci_role = usb_role_to_ci_role(role);
623 unsigned long flags;
624
625 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
626 (current_role == role))
627 return 0;
628
629 pm_runtime_get_sync(ci->dev);
630
631 spin_lock_irqsave(&ci->lock, flags);
632 if (current_role == USB_ROLE_DEVICE)
633 cable = &ci->platdata->vbus_extcon;
634 else if (current_role == USB_ROLE_HOST)
635 cable = &ci->platdata->id_extcon;
636
637 if (cable) {
638 cable->changed = true;
639 cable->connected = false;
640 ci_irq(ci->irq, ci);
641 spin_unlock_irqrestore(&ci->lock, flags);
642 if (ci->wq && role != USB_ROLE_NONE)
643 flush_workqueue(ci->wq);
644 spin_lock_irqsave(&ci->lock, flags);
645 }
646
647 cable = NULL;
648
649
650 if (role == USB_ROLE_DEVICE)
651 cable = &ci->platdata->vbus_extcon;
652 else if (role == USB_ROLE_HOST)
653 cable = &ci->platdata->id_extcon;
654
655 if (cable) {
656 cable->changed = true;
657 cable->connected = true;
658 ci_irq(ci->irq, ci);
659 }
660 spin_unlock_irqrestore(&ci->lock, flags);
661 pm_runtime_put_sync(ci->dev);
662
663 return 0;
664}
665
666static struct usb_role_switch_desc ci_role_switch = {
667 .set = ci_usb_role_switch_set,
668 .get = ci_usb_role_switch_get,
669};
670
671static int ci_get_platdata(struct device *dev,
672 struct ci_hdrc_platform_data *platdata)
673{
674 struct extcon_dev *ext_vbus, *ext_id;
675 struct ci_hdrc_cable *cable;
676 int ret;
677
678 if (!platdata->phy_mode)
679 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
680
681 if (!platdata->dr_mode)
682 platdata->dr_mode = usb_get_dr_mode(dev);
683
684 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
685 platdata->dr_mode = USB_DR_MODE_OTG;
686
687 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
688
689 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
690 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
691 return -EPROBE_DEFER;
692 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
693
694 platdata->reg_vbus = NULL;
695 } else if (IS_ERR(platdata->reg_vbus)) {
696 dev_err(dev, "Getting regulator error: %ld\n",
697 PTR_ERR(platdata->reg_vbus));
698 return PTR_ERR(platdata->reg_vbus);
699 }
700
701 if (!platdata->tpl_support)
702 platdata->tpl_support =
703 of_usb_host_tpl_support(dev->of_node);
704 }
705
706 if (platdata->dr_mode == USB_DR_MODE_OTG) {
707
708 platdata->ci_otg_caps.otg_rev = 0x0200;
709 platdata->ci_otg_caps.hnp_support = true;
710 platdata->ci_otg_caps.srp_support = true;
711
712
713 ret = of_usb_update_otg_caps(dev->of_node,
714 &platdata->ci_otg_caps);
715 if (ret)
716 return ret;
717 }
718
719 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
720 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
721
722 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
723 &platdata->phy_clkgate_delay_us);
724
725 platdata->itc_setting = 1;
726
727 of_property_read_u32(dev->of_node, "itc-setting",
728 &platdata->itc_setting);
729
730 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
731 &platdata->ahb_burst_config);
732 if (!ret) {
733 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
734 } else if (ret != -EINVAL) {
735 dev_err(dev, "failed to get ahb-burst-config\n");
736 return ret;
737 }
738
739 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
740 &platdata->tx_burst_size);
741 if (!ret) {
742 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
743 } else if (ret != -EINVAL) {
744 dev_err(dev, "failed to get tx-burst-size-dword\n");
745 return ret;
746 }
747
748 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
749 &platdata->rx_burst_size);
750 if (!ret) {
751 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
752 } else if (ret != -EINVAL) {
753 dev_err(dev, "failed to get rx-burst-size-dword\n");
754 return ret;
755 }
756
757 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
758 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
759
760 ext_id = ERR_PTR(-ENODEV);
761 ext_vbus = ERR_PTR(-ENODEV);
762 if (of_property_read_bool(dev->of_node, "extcon")) {
763
764 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
765 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
766 return PTR_ERR(ext_vbus);
767
768 ext_id = extcon_get_edev_by_phandle(dev, 1);
769 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
770 return PTR_ERR(ext_id);
771 }
772
773 cable = &platdata->vbus_extcon;
774 cable->nb.notifier_call = ci_cable_notifier;
775 cable->edev = ext_vbus;
776
777 if (!IS_ERR(ext_vbus)) {
778 ret = extcon_get_state(cable->edev, EXTCON_USB);
779 if (ret)
780 cable->connected = true;
781 else
782 cable->connected = false;
783 }
784
785 cable = &platdata->id_extcon;
786 cable->nb.notifier_call = ci_cable_notifier;
787 cable->edev = ext_id;
788
789 if (!IS_ERR(ext_id)) {
790 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
791 if (ret)
792 cable->connected = true;
793 else
794 cable->connected = false;
795 }
796
797 if (device_property_read_bool(dev, "usb-role-switch"))
798 ci_role_switch.fwnode = dev->fwnode;
799
800 platdata->pctl = devm_pinctrl_get(dev);
801 if (!IS_ERR(platdata->pctl)) {
802 struct pinctrl_state *p;
803
804 p = pinctrl_lookup_state(platdata->pctl, "default");
805 if (!IS_ERR(p))
806 platdata->pins_default = p;
807
808 p = pinctrl_lookup_state(platdata->pctl, "host");
809 if (!IS_ERR(p))
810 platdata->pins_host = p;
811
812 p = pinctrl_lookup_state(platdata->pctl, "device");
813 if (!IS_ERR(p))
814 platdata->pins_device = p;
815 }
816
817 return 0;
818}
819
820static int ci_extcon_register(struct ci_hdrc *ci)
821{
822 struct ci_hdrc_cable *id, *vbus;
823 int ret;
824
825 id = &ci->platdata->id_extcon;
826 id->ci = ci;
827 if (!IS_ERR_OR_NULL(id->edev)) {
828 ret = devm_extcon_register_notifier(ci->dev, id->edev,
829 EXTCON_USB_HOST, &id->nb);
830 if (ret < 0) {
831 dev_err(ci->dev, "register ID failed\n");
832 return ret;
833 }
834 }
835
836 vbus = &ci->platdata->vbus_extcon;
837 vbus->ci = ci;
838 if (!IS_ERR_OR_NULL(vbus->edev)) {
839 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
840 EXTCON_USB, &vbus->nb);
841 if (ret < 0) {
842 dev_err(ci->dev, "register VBUS failed\n");
843 return ret;
844 }
845 }
846
847 return 0;
848}
849
850static DEFINE_IDA(ci_ida);
851
852struct platform_device *ci_hdrc_add_device(struct device *dev,
853 struct resource *res, int nres,
854 struct ci_hdrc_platform_data *platdata)
855{
856 struct platform_device *pdev;
857 int id, ret;
858
859 ret = ci_get_platdata(dev, platdata);
860 if (ret)
861 return ERR_PTR(ret);
862
863 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
864 if (id < 0)
865 return ERR_PTR(id);
866
867 pdev = platform_device_alloc("ci_hdrc", id);
868 if (!pdev) {
869 ret = -ENOMEM;
870 goto put_id;
871 }
872
873 pdev->dev.parent = dev;
874
875 ret = platform_device_add_resources(pdev, res, nres);
876 if (ret)
877 goto err;
878
879 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
880 if (ret)
881 goto err;
882
883 ret = platform_device_add(pdev);
884 if (ret)
885 goto err;
886
887 return pdev;
888
889err:
890 platform_device_put(pdev);
891put_id:
892 ida_simple_remove(&ci_ida, id);
893 return ERR_PTR(ret);
894}
895EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
896
897void ci_hdrc_remove_device(struct platform_device *pdev)
898{
899 int id = pdev->id;
900 platform_device_unregister(pdev);
901 ida_simple_remove(&ci_ida, id);
902}
903EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
904
905static inline void ci_role_destroy(struct ci_hdrc *ci)
906{
907 ci_hdrc_gadget_destroy(ci);
908 ci_hdrc_host_destroy(ci);
909 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
910 ci_hdrc_otg_destroy(ci);
911}
912
913static void ci_get_otg_capable(struct ci_hdrc *ci)
914{
915 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
916 ci->is_otg = false;
917 else
918 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
919 DCCPARAMS_DC | DCCPARAMS_HC)
920 == (DCCPARAMS_DC | DCCPARAMS_HC));
921 if (ci->is_otg) {
922 dev_dbg(ci->dev, "It is OTG capable controller\n");
923
924 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
925 OTGSC_INT_STATUS_BITS);
926 }
927}
928
929static ssize_t role_show(struct device *dev, struct device_attribute *attr,
930 char *buf)
931{
932 struct ci_hdrc *ci = dev_get_drvdata(dev);
933
934 if (ci->role != CI_ROLE_END)
935 return sprintf(buf, "%s\n", ci_role(ci)->name);
936
937 return 0;
938}
939
940static ssize_t role_store(struct device *dev,
941 struct device_attribute *attr, const char *buf, size_t n)
942{
943 struct ci_hdrc *ci = dev_get_drvdata(dev);
944 enum ci_role role;
945 int ret;
946
947 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
948 dev_warn(dev, "Current configuration is not dual-role, quit\n");
949 return -EPERM;
950 }
951
952 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
953 if (!strncmp(buf, ci->roles[role]->name,
954 strlen(ci->roles[role]->name)))
955 break;
956
957 if (role == CI_ROLE_END || role == ci->role)
958 return -EINVAL;
959
960 pm_runtime_get_sync(dev);
961 disable_irq(ci->irq);
962 ci_role_stop(ci);
963 ret = ci_role_start(ci, role);
964 if (!ret && ci->role == CI_ROLE_GADGET)
965 ci_handle_vbus_change(ci);
966 enable_irq(ci->irq);
967 pm_runtime_put_sync(dev);
968
969 return (ret == 0) ? n : ret;
970}
971static DEVICE_ATTR_RW(role);
972
973static struct attribute *ci_attrs[] = {
974 &dev_attr_role.attr,
975 NULL,
976};
977ATTRIBUTE_GROUPS(ci);
978
979static int ci_hdrc_probe(struct platform_device *pdev)
980{
981 struct device *dev = &pdev->dev;
982 struct ci_hdrc *ci;
983 struct resource *res;
984 void __iomem *base;
985 int ret;
986 enum usb_dr_mode dr_mode;
987
988 if (!dev_get_platdata(dev)) {
989 dev_err(dev, "platform data missing\n");
990 return -ENODEV;
991 }
992
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 base = devm_ioremap_resource(dev, res);
995 if (IS_ERR(base))
996 return PTR_ERR(base);
997
998 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
999 if (!ci)
1000 return -ENOMEM;
1001
1002 spin_lock_init(&ci->lock);
1003 ci->dev = dev;
1004 ci->platdata = dev_get_platdata(dev);
1005 ci->imx28_write_fix = !!(ci->platdata->flags &
1006 CI_HDRC_IMX28_WRITE_FIX);
1007 ci->supports_runtime_pm = !!(ci->platdata->flags &
1008 CI_HDRC_SUPPORTS_RUNTIME_PM);
1009 platform_set_drvdata(pdev, ci);
1010
1011 ret = hw_device_init(ci, base);
1012 if (ret < 0) {
1013 dev_err(dev, "can't initialize hardware\n");
1014 return -ENODEV;
1015 }
1016
1017 ret = ci_ulpi_init(ci);
1018 if (ret)
1019 return ret;
1020
1021 if (ci->platdata->phy) {
1022 ci->phy = ci->platdata->phy;
1023 } else if (ci->platdata->usb_phy) {
1024 ci->usb_phy = ci->platdata->usb_phy;
1025 } else {
1026
1027 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1028
1029 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1030 ret = -EPROBE_DEFER;
1031 goto ulpi_exit;
1032 } else if (IS_ERR(ci->phy)) {
1033 ci->phy = NULL;
1034 }
1035
1036
1037 if (!ci->phy) {
1038 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1039 "phys", 0);
1040
1041 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1042 ret = -EPROBE_DEFER;
1043 goto ulpi_exit;
1044 } else if (IS_ERR(ci->usb_phy)) {
1045 ci->usb_phy = NULL;
1046 }
1047 }
1048
1049
1050 if (!ci->phy && !ci->usb_phy) {
1051 ci->usb_phy = devm_usb_get_phy(dev->parent,
1052 USB_PHY_TYPE_USB2);
1053
1054 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1055 ret = -EPROBE_DEFER;
1056 goto ulpi_exit;
1057 } else if (IS_ERR(ci->usb_phy)) {
1058 ci->usb_phy = NULL;
1059 }
1060 }
1061
1062
1063 if (!ci->phy && !ci->usb_phy) {
1064 ret = -ENXIO;
1065 goto ulpi_exit;
1066 }
1067 }
1068
1069 ret = ci_usb_phy_init(ci);
1070 if (ret) {
1071 dev_err(dev, "unable to init phy: %d\n", ret);
1072 return ret;
1073 }
1074
1075 ci->hw_bank.phys = res->start;
1076
1077 ci->irq = platform_get_irq(pdev, 0);
1078 if (ci->irq < 0) {
1079 ret = ci->irq;
1080 goto deinit_phy;
1081 }
1082
1083 ci_get_otg_capable(ci);
1084
1085 dr_mode = ci->platdata->dr_mode;
1086
1087 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1088 ret = ci_hdrc_host_init(ci);
1089 if (ret) {
1090 if (ret == -ENXIO)
1091 dev_info(dev, "doesn't support host\n");
1092 else
1093 goto deinit_phy;
1094 }
1095 }
1096
1097 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1098 ret = ci_hdrc_gadget_init(ci);
1099 if (ret) {
1100 if (ret == -ENXIO)
1101 dev_info(dev, "doesn't support gadget\n");
1102 else
1103 goto deinit_host;
1104 }
1105 }
1106
1107 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1108 dev_err(dev, "no supported roles\n");
1109 ret = -ENODEV;
1110 goto deinit_gadget;
1111 }
1112
1113 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1114 ret = ci_hdrc_otg_init(ci);
1115 if (ret) {
1116 dev_err(dev, "init otg fails, ret = %d\n", ret);
1117 goto deinit_gadget;
1118 }
1119 }
1120
1121 if (ci_role_switch.fwnode) {
1122 ci_role_switch.driver_data = ci;
1123 ci->role_switch = usb_role_switch_register(dev,
1124 &ci_role_switch);
1125 if (IS_ERR(ci->role_switch)) {
1126 ret = PTR_ERR(ci->role_switch);
1127 goto deinit_otg;
1128 }
1129 }
1130
1131 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1132 if (ci->is_otg) {
1133 ci->role = ci_otg_role(ci);
1134
1135 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1136 } else {
1137
1138
1139
1140
1141
1142 ci->role = CI_ROLE_GADGET;
1143 }
1144 } else {
1145 ci->role = ci->roles[CI_ROLE_HOST]
1146 ? CI_ROLE_HOST
1147 : CI_ROLE_GADGET;
1148 }
1149
1150 if (!ci_otg_is_fsm_mode(ci)) {
1151
1152 if (ci->role == CI_ROLE_GADGET)
1153 ci_handle_vbus_change(ci);
1154
1155 ret = ci_role_start(ci, ci->role);
1156 if (ret) {
1157 dev_err(dev, "can't start %s role\n",
1158 ci_role(ci)->name);
1159 goto stop;
1160 }
1161 }
1162
1163 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1164 ci->platdata->name, ci);
1165 if (ret)
1166 goto stop;
1167
1168 ret = ci_extcon_register(ci);
1169 if (ret)
1170 goto stop;
1171
1172 if (ci->supports_runtime_pm) {
1173 pm_runtime_set_active(&pdev->dev);
1174 pm_runtime_enable(&pdev->dev);
1175 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1176 pm_runtime_mark_last_busy(ci->dev);
1177 pm_runtime_use_autosuspend(&pdev->dev);
1178 }
1179
1180 if (ci_otg_is_fsm_mode(ci))
1181 ci_hdrc_otg_fsm_start(ci);
1182
1183 device_set_wakeup_capable(&pdev->dev, true);
1184 dbg_create_files(ci);
1185
1186 return 0;
1187
1188stop:
1189 if (ci->role_switch)
1190 usb_role_switch_unregister(ci->role_switch);
1191deinit_otg:
1192 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1193 ci_hdrc_otg_destroy(ci);
1194deinit_gadget:
1195 ci_hdrc_gadget_destroy(ci);
1196deinit_host:
1197 ci_hdrc_host_destroy(ci);
1198deinit_phy:
1199 ci_usb_phy_exit(ci);
1200ulpi_exit:
1201 ci_ulpi_exit(ci);
1202
1203 return ret;
1204}
1205
1206static int ci_hdrc_remove(struct platform_device *pdev)
1207{
1208 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1209
1210 if (ci->role_switch)
1211 usb_role_switch_unregister(ci->role_switch);
1212
1213 if (ci->supports_runtime_pm) {
1214 pm_runtime_get_sync(&pdev->dev);
1215 pm_runtime_disable(&pdev->dev);
1216 pm_runtime_put_noidle(&pdev->dev);
1217 }
1218
1219 dbg_remove_files(ci);
1220 ci_role_destroy(ci);
1221 ci_hdrc_enter_lpm(ci, true);
1222 ci_usb_phy_exit(ci);
1223 ci_ulpi_exit(ci);
1224
1225 return 0;
1226}
1227
1228#ifdef CONFIG_PM
1229
1230static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1231{
1232 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1233 !hw_read_otgsc(ci, OTGSC_ID)) {
1234 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1235 PORTSC_PP);
1236 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1237 PORTSC_WKCN);
1238 }
1239}
1240
1241
1242static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1243{
1244 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1245 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1246 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1247 ci->fsm.a_srp_det = 1;
1248 ci->fsm.a_bus_drop = 0;
1249 } else {
1250 ci->fsm.id = 1;
1251 }
1252 ci_otg_queue_work(ci);
1253 }
1254}
1255
1256static void ci_controller_suspend(struct ci_hdrc *ci)
1257{
1258 disable_irq(ci->irq);
1259 ci_hdrc_enter_lpm(ci, true);
1260 if (ci->platdata->phy_clkgate_delay_us)
1261 usleep_range(ci->platdata->phy_clkgate_delay_us,
1262 ci->platdata->phy_clkgate_delay_us + 50);
1263 usb_phy_set_suspend(ci->usb_phy, 1);
1264 ci->in_lpm = true;
1265 enable_irq(ci->irq);
1266}
1267
1268static int ci_controller_resume(struct device *dev)
1269{
1270 struct ci_hdrc *ci = dev_get_drvdata(dev);
1271 int ret;
1272
1273 dev_dbg(dev, "at %s\n", __func__);
1274
1275 if (!ci->in_lpm) {
1276 WARN_ON(1);
1277 return 0;
1278 }
1279
1280 ci_hdrc_enter_lpm(ci, false);
1281
1282 ret = ci_ulpi_resume(ci);
1283 if (ret)
1284 return ret;
1285
1286 if (ci->usb_phy) {
1287 usb_phy_set_suspend(ci->usb_phy, 0);
1288 usb_phy_set_wakeup(ci->usb_phy, false);
1289 hw_wait_phy_stable();
1290 }
1291
1292 ci->in_lpm = false;
1293 if (ci->wakeup_int) {
1294 ci->wakeup_int = false;
1295 pm_runtime_mark_last_busy(ci->dev);
1296 pm_runtime_put_autosuspend(ci->dev);
1297 enable_irq(ci->irq);
1298 if (ci_otg_is_fsm_mode(ci))
1299 ci_otg_fsm_wakeup_by_srp(ci);
1300 }
1301
1302 return 0;
1303}
1304
1305#ifdef CONFIG_PM_SLEEP
1306static int ci_suspend(struct device *dev)
1307{
1308 struct ci_hdrc *ci = dev_get_drvdata(dev);
1309
1310 if (ci->wq)
1311 flush_workqueue(ci->wq);
1312
1313
1314
1315
1316
1317
1318 if (ci->in_lpm)
1319 pm_runtime_resume(dev);
1320
1321 if (ci->in_lpm) {
1322 WARN_ON(1);
1323 return 0;
1324 }
1325
1326 if (device_may_wakeup(dev)) {
1327 if (ci_otg_is_fsm_mode(ci))
1328 ci_otg_fsm_suspend_for_srp(ci);
1329
1330 usb_phy_set_wakeup(ci->usb_phy, true);
1331 enable_irq_wake(ci->irq);
1332 }
1333
1334 ci_controller_suspend(ci);
1335
1336 return 0;
1337}
1338
1339static int ci_resume(struct device *dev)
1340{
1341 struct ci_hdrc *ci = dev_get_drvdata(dev);
1342 int ret;
1343
1344 if (device_may_wakeup(dev))
1345 disable_irq_wake(ci->irq);
1346
1347 ret = ci_controller_resume(dev);
1348 if (ret)
1349 return ret;
1350
1351 if (ci->supports_runtime_pm) {
1352 pm_runtime_disable(dev);
1353 pm_runtime_set_active(dev);
1354 pm_runtime_enable(dev);
1355 }
1356
1357 return ret;
1358}
1359#endif
1360
1361static int ci_runtime_suspend(struct device *dev)
1362{
1363 struct ci_hdrc *ci = dev_get_drvdata(dev);
1364
1365 dev_dbg(dev, "at %s\n", __func__);
1366
1367 if (ci->in_lpm) {
1368 WARN_ON(1);
1369 return 0;
1370 }
1371
1372 if (ci_otg_is_fsm_mode(ci))
1373 ci_otg_fsm_suspend_for_srp(ci);
1374
1375 usb_phy_set_wakeup(ci->usb_phy, true);
1376 ci_controller_suspend(ci);
1377
1378 return 0;
1379}
1380
1381static int ci_runtime_resume(struct device *dev)
1382{
1383 return ci_controller_resume(dev);
1384}
1385
1386#endif
1387static const struct dev_pm_ops ci_pm_ops = {
1388 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1389 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1390};
1391
1392static struct platform_driver ci_hdrc_driver = {
1393 .probe = ci_hdrc_probe,
1394 .remove = ci_hdrc_remove,
1395 .driver = {
1396 .name = "ci_hdrc",
1397 .pm = &ci_pm_ops,
1398 .dev_groups = ci_groups,
1399 },
1400};
1401
1402static int __init ci_hdrc_platform_register(void)
1403{
1404 ci_hdrc_host_driver_init();
1405 return platform_driver_register(&ci_hdrc_driver);
1406}
1407module_init(ci_hdrc_platform_register);
1408
1409static void __exit ci_hdrc_platform_unregister(void)
1410{
1411 platform_driver_unregister(&ci_hdrc_driver);
1412}
1413module_exit(ci_hdrc_platform_unregister);
1414
1415MODULE_ALIAS("platform:ci_hdrc");
1416MODULE_LICENSE("GPL v2");
1417MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1418MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1419
