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17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/bitfield.h>
26#include <linux/bitops.h>
27#include <linux/reset.h>
28#include <linux/phy/phy.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/role.h>
31#include <linux/regulator/consumer.h>
32
33
34
35#define U2P_REG_SIZE 0x20
36
37#define U2P_R0 0x0
38 #define U2P_R0_HOST_DEVICE BIT(0)
39 #define U2P_R0_POWER_OK BIT(1)
40 #define U2P_R0_HAST_MODE BIT(2)
41 #define U2P_R0_POWER_ON_RESET BIT(3)
42 #define U2P_R0_ID_PULLUP BIT(4)
43 #define U2P_R0_DRV_VBUS BIT(5)
44
45#define U2P_R1 0x4
46 #define U2P_R1_PHY_READY BIT(0)
47 #define U2P_R1_ID_DIG BIT(1)
48 #define U2P_R1_OTG_SESSION_VALID BIT(2)
49 #define U2P_R1_VBUS_VALID BIT(3)
50
51
52
53#define USB_R0 0x80
54 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
55 #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
56 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
57 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
58 #define USB_R0_U2D_ACT BIT(31)
59
60#define USB_R1 0x84
61 #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
62 #define USB_R1_U3H_PME_ENABLE BIT(1)
63 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2)
64 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7)
65 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12)
66 #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
67 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
68 #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
69 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
70 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
71
72#define USB_R2 0x88
73 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
74 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
75
76#define USB_R3 0x8c
77 #define USB_R3_P30_SSC_ENABLE BIT(0)
78 #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
79 #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
80 #define USB_R3_P30_REF_SSP_EN BIT(13)
81
82#define USB_R4 0x90
83 #define USB_R4_P21_PORT_RESET_0 BIT(0)
84 #define USB_R4_P21_SLEEP_M0 BIT(1)
85 #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
86 #define USB_R4_P21_ONLY BIT(4)
87
88#define USB_R5 0x94
89 #define USB_R5_ID_DIG_SYNC BIT(0)
90 #define USB_R5_ID_DIG_REG BIT(1)
91 #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
92 #define USB_R5_ID_DIG_EN_0 BIT(4)
93 #define USB_R5_ID_DIG_EN_1 BIT(5)
94 #define USB_R5_ID_DIG_CURR BIT(6)
95 #define USB_R5_ID_DIG_IRQ BIT(7)
96 #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
97 #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
98
99enum {
100 USB2_HOST_PHY = 0,
101 USB2_OTG_PHY,
102 USB3_HOST_PHY,
103 PHY_COUNT,
104};
105
106static const char *phy_names[PHY_COUNT] = {
107 "usb2-phy0", "usb2-phy1", "usb3-phy0",
108};
109
110static struct clk_bulk_data meson_g12a_clocks[] = {
111 { .id = NULL },
112};
113
114static struct clk_bulk_data meson_a1_clocks[] = {
115 { .id = "usb_ctrl" },
116 { .id = "usb_bus" },
117 { .id = "xtal_usb_ctrl" },
118};
119
120struct dwc3_meson_g12a_drvdata {
121 bool otg_switch_supported;
122 struct clk_bulk_data *clks;
123 int num_clks;
124};
125
126static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
127 .otg_switch_supported = true,
128 .clks = meson_g12a_clocks,
129 .num_clks = ARRAY_SIZE(meson_g12a_clocks),
130};
131
132static struct dwc3_meson_g12a_drvdata a1_drvdata = {
133 .otg_switch_supported = false,
134 .clks = meson_a1_clocks,
135 .num_clks = ARRAY_SIZE(meson_a1_clocks),
136};
137
138struct dwc3_meson_g12a {
139 struct device *dev;
140 struct regmap *regmap;
141 struct reset_control *reset;
142 struct phy *phys[PHY_COUNT];
143 enum usb_dr_mode otg_mode;
144 enum phy_mode otg_phy_mode;
145 unsigned int usb2_ports;
146 unsigned int usb3_ports;
147 struct regulator *vbus;
148 struct usb_role_switch_desc switch_desc;
149 struct usb_role_switch *role_switch;
150 const struct dwc3_meson_g12a_drvdata *drvdata;
151};
152
153static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
154 int i, enum phy_mode mode)
155{
156 if (mode == PHY_MODE_USB_HOST)
157 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
158 U2P_R0_HOST_DEVICE,
159 U2P_R0_HOST_DEVICE);
160 else
161 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
162 U2P_R0_HOST_DEVICE, 0);
163}
164
165static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
166{
167 int i;
168
169 if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
170 priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
171 else
172 priv->otg_phy_mode = PHY_MODE_USB_HOST;
173
174 for (i = 0 ; i < USB3_HOST_PHY ; ++i) {
175 if (!priv->phys[i])
176 continue;
177
178 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
179 U2P_R0_POWER_ON_RESET,
180 U2P_R0_POWER_ON_RESET);
181
182 if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) {
183 regmap_update_bits(priv->regmap,
184 U2P_R0 + (U2P_REG_SIZE * i),
185 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
186 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS);
187
188 dwc3_meson_g12a_usb2_set_mode(priv, i,
189 priv->otg_phy_mode);
190 } else
191 dwc3_meson_g12a_usb2_set_mode(priv, i,
192 PHY_MODE_USB_HOST);
193
194 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i),
195 U2P_R0_POWER_ON_RESET, 0);
196 }
197
198 return 0;
199}
200
201static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
202{
203 regmap_update_bits(priv->regmap, USB_R3,
204 USB_R3_P30_SSC_RANGE_MASK |
205 USB_R3_P30_REF_SSP_EN,
206 USB_R3_P30_SSC_ENABLE |
207 FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) |
208 USB_R3_P30_REF_SSP_EN);
209 udelay(2);
210
211 regmap_update_bits(priv->regmap, USB_R2,
212 USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK,
213 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15));
214
215 regmap_update_bits(priv->regmap, USB_R2,
216 USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK,
217 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20));
218
219 udelay(2);
220
221 regmap_update_bits(priv->regmap, USB_R1,
222 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT,
223 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT);
224
225 regmap_update_bits(priv->regmap, USB_R1,
226 USB_R1_P30_PCS_TX_SWING_FULL_MASK,
227 FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
228}
229
230static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
231{
232 if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) {
233 regmap_update_bits(priv->regmap, USB_R0,
234 USB_R0_U2D_ACT, USB_R0_U2D_ACT);
235 regmap_update_bits(priv->regmap, USB_R0,
236 USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
237 regmap_update_bits(priv->regmap, USB_R4,
238 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
239 } else {
240 regmap_update_bits(priv->regmap, USB_R0,
241 USB_R0_U2D_ACT, 0);
242 regmap_update_bits(priv->regmap, USB_R4,
243 USB_R4_P21_SLEEP_M0, 0);
244 }
245}
246
247static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
248{
249 int ret;
250
251 ret = dwc3_meson_g12a_usb2_init(priv);
252 if (ret)
253 return ret;
254
255 regmap_update_bits(priv->regmap, USB_R1,
256 USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
257 FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
258
259 regmap_update_bits(priv->regmap, USB_R5,
260 USB_R5_ID_DIG_EN_0,
261 USB_R5_ID_DIG_EN_0);
262 regmap_update_bits(priv->regmap, USB_R5,
263 USB_R5_ID_DIG_EN_1,
264 USB_R5_ID_DIG_EN_1);
265 regmap_update_bits(priv->regmap, USB_R5,
266 USB_R5_ID_DIG_TH_MASK,
267 FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
268
269
270 if (priv->usb3_ports)
271 dwc3_meson_g12a_usb3_init(priv);
272
273 dwc3_meson_g12a_usb_otg_apply_mode(priv);
274
275 return 0;
276}
277
278static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = {
279 .reg_bits = 8,
280 .val_bits = 32,
281 .reg_stride = 4,
282 .max_register = USB_R5,
283};
284
285static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv)
286{
287 int i;
288
289 for (i = 0 ; i < PHY_COUNT ; ++i) {
290 priv->phys[i] = devm_phy_optional_get(priv->dev, phy_names[i]);
291 if (!priv->phys[i])
292 continue;
293
294 if (IS_ERR(priv->phys[i]))
295 return PTR_ERR(priv->phys[i]);
296
297 if (i == USB3_HOST_PHY)
298 priv->usb3_ports++;
299 else
300 priv->usb2_ports++;
301 }
302
303 dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports);
304 dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports);
305
306 return 0;
307}
308
309static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv)
310{
311 u32 reg;
312
313 regmap_read(priv->regmap, USB_R5, ®);
314
315 if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG))
316 return PHY_MODE_USB_DEVICE;
317
318 return PHY_MODE_USB_HOST;
319}
320
321static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
322 enum phy_mode mode)
323{
324 int ret;
325
326 if (!priv->drvdata->otg_switch_supported || !priv->phys[USB2_OTG_PHY])
327 return -EINVAL;
328
329 if (mode == PHY_MODE_USB_HOST)
330 dev_info(priv->dev, "switching to Host Mode\n");
331 else
332 dev_info(priv->dev, "switching to Device Mode\n");
333
334 if (priv->vbus) {
335 if (mode == PHY_MODE_USB_DEVICE)
336 ret = regulator_disable(priv->vbus);
337 else
338 ret = regulator_enable(priv->vbus);
339 if (ret)
340 return ret;
341 }
342
343 priv->otg_phy_mode = mode;
344
345 dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode);
346
347 dwc3_meson_g12a_usb_otg_apply_mode(priv);
348
349 return 0;
350}
351
352static int dwc3_meson_g12a_role_set(struct usb_role_switch *sw,
353 enum usb_role role)
354{
355 struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
356 enum phy_mode mode;
357
358 if (role == USB_ROLE_NONE)
359 return 0;
360
361 mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST
362 : PHY_MODE_USB_DEVICE;
363
364 if (mode == priv->otg_phy_mode)
365 return 0;
366
367 return dwc3_meson_g12a_otg_mode_set(priv, mode);
368}
369
370static enum usb_role dwc3_meson_g12a_role_get(struct usb_role_switch *sw)
371{
372 struct dwc3_meson_g12a *priv = usb_role_switch_get_drvdata(sw);
373
374 return priv->otg_phy_mode == PHY_MODE_USB_HOST ?
375 USB_ROLE_HOST : USB_ROLE_DEVICE;
376}
377
378static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data)
379{
380 struct dwc3_meson_g12a *priv = data;
381 enum phy_mode otg_id;
382
383 otg_id = dwc3_meson_g12a_get_id(priv);
384 if (otg_id != priv->otg_phy_mode) {
385 if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
386 dev_warn(priv->dev, "Failed to switch OTG mode\n");
387 }
388
389 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0);
390
391 return IRQ_HANDLED;
392}
393
394static struct device *dwc3_meson_g12_find_child(struct device *dev,
395 const char *compatible)
396{
397 struct platform_device *pdev;
398 struct device_node *np;
399
400 np = of_get_compatible_child(dev->of_node, compatible);
401 if (!np)
402 return NULL;
403
404 pdev = of_find_device_by_node(np);
405 of_node_put(np);
406 if (!pdev)
407 return NULL;
408
409 return &pdev->dev;
410}
411
412static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
413 struct dwc3_meson_g12a *priv)
414{
415 enum phy_mode otg_id;
416 int ret, irq;
417 struct device *dev = &pdev->dev;
418
419 if (!priv->drvdata->otg_switch_supported)
420 return 0;
421
422 if (priv->otg_mode == USB_DR_MODE_OTG) {
423
424 regmap_update_bits(priv->regmap, USB_R5,
425 USB_R5_ID_DIG_IRQ, 0);
426
427 irq = platform_get_irq(pdev, 0);
428 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
429 dwc3_meson_g12a_irq_thread,
430 IRQF_ONESHOT, pdev->name, priv);
431 if (ret)
432 return ret;
433 }
434
435
436 if (priv->otg_mode == USB_DR_MODE_OTG) {
437 otg_id = dwc3_meson_g12a_get_id(priv);
438 if (otg_id != priv->otg_phy_mode) {
439 if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
440 dev_warn(dev, "Failed to switch OTG mode\n");
441 }
442 }
443
444
445 priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
446 "snps,dwc3");
447 priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
448 priv->switch_desc.allow_userspace_control = true;
449 priv->switch_desc.set = dwc3_meson_g12a_role_set;
450 priv->switch_desc.get = dwc3_meson_g12a_role_get;
451 priv->switch_desc.driver_data = priv;
452
453 priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
454 if (IS_ERR(priv->role_switch))
455 dev_warn(dev, "Unable to register Role Switch\n");
456
457 return 0;
458}
459
460static int dwc3_meson_g12a_probe(struct platform_device *pdev)
461{
462 struct dwc3_meson_g12a *priv;
463 struct device *dev = &pdev->dev;
464 struct device_node *np = dev->of_node;
465 void __iomem *base;
466 int ret, i;
467
468 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
469 if (!priv)
470 return -ENOMEM;
471
472 base = devm_platform_ioremap_resource(pdev, 0);
473 if (IS_ERR(base))
474 return PTR_ERR(base);
475
476 priv->regmap = devm_regmap_init_mmio(dev, base,
477 &phy_meson_g12a_usb3_regmap_conf);
478 if (IS_ERR(priv->regmap))
479 return PTR_ERR(priv->regmap);
480
481 priv->vbus = devm_regulator_get_optional(dev, "vbus");
482 if (IS_ERR(priv->vbus)) {
483 if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
484 return PTR_ERR(priv->vbus);
485 priv->vbus = NULL;
486 }
487
488 priv->drvdata = of_device_get_match_data(&pdev->dev);
489
490 ret = devm_clk_bulk_get(dev,
491 priv->drvdata->num_clks,
492 priv->drvdata->clks);
493 if (ret)
494 return ret;
495
496 ret = clk_bulk_prepare_enable(priv->drvdata->num_clks,
497 priv->drvdata->clks);
498 if (ret)
499 return ret;
500
501 platform_set_drvdata(pdev, priv);
502 priv->dev = dev;
503
504 priv->reset = devm_reset_control_get(dev, NULL);
505 if (IS_ERR(priv->reset)) {
506 ret = PTR_ERR(priv->reset);
507 dev_err(dev, "failed to get device reset, err=%d\n", ret);
508 return ret;
509 }
510
511 ret = reset_control_reset(priv->reset);
512 if (ret)
513 goto err_disable_clks;
514
515 ret = dwc3_meson_g12a_get_phys(priv);
516 if (ret)
517 goto err_disable_clks;
518
519 if (priv->vbus) {
520 ret = regulator_enable(priv->vbus);
521 if (ret)
522 goto err_disable_clks;
523 }
524
525
526 priv->otg_mode = usb_get_dr_mode(dev);
527
528 dwc3_meson_g12a_usb_init(priv);
529
530
531 for (i = 0 ; i < PHY_COUNT ; ++i) {
532 ret = phy_init(priv->phys[i]);
533 if (ret)
534 goto err_disable_clks;
535 }
536
537
538 for (i = 0 ; i < PHY_COUNT ; ++i) {
539 ret = phy_power_on(priv->phys[i]);
540 if (ret)
541 goto err_phys_exit;
542 }
543
544 ret = of_platform_populate(np, NULL, NULL, dev);
545 if (ret)
546 goto err_phys_power;
547
548 ret = dwc3_meson_g12a_otg_init(pdev, priv);
549 if (ret)
550 goto err_phys_power;
551
552 pm_runtime_set_active(dev);
553 pm_runtime_enable(dev);
554 pm_runtime_get_sync(dev);
555
556 return 0;
557
558err_phys_power:
559 for (i = 0 ; i < PHY_COUNT ; ++i)
560 phy_power_off(priv->phys[i]);
561
562err_phys_exit:
563 for (i = 0 ; i < PHY_COUNT ; ++i)
564 phy_exit(priv->phys[i]);
565
566err_disable_clks:
567 clk_bulk_disable_unprepare(priv->drvdata->num_clks,
568 priv->drvdata->clks);
569
570 return ret;
571}
572
573static int dwc3_meson_g12a_remove(struct platform_device *pdev)
574{
575 struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev);
576 struct device *dev = &pdev->dev;
577 int i;
578
579 if (priv->drvdata->otg_switch_supported)
580 usb_role_switch_unregister(priv->role_switch);
581
582 of_platform_depopulate(dev);
583
584 for (i = 0 ; i < PHY_COUNT ; ++i) {
585 phy_power_off(priv->phys[i]);
586 phy_exit(priv->phys[i]);
587 }
588
589 pm_runtime_disable(dev);
590 pm_runtime_put_noidle(dev);
591 pm_runtime_set_suspended(dev);
592
593 clk_bulk_disable_unprepare(priv->drvdata->num_clks,
594 priv->drvdata->clks);
595
596 return 0;
597}
598
599static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
600{
601 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
602
603 clk_bulk_disable_unprepare(priv->drvdata->num_clks,
604 priv->drvdata->clks);
605
606 return 0;
607}
608
609static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
610{
611 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
612
613 return clk_bulk_prepare_enable(priv->drvdata->num_clks,
614 priv->drvdata->clks);
615}
616
617static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
618{
619 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
620 int i, ret;
621
622 if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
623 ret = regulator_disable(priv->vbus);
624 if (ret)
625 return ret;
626 }
627
628 for (i = 0 ; i < PHY_COUNT ; ++i) {
629 phy_power_off(priv->phys[i]);
630 phy_exit(priv->phys[i]);
631 }
632
633 reset_control_assert(priv->reset);
634
635 return 0;
636}
637
638static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
639{
640 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
641 int i, ret;
642
643 reset_control_deassert(priv->reset);
644
645 dwc3_meson_g12a_usb_init(priv);
646
647
648 for (i = 0 ; i < PHY_COUNT ; ++i) {
649 ret = phy_init(priv->phys[i]);
650 if (ret)
651 return ret;
652 }
653
654
655 for (i = 0 ; i < PHY_COUNT ; ++i) {
656 ret = phy_power_on(priv->phys[i]);
657 if (ret)
658 return ret;
659 }
660
661 if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
662 ret = regulator_enable(priv->vbus);
663 if (ret)
664 return ret;
665 }
666
667 return 0;
668}
669
670static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
671 SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume)
672 SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend,
673 dwc3_meson_g12a_runtime_resume, NULL)
674};
675
676static const struct of_device_id dwc3_meson_g12a_match[] = {
677 {
678 .compatible = "amlogic,meson-g12a-usb-ctrl",
679 .data = &g12a_drvdata,
680 },
681 {
682 .compatible = "amlogic,meson-a1-usb-ctrl",
683 .data = &a1_drvdata,
684 },
685 { }
686};
687MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
688
689static struct platform_driver dwc3_meson_g12a_driver = {
690 .probe = dwc3_meson_g12a_probe,
691 .remove = dwc3_meson_g12a_remove,
692 .driver = {
693 .name = "dwc3-meson-g12a",
694 .of_match_table = dwc3_meson_g12a_match,
695 .pm = &dwc3_meson_g12a_dev_pm_ops,
696 },
697};
698
699module_platform_driver(dwc3_meson_g12a_driver);
700MODULE_LICENSE("GPL v2");
701MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer");
702MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
703
