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12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/mm.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/fb.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <linux/console.h>
23#include <linux/backlight.h>
24#ifdef CONFIG_BOOTX_TEXT
25#include <asm/btext.h>
26#endif
27
28#include "nv_local.h"
29#include "nv_type.h"
30#include "nv_proto.h"
31#include "nv_dma.h"
32
33#ifdef CONFIG_FB_NVIDIA_DEBUG
34#define NVTRACE printk
35#else
36#define NVTRACE if (0) printk
37#endif
38
39#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
40#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
41
42#ifdef CONFIG_FB_NVIDIA_DEBUG
43#define assert(expr) \
44 if (!(expr)) { \
45 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
46 #expr,__FILE__,__func__,__LINE__); \
47 BUG(); \
48 }
49#else
50#define assert(expr)
51#endif
52
53#define PFX "nvidiafb: "
54
55
56#define MAX_CURS 32
57
58static const struct pci_device_id nvidiafb_pci_tbl[] = {
59 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
60 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
61 { 0, }
62};
63MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
64
65
66static int flatpanel = -1;
67static int fpdither = -1;
68static int forceCRTC = -1;
69static int hwcur = 0;
70static int noaccel = 0;
71static int noscale = 0;
72static int paneltweak = 0;
73static int vram = 0;
74static int bpp = 8;
75static int reverse_i2c;
76static bool nomtrr = false;
77#ifdef CONFIG_PMAC_BACKLIGHT
78static int backlight = 1;
79#else
80static int backlight = 0;
81#endif
82
83static char *mode_option = NULL;
84
85static struct fb_fix_screeninfo nvidiafb_fix = {
86 .type = FB_TYPE_PACKED_PIXELS,
87 .xpanstep = 8,
88 .ypanstep = 1,
89};
90
91static struct fb_var_screeninfo nvidiafb_default_var = {
92 .xres = 640,
93 .yres = 480,
94 .xres_virtual = 640,
95 .yres_virtual = 480,
96 .bits_per_pixel = 8,
97 .red = {0, 8, 0},
98 .green = {0, 8, 0},
99 .blue = {0, 8, 0},
100 .transp = {0, 0, 0},
101 .activate = FB_ACTIVATE_NOW,
102 .height = -1,
103 .width = -1,
104 .pixclock = 39721,
105 .left_margin = 40,
106 .right_margin = 24,
107 .upper_margin = 32,
108 .lower_margin = 11,
109 .hsync_len = 96,
110 .vsync_len = 2,
111 .vmode = FB_VMODE_NONINTERLACED
112};
113
114static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
115 u16 bg, u16 fg, u32 w, u32 h)
116{
117 u32 *data = (u32 *) data8;
118 int i, j, k = 0;
119 u32 b, tmp;
120
121 w = (w + 1) & ~1;
122
123 for (i = 0; i < h; i++) {
124 b = *data++;
125 reverse_order(&b);
126
127 for (j = 0; j < w / 2; j++) {
128 tmp = 0;
129#if defined (__BIG_ENDIAN)
130 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
131 b <<= 1;
132 tmp |= (b & (1 << 31)) ? fg : bg;
133 b <<= 1;
134#else
135 tmp = (b & 1) ? fg : bg;
136 b >>= 1;
137 tmp |= (b & 1) ? fg << 16 : bg << 16;
138 b >>= 1;
139#endif
140 NV_WR32(&par->CURSOR[k++], 0, tmp);
141 }
142 k += (MAX_CURS - w) / 2;
143 }
144}
145
146static void nvidia_write_clut(struct nvidia_par *par,
147 u8 regnum, u8 red, u8 green, u8 blue)
148{
149 NVWriteDacMask(par, 0xff);
150 NVWriteDacWriteAddr(par, regnum);
151 NVWriteDacData(par, red);
152 NVWriteDacData(par, green);
153 NVWriteDacData(par, blue);
154}
155
156static void nvidia_read_clut(struct nvidia_par *par,
157 u8 regnum, u8 * red, u8 * green, u8 * blue)
158{
159 NVWriteDacMask(par, 0xff);
160 NVWriteDacReadAddr(par, regnum);
161 *red = NVReadDacData(par);
162 *green = NVReadDacData(par);
163 *blue = NVReadDacData(par);
164}
165
166static int nvidia_panel_tweak(struct nvidia_par *par,
167 struct _riva_hw_state *state)
168{
169 int tweak = 0;
170
171 if (par->paneltweak) {
172 tweak = par->paneltweak;
173 } else {
174
175
176
177
178
179
180 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
181
182 tweak = -1;
183 }
184
185 if ((par->Chipset & 0xfff0) == 0x0310)
186 tweak = 1;
187
188 }
189
190 return tweak;
191}
192
193static void nvidia_screen_off(struct nvidia_par *par, int on)
194{
195 unsigned char tmp;
196
197 if (on) {
198
199
200
201 tmp = NVReadSeq(par, 0x01);
202
203 NVWriteSeq(par, 0x00, 0x01);
204 NVWriteSeq(par, 0x01, tmp | 0x20);
205 } else {
206
207
208
209
210 tmp = NVReadSeq(par, 0x01);
211
212 NVWriteSeq(par, 0x01, tmp & ~0x20);
213 NVWriteSeq(par, 0x00, 0x03);
214 }
215}
216
217static void nvidia_save_vga(struct nvidia_par *par,
218 struct _riva_hw_state *state)
219{
220 int i;
221
222 NVTRACE_ENTER();
223 NVLockUnlock(par, 0);
224
225 NVUnloadStateExt(par, state);
226
227 state->misc_output = NVReadMiscOut(par);
228
229 for (i = 0; i < NUM_CRT_REGS; i++)
230 state->crtc[i] = NVReadCrtc(par, i);
231
232 for (i = 0; i < NUM_ATC_REGS; i++)
233 state->attr[i] = NVReadAttr(par, i);
234
235 for (i = 0; i < NUM_GRC_REGS; i++)
236 state->gra[i] = NVReadGr(par, i);
237
238 for (i = 0; i < NUM_SEQ_REGS; i++)
239 state->seq[i] = NVReadSeq(par, i);
240 NVTRACE_LEAVE();
241}
242
243#undef DUMP_REG
244
245static void nvidia_write_regs(struct nvidia_par *par,
246 struct _riva_hw_state *state)
247{
248 int i;
249
250 NVTRACE_ENTER();
251
252 NVLoadStateExt(par, state);
253
254 NVWriteMiscOut(par, state->misc_output);
255
256 for (i = 1; i < NUM_SEQ_REGS; i++) {
257#ifdef DUMP_REG
258 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
259#endif
260 NVWriteSeq(par, i, state->seq[i]);
261 }
262
263
264 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
265
266 for (i = 0; i < NUM_CRT_REGS; i++) {
267 switch (i) {
268 case 0x19:
269 case 0x20 ... 0x40:
270 break;
271 default:
272#ifdef DUMP_REG
273 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
274#endif
275 NVWriteCrtc(par, i, state->crtc[i]);
276 }
277 }
278
279 for (i = 0; i < NUM_GRC_REGS; i++) {
280#ifdef DUMP_REG
281 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
282#endif
283 NVWriteGr(par, i, state->gra[i]);
284 }
285
286 for (i = 0; i < NUM_ATC_REGS; i++) {
287#ifdef DUMP_REG
288 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
289#endif
290 NVWriteAttr(par, i, state->attr[i]);
291 }
292
293 NVTRACE_LEAVE();
294}
295
296static int nvidia_calc_regs(struct fb_info *info)
297{
298 struct nvidia_par *par = info->par;
299 struct _riva_hw_state *state = &par->ModeReg;
300 int i, depth = fb_get_color_depth(&info->var, &info->fix);
301 int h_display = info->var.xres / 8 - 1;
302 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
303 int h_end = (info->var.xres + info->var.right_margin +
304 info->var.hsync_len) / 8 - 1;
305 int h_total = (info->var.xres + info->var.right_margin +
306 info->var.hsync_len + info->var.left_margin) / 8 - 5;
307 int h_blank_s = h_display;
308 int h_blank_e = h_total + 4;
309 int v_display = info->var.yres - 1;
310 int v_start = info->var.yres + info->var.lower_margin - 1;
311 int v_end = (info->var.yres + info->var.lower_margin +
312 info->var.vsync_len) - 1;
313 int v_total = (info->var.yres + info->var.lower_margin +
314 info->var.vsync_len + info->var.upper_margin) - 2;
315 int v_blank_s = v_display;
316 int v_blank_e = v_total + 1;
317
318
319
320
321
322 if (info->var.vmode & FB_VMODE_INTERLACED)
323 v_total |= 1;
324
325 if (par->FlatPanel == 1) {
326 v_start = v_total - 3;
327 v_end = v_total - 2;
328 v_blank_s = v_start;
329 h_start = h_total - 5;
330 h_end = h_total - 2;
331 h_blank_e = h_total + 4;
332 }
333
334 state->crtc[0x0] = Set8Bits(h_total);
335 state->crtc[0x1] = Set8Bits(h_display);
336 state->crtc[0x2] = Set8Bits(h_blank_s);
337 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
338 | SetBit(7);
339 state->crtc[0x4] = Set8Bits(h_start);
340 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
341 | SetBitField(h_end, 4: 0, 4:0);
342 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
343 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
344 | SetBitField(v_display, 8: 8, 1:1)
345 | SetBitField(v_start, 8: 8, 2:2)
346 | SetBitField(v_blank_s, 8: 8, 3:3)
347 | SetBit(4)
348 | SetBitField(v_total, 9: 9, 5:5)
349 | SetBitField(v_display, 9: 9, 6:6)
350 | SetBitField(v_start, 9: 9, 7:7);
351 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
352 | SetBit(6)
353 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
354 state->crtc[0x10] = Set8Bits(v_start);
355 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
356 state->crtc[0x12] = Set8Bits(v_display);
357 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
358 (info->var.bits_per_pixel / 8));
359 state->crtc[0x15] = Set8Bits(v_blank_s);
360 state->crtc[0x16] = Set8Bits(v_blank_e);
361
362 state->attr[0x10] = 0x01;
363
364 if (par->Television)
365 state->attr[0x11] = 0x00;
366
367 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
368 | SetBitField(v_blank_s, 10: 10, 3:3)
369 | SetBitField(v_start, 10: 10, 2:2)
370 | SetBitField(v_display, 10: 10, 1:1)
371 | SetBitField(v_total, 10: 10, 0:0);
372
373 state->horiz = SetBitField(h_total, 8: 8, 0:0)
374 | SetBitField(h_display, 8: 8, 1:1)
375 | SetBitField(h_blank_s, 8: 8, 2:2)
376 | SetBitField(h_start, 8: 8, 3:3);
377
378 state->extra = SetBitField(v_total, 11: 11, 0:0)
379 | SetBitField(v_display, 11: 11, 2:2)
380 | SetBitField(v_start, 11: 11, 4:4)
381 | SetBitField(v_blank_s, 11: 11, 6:6);
382
383 if (info->var.vmode & FB_VMODE_INTERLACED) {
384 h_total = (h_total >> 1) & ~1;
385 state->interlace = Set8Bits(h_total);
386 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
387 } else {
388 state->interlace = 0xff;
389 }
390
391
392
393
394
395 if (depth < 24)
396 i = depth;
397 else
398 i = 32;
399
400 if (par->Architecture >= NV_ARCH_10)
401 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
402 par->CursorStart);
403
404 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
405 state->misc_output &= ~0x40;
406 else
407 state->misc_output |= 0x40;
408 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
409 state->misc_output &= ~0x80;
410 else
411 state->misc_output |= 0x80;
412
413 NVCalcStateExt(par, state, i, info->var.xres_virtual,
414 info->var.xres, info->var.yres_virtual,
415 1000000000 / info->var.pixclock, info->var.vmode);
416
417 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
418 if (par->FlatPanel == 1) {
419 state->pixel |= (1 << 7);
420
421 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
422 || (par->fpHeight <= info->var.yres)) {
423 state->scale |= (1 << 8);
424 }
425
426 if (!par->crtcSync_read) {
427 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
428 par->crtcSync_read = 1;
429 }
430
431 par->PanelTweak = nvidia_panel_tweak(par, state);
432 }
433
434 state->vpll = state->pll;
435 state->vpll2 = state->pll;
436 state->vpllB = state->pllB;
437 state->vpll2B = state->pllB;
438
439 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
440 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
441
442 if (par->CRTCnumber) {
443 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
444 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
445 state->crtcOwner = 3;
446 state->pllsel |= 0x20000800;
447 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
448 if (par->twoStagePLL)
449 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
450 } else if (par->twoHeads) {
451 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
452 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
453 state->crtcOwner = 0;
454 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
455 if (par->twoStagePLL)
456 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
457 }
458
459 state->cursorConfig = 0x00000100;
460
461 if (info->var.vmode & FB_VMODE_DOUBLE)
462 state->cursorConfig |= (1 << 4);
463
464 if (par->alphaCursor) {
465 if ((par->Chipset & 0x0ff0) != 0x0110)
466 state->cursorConfig |= 0x04011000;
467 else
468 state->cursorConfig |= 0x14011000;
469 state->general |= (1 << 29);
470 } else
471 state->cursorConfig |= 0x02000000;
472
473 if (par->twoHeads) {
474 if ((par->Chipset & 0x0ff0) == 0x0110) {
475 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
476 ~0x00010000;
477 if (par->FPDither)
478 state->dither |= 0x00010000;
479 } else {
480 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
481 if (par->FPDither)
482 state->dither |= 1;
483 }
484 }
485
486 state->timingH = 0;
487 state->timingV = 0;
488 state->displayV = info->var.xres;
489
490 return 0;
491}
492
493static void nvidia_init_vga(struct fb_info *info)
494{
495 struct nvidia_par *par = info->par;
496 struct _riva_hw_state *state = &par->ModeReg;
497 int i;
498
499 for (i = 0; i < 0x10; i++)
500 state->attr[i] = i;
501 state->attr[0x10] = 0x41;
502 state->attr[0x11] = 0xff;
503 state->attr[0x12] = 0x0f;
504 state->attr[0x13] = 0x00;
505 state->attr[0x14] = 0x00;
506
507 memset(state->crtc, 0x00, NUM_CRT_REGS);
508 state->crtc[0x0a] = 0x20;
509 state->crtc[0x17] = 0xe3;
510 state->crtc[0x18] = 0xff;
511 state->crtc[0x28] = 0x40;
512
513 memset(state->gra, 0x00, NUM_GRC_REGS);
514 state->gra[0x05] = 0x40;
515 state->gra[0x06] = 0x05;
516 state->gra[0x07] = 0x0f;
517 state->gra[0x08] = 0xff;
518
519 state->seq[0x00] = 0x03;
520 state->seq[0x01] = 0x01;
521 state->seq[0x02] = 0x0f;
522 state->seq[0x03] = 0x00;
523 state->seq[0x04] = 0x0e;
524
525 state->misc_output = 0xeb;
526}
527
528static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
529{
530 struct nvidia_par *par = info->par;
531 u8 data[MAX_CURS * MAX_CURS / 8];
532 int i, set = cursor->set;
533 u16 fg, bg;
534
535 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
536 return -ENXIO;
537
538 NVShowHideCursor(par, 0);
539
540 if (par->cursor_reset) {
541 set = FB_CUR_SETALL;
542 par->cursor_reset = 0;
543 }
544
545 if (set & FB_CUR_SETSIZE)
546 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
547
548 if (set & FB_CUR_SETPOS) {
549 u32 xx, yy, temp;
550
551 yy = cursor->image.dy - info->var.yoffset;
552 xx = cursor->image.dx - info->var.xoffset;
553 temp = xx & 0xFFFF;
554 temp |= yy << 16;
555
556 NV_WR32(par->PRAMDAC, 0x0000300, temp);
557 }
558
559 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
560 u32 bg_idx = cursor->image.bg_color;
561 u32 fg_idx = cursor->image.fg_color;
562 u32 s_pitch = (cursor->image.width + 7) >> 3;
563 u32 d_pitch = MAX_CURS / 8;
564 u8 *dat = (u8 *) cursor->image.data;
565 u8 *msk = (u8 *) cursor->mask;
566 u8 *src;
567
568 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
569
570 if (src) {
571 switch (cursor->rop) {
572 case ROP_XOR:
573 for (i = 0; i < s_pitch * cursor->image.height; i++)
574 src[i] = dat[i] ^ msk[i];
575 break;
576 case ROP_COPY:
577 default:
578 for (i = 0; i < s_pitch * cursor->image.height; i++)
579 src[i] = dat[i] & msk[i];
580 break;
581 }
582
583 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
584 cursor->image.height);
585
586 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
587 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
588 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
589
590 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
591 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
592 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
593
594 NVLockUnlock(par, 0);
595
596 nvidiafb_load_cursor_image(par, data, bg, fg,
597 cursor->image.width,
598 cursor->image.height);
599 kfree(src);
600 }
601 }
602
603 if (cursor->enable)
604 NVShowHideCursor(par, 1);
605
606 return 0;
607}
608
609static struct fb_ops nvidia_fb_ops;
610
611static int nvidiafb_set_par(struct fb_info *info)
612{
613 struct nvidia_par *par = info->par;
614
615 NVTRACE_ENTER();
616
617 NVLockUnlock(par, 1);
618 if (!par->FlatPanel || !par->twoHeads)
619 par->FPDither = 0;
620
621 if (par->FPDither < 0) {
622 if ((par->Chipset & 0x0ff0) == 0x0110)
623 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
624 & 0x00010000);
625 else
626 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
627 printk(KERN_INFO PFX "Flat panel dithering %s\n",
628 par->FPDither ? "enabled" : "disabled");
629 }
630
631 info->fix.visual = (info->var.bits_per_pixel == 8) ?
632 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
633
634 nvidia_init_vga(info);
635 nvidia_calc_regs(info);
636
637 NVLockUnlock(par, 0);
638 if (par->twoHeads) {
639 VGA_WR08(par->PCIO, 0x03D4, 0x44);
640 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
641 NVLockUnlock(par, 0);
642 }
643
644 nvidia_screen_off(par, 1);
645
646 nvidia_write_regs(par, &par->ModeReg);
647 NVSetStartAddress(par, 0);
648
649#if defined (__BIG_ENDIAN)
650
651 {
652 unsigned char tmp;
653
654 VGA_WR08(par->PCIO, 0x3d4, 0x46);
655 tmp = VGA_RD08(par->PCIO, 0x3d5);
656 tmp |= (1 << 7);
657 VGA_WR08(par->PCIO, 0x3d5, tmp);
658 }
659#endif
660
661 info->fix.line_length = (info->var.xres_virtual *
662 info->var.bits_per_pixel) >> 3;
663 if (info->var.accel_flags) {
664 nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit;
665 nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect;
666 nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea;
667 nvidia_fb_ops.fb_sync = nvidiafb_sync;
668 info->pixmap.scan_align = 4;
669 info->flags &= ~FBINFO_HWACCEL_DISABLED;
670 info->flags |= FBINFO_READS_FAST;
671 NVResetGraphics(info);
672 } else {
673 nvidia_fb_ops.fb_imageblit = cfb_imageblit;
674 nvidia_fb_ops.fb_fillrect = cfb_fillrect;
675 nvidia_fb_ops.fb_copyarea = cfb_copyarea;
676 nvidia_fb_ops.fb_sync = NULL;
677 info->pixmap.scan_align = 1;
678 info->flags |= FBINFO_HWACCEL_DISABLED;
679 info->flags &= ~FBINFO_READS_FAST;
680 }
681
682 par->cursor_reset = 1;
683
684 nvidia_screen_off(par, 0);
685
686#ifdef CONFIG_BOOTX_TEXT
687
688 btext_update_display(info->fix.smem_start,
689 info->var.xres, info->var.yres,
690 info->var.bits_per_pixel, info->fix.line_length);
691#endif
692
693 NVLockUnlock(par, 0);
694 NVTRACE_LEAVE();
695 return 0;
696}
697
698static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
699 unsigned blue, unsigned transp,
700 struct fb_info *info)
701{
702 struct nvidia_par *par = info->par;
703 int i;
704
705 NVTRACE_ENTER();
706 if (regno >= (1 << info->var.green.length))
707 return -EINVAL;
708
709 if (info->var.grayscale) {
710
711 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
712 }
713
714 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
715 ((u32 *) info->pseudo_palette)[regno] =
716 (regno << info->var.red.offset) |
717 (regno << info->var.green.offset) |
718 (regno << info->var.blue.offset);
719 }
720
721 switch (info->var.bits_per_pixel) {
722 case 8:
723
724 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
725 break;
726 case 16:
727 if (info->var.green.length == 5) {
728 for (i = 0; i < 8; i++) {
729 nvidia_write_clut(par, regno * 8 + i, red >> 8,
730 green >> 8, blue >> 8);
731 }
732 } else {
733 u8 r, g, b;
734
735 if (regno < 32) {
736 for (i = 0; i < 8; i++) {
737 nvidia_write_clut(par, regno * 8 + i,
738 red >> 8, green >> 8,
739 blue >> 8);
740 }
741 }
742
743 nvidia_read_clut(par, regno * 4, &r, &g, &b);
744
745 for (i = 0; i < 4; i++)
746 nvidia_write_clut(par, regno * 4 + i, r,
747 green >> 8, b);
748 }
749 break;
750 case 32:
751 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
752 break;
753 default:
754
755 break;
756 }
757
758 NVTRACE_LEAVE();
759 return 0;
760}
761
762static int nvidiafb_check_var(struct fb_var_screeninfo *var,
763 struct fb_info *info)
764{
765 struct nvidia_par *par = info->par;
766 int memlen, vramlen, mode_valid = 0;
767 int pitch, err = 0;
768
769 NVTRACE_ENTER();
770
771 var->transp.offset = 0;
772 var->transp.length = 0;
773
774 var->xres &= ~7;
775
776 if (var->bits_per_pixel <= 8)
777 var->bits_per_pixel = 8;
778 else if (var->bits_per_pixel <= 16)
779 var->bits_per_pixel = 16;
780 else
781 var->bits_per_pixel = 32;
782
783 switch (var->bits_per_pixel) {
784 case 8:
785 var->red.offset = 0;
786 var->red.length = 8;
787 var->green.offset = 0;
788 var->green.length = 8;
789 var->blue.offset = 0;
790 var->blue.length = 8;
791 var->transp.offset = 0;
792 var->transp.length = 0;
793 break;
794 case 16:
795 var->green.length = (var->green.length < 6) ? 5 : 6;
796 var->red.length = 5;
797 var->blue.length = 5;
798 var->transp.length = 6 - var->green.length;
799 var->blue.offset = 0;
800 var->green.offset = 5;
801 var->red.offset = 5 + var->green.length;
802 var->transp.offset = (5 + var->red.offset) & 15;
803 break;
804 case 32:
805 var->red.offset = 16;
806 var->red.length = 8;
807 var->green.offset = 8;
808 var->green.length = 8;
809 var->blue.offset = 0;
810 var->blue.length = 8;
811 var->transp.length = 8;
812 var->transp.offset = 24;
813 break;
814 }
815
816 var->red.msb_right = 0;
817 var->green.msb_right = 0;
818 var->blue.msb_right = 0;
819 var->transp.msb_right = 0;
820
821 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
822 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
823 mode_valid = 1;
824
825
826 if (!mode_valid && info->monspecs.gtf) {
827 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
828 mode_valid = 1;
829 }
830
831 if (!mode_valid) {
832 const struct fb_videomode *mode;
833
834 mode = fb_find_best_mode(var, &info->modelist);
835 if (mode) {
836 fb_videomode_to_var(var, mode);
837 mode_valid = 1;
838 }
839 }
840
841 if (!mode_valid && info->monspecs.modedb_len)
842 return -EINVAL;
843
844
845
846
847
848
849 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
850 par->fpHeight < var->yres)) {
851 const struct fb_videomode *mode;
852
853 var->xres = par->fpWidth;
854 var->yres = par->fpHeight;
855
856 mode = fb_find_best_mode(var, &info->modelist);
857 if (!mode) {
858 printk(KERN_ERR PFX "mode out of range of flat "
859 "panel dimensions\n");
860 return -EINVAL;
861 }
862
863 fb_videomode_to_var(var, mode);
864 }
865
866 if (var->yres_virtual < var->yres)
867 var->yres_virtual = var->yres;
868
869 if (var->xres_virtual < var->xres)
870 var->xres_virtual = var->xres;
871
872 var->xres_virtual = (var->xres_virtual + 63) & ~63;
873
874 vramlen = info->screen_size;
875 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
876 memlen = pitch * var->yres_virtual;
877
878 if (memlen > vramlen) {
879 var->yres_virtual = vramlen / pitch;
880
881 if (var->yres_virtual < var->yres) {
882 var->yres_virtual = var->yres;
883 var->xres_virtual = vramlen / var->yres_virtual;
884 var->xres_virtual /= var->bits_per_pixel / 8;
885 var->xres_virtual &= ~63;
886 pitch = (var->xres_virtual *
887 var->bits_per_pixel + 7) / 8;
888 memlen = pitch * var->yres;
889
890 if (var->xres_virtual < var->xres) {
891 printk("nvidiafb: required video memory, "
892 "%d bytes, for %dx%d-%d (virtual) "
893 "is out of range\n",
894 memlen, var->xres_virtual,
895 var->yres_virtual, var->bits_per_pixel);
896 err = -ENOMEM;
897 }
898 }
899 }
900
901 if (var->accel_flags) {
902 if (var->yres_virtual > 0x7fff)
903 var->yres_virtual = 0x7fff;
904 if (var->xres_virtual > 0x7fff)
905 var->xres_virtual = 0x7fff;
906 }
907
908 var->xres_virtual &= ~63;
909
910 NVTRACE_LEAVE();
911
912 return err;
913}
914
915static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
916 struct fb_info *info)
917{
918 struct nvidia_par *par = info->par;
919 u32 total;
920
921 total = var->yoffset * info->fix.line_length + var->xoffset;
922
923 NVSetStartAddress(par, total);
924
925 return 0;
926}
927
928static int nvidiafb_blank(int blank, struct fb_info *info)
929{
930 struct nvidia_par *par = info->par;
931 unsigned char tmp, vesa;
932
933 tmp = NVReadSeq(par, 0x01) & ~0x20;
934 vesa = NVReadCrtc(par, 0x1a) & ~0xc0;
935
936 NVTRACE_ENTER();
937
938 if (blank)
939 tmp |= 0x20;
940
941 switch (blank) {
942 case FB_BLANK_UNBLANK:
943 case FB_BLANK_NORMAL:
944 break;
945 case FB_BLANK_VSYNC_SUSPEND:
946 vesa |= 0x80;
947 break;
948 case FB_BLANK_HSYNC_SUSPEND:
949 vesa |= 0x40;
950 break;
951 case FB_BLANK_POWERDOWN:
952 vesa |= 0xc0;
953 break;
954 }
955
956 NVWriteSeq(par, 0x01, tmp);
957 NVWriteCrtc(par, 0x1a, vesa);
958
959 NVTRACE_LEAVE();
960
961 return 0;
962}
963
964
965
966
967
968
969
970#ifdef CONFIG_X86
971static void save_vga_x86(struct nvidia_par *par)
972{
973 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
974
975 if (res && res->flags & IORESOURCE_ROM_SHADOW) {
976 memset(&par->vgastate, 0, sizeof(par->vgastate));
977 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
978 VGA_SAVE_CMAP;
979 save_vga(&par->vgastate);
980 }
981}
982
983static void restore_vga_x86(struct nvidia_par *par)
984{
985 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
986
987 if (res && res->flags & IORESOURCE_ROM_SHADOW)
988 restore_vga(&par->vgastate);
989}
990#else
991#define save_vga_x86(x) do {} while (0)
992#define restore_vga_x86(x) do {} while (0)
993#endif
994
995static int nvidiafb_open(struct fb_info *info, int user)
996{
997 struct nvidia_par *par = info->par;
998
999 if (!par->open_count) {
1000 save_vga_x86(par);
1001 nvidia_save_vga(par, &par->initial_state);
1002 }
1003
1004 par->open_count++;
1005 return 0;
1006}
1007
1008static int nvidiafb_release(struct fb_info *info, int user)
1009{
1010 struct nvidia_par *par = info->par;
1011 int err = 0;
1012
1013 if (!par->open_count) {
1014 err = -EINVAL;
1015 goto done;
1016 }
1017
1018 if (par->open_count == 1) {
1019 nvidia_write_regs(par, &par->initial_state);
1020 restore_vga_x86(par);
1021 }
1022
1023 par->open_count--;
1024done:
1025 return err;
1026}
1027
1028static struct fb_ops nvidia_fb_ops = {
1029 .owner = THIS_MODULE,
1030 .fb_open = nvidiafb_open,
1031 .fb_release = nvidiafb_release,
1032 .fb_check_var = nvidiafb_check_var,
1033 .fb_set_par = nvidiafb_set_par,
1034 .fb_setcolreg = nvidiafb_setcolreg,
1035 .fb_pan_display = nvidiafb_pan_display,
1036 .fb_blank = nvidiafb_blank,
1037 .fb_fillrect = nvidiafb_fillrect,
1038 .fb_copyarea = nvidiafb_copyarea,
1039 .fb_imageblit = nvidiafb_imageblit,
1040 .fb_cursor = nvidiafb_cursor,
1041 .fb_sync = nvidiafb_sync,
1042};
1043
1044#ifdef CONFIG_PM
1045static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg)
1046{
1047 struct fb_info *info = pci_get_drvdata(dev);
1048 struct nvidia_par *par = info->par;
1049
1050 if (mesg.event == PM_EVENT_PRETHAW)
1051 mesg.event = PM_EVENT_FREEZE;
1052 console_lock();
1053 par->pm_state = mesg.event;
1054
1055 if (mesg.event & PM_EVENT_SLEEP) {
1056 fb_set_suspend(info, 1);
1057 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1058 nvidia_write_regs(par, &par->SavedReg);
1059 pci_save_state(dev);
1060 pci_disable_device(dev);
1061 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1062 }
1063 dev->dev.power.power_state = mesg;
1064
1065 console_unlock();
1066 return 0;
1067}
1068
1069static int nvidiafb_resume(struct pci_dev *dev)
1070{
1071 struct fb_info *info = pci_get_drvdata(dev);
1072 struct nvidia_par *par = info->par;
1073
1074 console_lock();
1075 pci_set_power_state(dev, PCI_D0);
1076
1077 if (par->pm_state != PM_EVENT_FREEZE) {
1078 pci_restore_state(dev);
1079
1080 if (pci_enable_device(dev))
1081 goto fail;
1082
1083 pci_set_master(dev);
1084 }
1085
1086 par->pm_state = PM_EVENT_ON;
1087 nvidiafb_set_par(info);
1088 fb_set_suspend (info, 0);
1089 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1090
1091fail:
1092 console_unlock();
1093 return 0;
1094}
1095#else
1096#define nvidiafb_suspend NULL
1097#define nvidiafb_resume NULL
1098#endif
1099
1100static int nvidia_set_fbinfo(struct fb_info *info)
1101{
1102 struct fb_monspecs *specs = &info->monspecs;
1103 struct fb_videomode modedb;
1104 struct nvidia_par *par = info->par;
1105 int lpitch;
1106
1107 NVTRACE_ENTER();
1108 info->flags = FBINFO_DEFAULT
1109 | FBINFO_HWACCEL_IMAGEBLIT
1110 | FBINFO_HWACCEL_FILLRECT
1111 | FBINFO_HWACCEL_COPYAREA
1112 | FBINFO_HWACCEL_YPAN;
1113
1114 fb_videomode_to_modelist(info->monspecs.modedb,
1115 info->monspecs.modedb_len, &info->modelist);
1116 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1117
1118 switch (bpp) {
1119 case 0 ... 8:
1120 bpp = 8;
1121 break;
1122 case 9 ... 16:
1123 bpp = 16;
1124 break;
1125 default:
1126 bpp = 32;
1127 break;
1128 }
1129
1130 if (specs->modedb != NULL) {
1131 const struct fb_videomode *mode;
1132
1133 mode = fb_find_best_display(specs, &info->modelist);
1134 fb_videomode_to_var(&nvidiafb_default_var, mode);
1135 nvidiafb_default_var.bits_per_pixel = bpp;
1136 } else if (par->fpWidth && par->fpHeight) {
1137 char buf[16];
1138
1139 memset(buf, 0, 16);
1140 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1141 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1142 specs->modedb_len, &modedb, bpp);
1143 }
1144
1145 if (mode_option)
1146 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1147 specs->modedb, specs->modedb_len, &modedb, bpp);
1148
1149 info->var = nvidiafb_default_var;
1150 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1151 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1152 info->pseudo_palette = par->pseudo_palette;
1153 fb_alloc_cmap(&info->cmap, 256, 0);
1154 fb_destroy_modedb(info->monspecs.modedb);
1155 info->monspecs.modedb = NULL;
1156
1157
1158 lpitch = info->var.xres_virtual *
1159 ((info->var.bits_per_pixel + 7) >> 3);
1160 info->var.yres_virtual = info->screen_size / lpitch;
1161
1162 info->pixmap.scan_align = 4;
1163 info->pixmap.buf_align = 4;
1164 info->pixmap.access_align = 32;
1165 info->pixmap.size = 8 * 1024;
1166 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1167
1168 if (!hwcur)
1169 nvidia_fb_ops.fb_cursor = NULL;
1170
1171 info->var.accel_flags = (!noaccel);
1172
1173 switch (par->Architecture) {
1174 case NV_ARCH_04:
1175 info->fix.accel = FB_ACCEL_NV4;
1176 break;
1177 case NV_ARCH_10:
1178 info->fix.accel = FB_ACCEL_NV_10;
1179 break;
1180 case NV_ARCH_20:
1181 info->fix.accel = FB_ACCEL_NV_20;
1182 break;
1183 case NV_ARCH_30:
1184 info->fix.accel = FB_ACCEL_NV_30;
1185 break;
1186 case NV_ARCH_40:
1187 info->fix.accel = FB_ACCEL_NV_40;
1188 break;
1189 }
1190
1191 NVTRACE_LEAVE();
1192
1193 return nvidiafb_check_var(&info->var, info);
1194}
1195
1196static u32 nvidia_get_chipset(struct fb_info *info)
1197{
1198 struct nvidia_par *par = info->par;
1199 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1200
1201 printk(KERN_INFO PFX "Device ID: %x \n", id);
1202
1203 if ((id & 0xfff0) == 0x00f0 ||
1204 (id & 0xfff0) == 0x02e0) {
1205
1206 id = NV_RD32(par->REGS, 0x1800);
1207
1208 if ((id & 0x0000ffff) == 0x000010DE)
1209 id = 0x10DE0000 | (id >> 16);
1210 else if ((id & 0xffff0000) == 0xDE100000)
1211 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1212 ((id >> 8) & 0x000000ff);
1213 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1214 }
1215
1216 return id;
1217}
1218
1219static u32 nvidia_get_arch(struct fb_info *info)
1220{
1221 struct nvidia_par *par = info->par;
1222 u32 arch = 0;
1223
1224 switch (par->Chipset & 0x0ff0) {
1225 case 0x0100:
1226 case 0x0110:
1227 case 0x0150:
1228 case 0x0170:
1229 case 0x0180:
1230 case 0x01A0:
1231 case 0x01F0:
1232 arch = NV_ARCH_10;
1233 break;
1234 case 0x0200:
1235 case 0x0250:
1236 case 0x0280:
1237 arch = NV_ARCH_20;
1238 break;
1239 case 0x0300:
1240 case 0x0310:
1241 case 0x0320:
1242 case 0x0330:
1243 case 0x0340:
1244 arch = NV_ARCH_30;
1245 break;
1246 case 0x0040:
1247 case 0x00C0:
1248 case 0x0120:
1249 case 0x0140:
1250 case 0x0160:
1251 case 0x01D0:
1252 case 0x0090:
1253 case 0x0210:
1254 case 0x0220:
1255 case 0x0240:
1256 case 0x0290:
1257 case 0x0390:
1258 case 0x03D0:
1259 arch = NV_ARCH_40;
1260 break;
1261 case 0x0020:
1262 arch = NV_ARCH_04;
1263 break;
1264 default:
1265 break;
1266 }
1267
1268 return arch;
1269}
1270
1271static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1272{
1273 struct nvidia_par *par;
1274 struct fb_info *info;
1275 unsigned short cmd;
1276
1277
1278 NVTRACE_ENTER();
1279 assert(pd != NULL);
1280
1281 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1282
1283 if (!info)
1284 goto err_out;
1285
1286 par = info->par;
1287 par->pci_dev = pd;
1288 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1289
1290 if (info->pixmap.addr == NULL)
1291 goto err_out_kfree;
1292
1293 if (pci_enable_device(pd)) {
1294 printk(KERN_ERR PFX "cannot enable PCI device\n");
1295 goto err_out_enable;
1296 }
1297
1298 if (pci_request_regions(pd, "nvidiafb")) {
1299 printk(KERN_ERR PFX "cannot request PCI regions\n");
1300 goto err_out_enable;
1301 }
1302
1303 par->FlatPanel = flatpanel;
1304 if (flatpanel == 1)
1305 printk(KERN_INFO PFX "flatpanel support enabled\n");
1306 par->FPDither = fpdither;
1307
1308 par->CRTCnumber = forceCRTC;
1309 par->FpScale = (!noscale);
1310 par->paneltweak = paneltweak;
1311 par->reverse_i2c = reverse_i2c;
1312
1313
1314 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1315 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1316 pci_write_config_word(pd, PCI_COMMAND, cmd);
1317
1318 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1319 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1320 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1321
1322 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1323
1324 if (!par->REGS) {
1325 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1326 goto err_out_free_base0;
1327 }
1328
1329 par->Chipset = nvidia_get_chipset(info);
1330 par->Architecture = nvidia_get_arch(info);
1331
1332 if (par->Architecture == 0) {
1333 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1334 goto err_out_arch;
1335 }
1336
1337 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1338
1339 if (NVCommonSetup(info))
1340 goto err_out_arch;
1341
1342 par->FbAddress = nvidiafb_fix.smem_start;
1343 par->FbMapSize = par->RamAmountKBytes * 1024;
1344 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1345 par->FbMapSize = vram * 1024 * 1024;
1346
1347
1348 if (par->FbMapSize > 64 * 1024 * 1024)
1349 par->FbMapSize = 64 * 1024 * 1024;
1350
1351 if(par->Architecture >= NV_ARCH_40)
1352 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1353 else
1354 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1355 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1356 16 * 1024;
1357 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1358 par->CursorStart = par->FbUsableSize + (32 * 1024);
1359
1360 info->screen_base = ioremap_wc(nvidiafb_fix.smem_start,
1361 par->FbMapSize);
1362 info->screen_size = par->FbUsableSize;
1363 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1364
1365 if (!info->screen_base) {
1366 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1367 goto err_out_free_base1;
1368 }
1369
1370 par->FbStart = info->screen_base;
1371
1372 if (!nomtrr)
1373 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
1374 par->RamAmountKBytes * 1024);
1375
1376 info->fbops = &nvidia_fb_ops;
1377 info->fix = nvidiafb_fix;
1378
1379 if (nvidia_set_fbinfo(info) < 0) {
1380 printk(KERN_ERR PFX "error setting initial video mode\n");
1381 goto err_out_iounmap_fb;
1382 }
1383
1384 nvidia_save_vga(par, &par->SavedReg);
1385
1386 pci_set_drvdata(pd, info);
1387
1388 if (backlight)
1389 nvidia_bl_init(par);
1390
1391 if (register_framebuffer(info) < 0) {
1392 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1393 goto err_out_iounmap_fb;
1394 }
1395
1396
1397 printk(KERN_INFO PFX
1398 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1399 info->fix.id,
1400 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1401
1402 NVTRACE_LEAVE();
1403 return 0;
1404
1405err_out_iounmap_fb:
1406 iounmap(info->screen_base);
1407err_out_free_base1:
1408 fb_destroy_modedb(info->monspecs.modedb);
1409 nvidia_delete_i2c_busses(par);
1410err_out_arch:
1411 iounmap(par->REGS);
1412 err_out_free_base0:
1413 pci_release_regions(pd);
1414err_out_enable:
1415 kfree(info->pixmap.addr);
1416err_out_kfree:
1417 framebuffer_release(info);
1418err_out:
1419 return -ENODEV;
1420}
1421
1422static void nvidiafb_remove(struct pci_dev *pd)
1423{
1424 struct fb_info *info = pci_get_drvdata(pd);
1425 struct nvidia_par *par = info->par;
1426
1427 NVTRACE_ENTER();
1428
1429 unregister_framebuffer(info);
1430
1431 nvidia_bl_exit(par);
1432 arch_phys_wc_del(par->wc_cookie);
1433 iounmap(info->screen_base);
1434 fb_destroy_modedb(info->monspecs.modedb);
1435 nvidia_delete_i2c_busses(par);
1436 iounmap(par->REGS);
1437 pci_release_regions(pd);
1438 kfree(info->pixmap.addr);
1439 framebuffer_release(info);
1440 NVTRACE_LEAVE();
1441}
1442
1443
1444
1445
1446
1447
1448
1449#ifndef MODULE
1450static int nvidiafb_setup(char *options)
1451{
1452 char *this_opt;
1453
1454 NVTRACE_ENTER();
1455 if (!options || !*options)
1456 return 0;
1457
1458 while ((this_opt = strsep(&options, ",")) != NULL) {
1459 if (!strncmp(this_opt, "forceCRTC", 9)) {
1460 char *p;
1461
1462 p = this_opt + 9;
1463 if (!*p || !*(++p))
1464 continue;
1465 forceCRTC = *p - '0';
1466 if (forceCRTC < 0 || forceCRTC > 1)
1467 forceCRTC = -1;
1468 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1469 flatpanel = 1;
1470 } else if (!strncmp(this_opt, "hwcur", 5)) {
1471 hwcur = 1;
1472 } else if (!strncmp(this_opt, "noaccel", 6)) {
1473 noaccel = 1;
1474 } else if (!strncmp(this_opt, "noscale", 7)) {
1475 noscale = 1;
1476 } else if (!strncmp(this_opt, "reverse_i2c", 11)) {
1477 reverse_i2c = 1;
1478 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1479 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1480 } else if (!strncmp(this_opt, "vram:", 5)) {
1481 vram = simple_strtoul(this_opt+5, NULL, 0);
1482 } else if (!strncmp(this_opt, "backlight:", 10)) {
1483 backlight = simple_strtoul(this_opt+10, NULL, 0);
1484 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1485 nomtrr = true;
1486 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1487 fpdither = simple_strtol(this_opt+9, NULL, 0);
1488 } else if (!strncmp(this_opt, "bpp:", 4)) {
1489 bpp = simple_strtoul(this_opt+4, NULL, 0);
1490 } else
1491 mode_option = this_opt;
1492 }
1493 NVTRACE_LEAVE();
1494 return 0;
1495}
1496#endif
1497
1498static struct pci_driver nvidiafb_driver = {
1499 .name = "nvidiafb",
1500 .id_table = nvidiafb_pci_tbl,
1501 .probe = nvidiafb_probe,
1502 .suspend = nvidiafb_suspend,
1503 .resume = nvidiafb_resume,
1504 .remove = nvidiafb_remove,
1505};
1506
1507
1508
1509
1510
1511
1512
1513static int nvidiafb_init(void)
1514{
1515#ifndef MODULE
1516 char *option = NULL;
1517
1518 if (fb_get_options("nvidiafb", &option))
1519 return -ENODEV;
1520 nvidiafb_setup(option);
1521#endif
1522 return pci_register_driver(&nvidiafb_driver);
1523}
1524
1525module_init(nvidiafb_init);
1526
1527static void __exit nvidiafb_exit(void)
1528{
1529 pci_unregister_driver(&nvidiafb_driver);
1530}
1531
1532module_exit(nvidiafb_exit);
1533
1534module_param(flatpanel, int, 0);
1535MODULE_PARM_DESC(flatpanel,
1536 "Enables experimental flat panel support for some chipsets. "
1537 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1538module_param(fpdither, int, 0);
1539MODULE_PARM_DESC(fpdither,
1540 "Enables dithering of flat panel for 6 bits panels. "
1541 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1542module_param(hwcur, int, 0);
1543MODULE_PARM_DESC(hwcur,
1544 "Enables hardware cursor implementation. (0 or 1=enabled) "
1545 "(default=0)");
1546module_param(noaccel, int, 0);
1547MODULE_PARM_DESC(noaccel,
1548 "Disables hardware acceleration. (0 or 1=disable) "
1549 "(default=0)");
1550module_param(noscale, int, 0);
1551MODULE_PARM_DESC(noscale,
1552 "Disables screen scaling. (0 or 1=disable) "
1553 "(default=0, do scaling)");
1554module_param(paneltweak, int, 0);
1555MODULE_PARM_DESC(paneltweak,
1556 "Tweak display settings for flatpanels. "
1557 "(default=0, no tweaks)");
1558module_param(forceCRTC, int, 0);
1559MODULE_PARM_DESC(forceCRTC,
1560 "Forces usage of a particular CRTC in case autodetection "
1561 "fails. (0 or 1) (default=autodetect)");
1562module_param(vram, int, 0);
1563MODULE_PARM_DESC(vram,
1564 "amount of framebuffer memory to remap in MiB"
1565 "(default=0 - remap entire memory)");
1566module_param(mode_option, charp, 0);
1567MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1568module_param(bpp, int, 0);
1569MODULE_PARM_DESC(bpp, "pixel width in bits"
1570 "(default=8)");
1571module_param(reverse_i2c, int, 0);
1572MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
1573module_param(nomtrr, bool, false);
1574MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1575 "(default=0)");
1576
1577MODULE_AUTHOR("Antonino Daplas");
1578MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1579MODULE_LICENSE("GPL");
1580
