1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Rahul Sharma <rahul.sharma@samsung.com> 5 * 6 * Provides Constants for Exynos5260 clocks. 7 */ 8 9#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 10#define _DT_BINDINGS_CLK_EXYNOS5260_H 11 12/* Clock names: <cmu><type><IP> */ 13 14/* List Of Clocks For CMU_TOP */ 15 16#define TOP_FOUT_DISP_PLL 1 17#define TOP_FOUT_AUD_PLL 2 18#define TOP_MOUT_AUDTOP_PLL_USER 3 19#define TOP_MOUT_AUD_PLL 4 20#define TOP_MOUT_DISP_PLL 5 21#define TOP_MOUT_BUSTOP_PLL_USER 6 22#define TOP_MOUT_MEMTOP_PLL_USER 7 23#define TOP_MOUT_MEDIATOP_PLL_USER 8 24#define TOP_MOUT_DISP_DISP_333 9 25#define TOP_MOUT_ACLK_DISP_333 10 26#define TOP_MOUT_DISP_DISP_222 11 27#define TOP_MOUT_ACLK_DISP_222 12 28#define TOP_MOUT_DISP_MEDIA_PIXEL 13 29#define TOP_MOUT_FIMD1 14 30#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 31#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 32#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 33#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 34#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 35#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 36#define TOP_MOUT_BUS4_BUSTOP_100 21 37#define TOP_MOUT_BUS4_BUSTOP_400 22 38#define TOP_MOUT_BUS3_BUSTOP_100 23 39#define TOP_MOUT_BUS3_BUSTOP_400 24 40#define TOP_MOUT_BUS2_BUSTOP_400 25 41#define TOP_MOUT_BUS2_BUSTOP_100 26 42#define TOP_MOUT_BUS1_BUSTOP_100 27 43#define TOP_MOUT_BUS1_BUSTOP_400 28 44#define TOP_MOUT_SCLK_FSYS_USB 29 45#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 46#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 47#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 48#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 49#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 50#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 51#define TOP_MOUT_ACLK_ISP1_266 36 52#define TOP_MOUT_ISP1_MEDIA_266 37 53#define TOP_MOUT_ACLK_ISP1_400 38 54#define TOP_MOUT_ISP1_MEDIA_400 39 55#define TOP_MOUT_SCLK_ISP1_SPI0 40 56#define TOP_MOUT_SCLK_ISP1_SPI1 41 57#define TOP_MOUT_SCLK_ISP1_UART 42 58#define TOP_MOUT_SCLK_ISP1_SENSOR2 43 59#define TOP_MOUT_SCLK_ISP1_SENSOR1 44 60#define TOP_MOUT_SCLK_ISP1_SENSOR0 45 61#define TOP_MOUT_ACLK_MFC_333 46 62#define TOP_MOUT_MFC_BUSTOP_333 47 63#define TOP_MOUT_ACLK_G2D_333 48 64#define TOP_MOUT_G2D_BUSTOP_333 49 65#define TOP_MOUT_ACLK_GSCL_FIMC 50 66#define TOP_MOUT_GSCL_BUSTOP_FIMC 51 67#define TOP_MOUT_ACLK_GSCL_333 52 68#define TOP_MOUT_GSCL_BUSTOP_333 53 69#define TOP_MOUT_ACLK_GSCL_400 54 70#define TOP_MOUT_M2M_MEDIATOP_400 55 71#define TOP_DOUT_ACLK_MFC_333 56 72#define TOP_DOUT_ACLK_G2D_333 57 73#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 74#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 75#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 76#define TOP_DOUT_ACLK_GSCL_FIMC 61 77#define TOP_DOUT_ACLK_GSCL_400 62 78#define TOP_DOUT_ACLK_GSCL_333 63 79#define TOP_DOUT_SCLK_ISP1_SPI0_B 64 80#define TOP_DOUT_SCLK_ISP1_SPI0_A 65 81#define TOP_DOUT_ACLK_ISP1_400 66 82#define TOP_DOUT_ACLK_ISP1_266 67 83#define TOP_DOUT_SCLK_ISP1_UART 68 84#define TOP_DOUT_SCLK_ISP1_SPI1_B 69 85#define TOP_DOUT_SCLK_ISP1_SPI1_A 70 86#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 87#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 88#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 89#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 90#define TOP_DOUT_SCLK_DISP_PIXEL 75 91#define TOP_DOUT_ACLK_DISP_222 76 92#define TOP_DOUT_ACLK_DISP_333 77 93#define TOP_DOUT_ACLK_BUS4_100 78 94#define TOP_DOUT_ACLK_BUS4_400 79 95#define TOP_DOUT_ACLK_BUS3_100 80 96#define TOP_DOUT_ACLK_BUS3_400 81 97#define TOP_DOUT_ACLK_BUS2_100 82 98#define TOP_DOUT_ACLK_BUS2_400 83 99#define TOP_DOUT_ACLK_BUS1_100 84 100#define TOP_DOUT_ACLK_BUS1_400 85 101#define TOP_DOUT_SCLK_PERI_SPI1_B 86 102#define TOP_DOUT_SCLK_PERI_SPI1_A 87 103#define TOP_DOUT_SCLK_PERI_SPI0_B 88 104#define TOP_DOUT_SCLK_PERI_SPI0_A 89 105#define TOP_DOUT_SCLK_PERI_UART0 90 106#define TOP_DOUT_SCLK_PERI_UART2 91 107#define TOP_DOUT_SCLK_PERI_UART1 92 108#define TOP_DOUT_SCLK_PERI_SPI2_B 93 109#define TOP_DOUT_SCLK_PERI_SPI2_A 94 110#define TOP_DOUT_ACLK_PERI_AUD 95 111#define TOP_DOUT_ACLK_PERI_66 96 112#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 113#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 114#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 115#define TOP_DOUT_ACLK_FSYS_200 100 116#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 117#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 118#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 119#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 120#define TOP_SCLK_FIMD1 105 121#define TOP_SCLK_MMC2 106 122#define TOP_SCLK_MMC1 107 123#define TOP_SCLK_MMC0 108 124#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 125#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 126#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 127#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 128#define phyclk_hdmi_phy_tmds_clko 113 129#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 130#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 131#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 132#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 133#define PHYCLK_DPTX_PHY_CLK_DIV2 118 134#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 135#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 136#define PHYCLK_USBHOST20_PHY_FREECLK 121 137#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 138#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 139#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 140#define TOP_NR_CLK 125 141 142 143/* List Of Clocks For CMU_EGL */ 144 145#define EGL_FOUT_EGL_PLL 1 146#define EGL_FOUT_EGL_DPLL 2 147#define EGL_MOUT_EGL_B 3 148#define EGL_MOUT_EGL_PLL 4 149#define EGL_DOUT_EGL_PLL 5 150#define EGL_DOUT_EGL_PCLK_DBG 6 151#define EGL_DOUT_EGL_ATCLK 7 152#define EGL_DOUT_PCLK_EGL 8 153#define EGL_DOUT_ACLK_EGL 9 154#define EGL_DOUT_EGL2 10 155#define EGL_DOUT_EGL1 11 156#define EGL_NR_CLK 12 157 158 159/* List Of Clocks For CMU_KFC */ 160 161#define KFC_FOUT_KFC_PLL 1 162#define KFC_MOUT_KFC_PLL 2 163#define KFC_MOUT_KFC 3 164#define KFC_DOUT_KFC_PLL 4 165#define KFC_DOUT_PCLK_KFC 5 166#define KFC_DOUT_ACLK_KFC 6 167#define KFC_DOUT_KFC_PCLK_DBG 7 168#define KFC_DOUT_KFC_ATCLK 8 169#define KFC_DOUT_KFC2 9 170#define KFC_DOUT_KFC1 10 171#define KFC_NR_CLK 11 172 173 174/* List Of Clocks For CMU_MIF */ 175 176#define MIF_FOUT_MEM_PLL 1 177#define MIF_FOUT_MEDIA_PLL 2 178#define MIF_FOUT_BUS_PLL 3 179#define MIF_MOUT_CLK2X_PHY 4 180#define MIF_MOUT_MIF_DREX2X 5 181#define MIF_MOUT_CLKM_PHY 6 182#define MIF_MOUT_MIF_DREX 7 183#define MIF_MOUT_MEDIA_PLL 8 184#define MIF_MOUT_BUS_PLL 9 185#define MIF_MOUT_MEM_PLL 10 186#define MIF_DOUT_ACLK_BUS_100 11 187#define MIF_DOUT_ACLK_BUS_200 12 188#define MIF_DOUT_ACLK_MIF_466 13 189#define MIF_DOUT_CLK2X_PHY 14 190#define MIF_DOUT_CLKM_PHY 15 191#define MIF_DOUT_BUS_PLL 16 192#define MIF_DOUT_MEM_PLL 17 193#define MIF_DOUT_MEDIA_PLL 18 194#define MIF_CLK_LPDDR3PHY_WRAP1 19 195#define MIF_CLK_LPDDR3PHY_WRAP0 20 196#define MIF_CLK_MONOCNT 21 197#define MIF_CLK_MIF_RTC 22 198#define MIF_CLK_DREX1 23 199#define MIF_CLK_DREX0 24 200#define MIF_CLK_INTMEM 25 201#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 202#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 203#define MIF_NR_CLK 28 204 205 206/* List Of Clocks For CMU_G3D */ 207 208#define G3D_FOUT_G3D_PLL 1 209#define G3D_MOUT_G3D_PLL 2 210#define G3D_DOUT_PCLK_G3D 3 211#define G3D_DOUT_ACLK_G3D 4 212#define G3D_CLK_G3D_HPM 5 213#define G3D_CLK_G3D 6 214#define G3D_NR_CLK 7 215 216 217/* List Of Clocks For CMU_AUD */ 218 219#define AUD_MOUT_SCLK_AUD_PCM 1 220#define AUD_MOUT_SCLK_AUD_I2S 2 221#define AUD_MOUT_AUD_PLL_USER 3 222#define AUD_DOUT_ACLK_AUD_131 4 223#define AUD_DOUT_SCLK_AUD_UART 5 224#define AUD_DOUT_SCLK_AUD_PCM 6 225#define AUD_DOUT_SCLK_AUD_I2S 7 226#define AUD_CLK_AUD_UART 8 227#define AUD_CLK_PCM 9 228#define AUD_CLK_I2S 10 229#define AUD_CLK_DMAC 11 230#define AUD_CLK_SRAMC 12 231#define AUD_SCLK_AUD_UART 13 232#define AUD_SCLK_PCM 14 233#define AUD_SCLK_I2S 15 234#define AUD_NR_CLK 16 235 236 237/* List Of Clocks For CMU_MFC */ 238 239#define MFC_MOUT_ACLK_MFC_333_USER 1 240#define MFC_DOUT_PCLK_MFC_83 2 241#define MFC_CLK_MFC 3 242#define MFC_CLK_SMMU2_MFCM1 4 243#define MFC_CLK_SMMU2_MFCM0 5 244#define MFC_NR_CLK 6 245 246 247/* List Of Clocks For CMU_GSCL */ 248 249#define GSCL_MOUT_ACLK_CSIS 1 250#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 251#define GSCL_MOUT_ACLK_M2M_400_USER 3 252#define GSCL_MOUT_ACLK_GSCL_333_USER 4 253#define GSCL_DOUT_ACLK_CSIS_200 5 254#define GSCL_DOUT_PCLK_M2M_100 6 255#define GSCL_CLK_PIXEL_GSCL1 7 256#define GSCL_CLK_PIXEL_GSCL0 8 257#define GSCL_CLK_MSCL1 9 258#define GSCL_CLK_MSCL0 10 259#define GSCL_CLK_GSCL1 11 260#define GSCL_CLK_GSCL0 12 261#define GSCL_CLK_FIMC_LITE_D 13 262#define GSCL_CLK_FIMC_LITE_B 14 263#define GSCL_CLK_FIMC_LITE_A 15 264#define GSCL_CLK_CSIS1 16 265#define GSCL_CLK_CSIS0 17 266#define GSCL_CLK_SMMU3_LITE_D 18 267#define GSCL_CLK_SMMU3_LITE_B 19 268#define GSCL_CLK_SMMU3_LITE_A 20 269#define GSCL_CLK_SMMU3_GSCL0 21 270#define GSCL_CLK_SMMU3_GSCL1 22 271#define GSCL_CLK_SMMU3_MSCL0 23 272#define GSCL_CLK_SMMU3_MSCL1 24 273#define GSCL_SCLK_CSIS1_WRAP 25 274#define GSCL_SCLK_CSIS0_WRAP 26 275#define GSCL_NR_CLK 27 276 277 278/* List Of Clocks For CMU_FSYS */ 279 280#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 281#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 282#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 283#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 284#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 285#define FSYS_CLK_TSI 6 286#define FSYS_CLK_USBLINK 7 287#define FSYS_CLK_USBHOST20 8 288#define FSYS_CLK_USBDRD30 9 289#define FSYS_CLK_SROMC 10 290#define FSYS_CLK_PDMA 11 291#define FSYS_CLK_MMC2 12 292#define FSYS_CLK_MMC1 13 293#define FSYS_CLK_MMC0 14 294#define FSYS_CLK_RTIC 15 295#define FSYS_CLK_SMMU_RTIC 16 296#define FSYS_PHYCLK_USBDRD30 17 297#define FSYS_PHYCLK_USBHOST20 18 298#define FSYS_NR_CLK 19 299 300 301/* List Of Clocks For CMU_PERI */ 302 303#define PERI_MOUT_SCLK_SPDIF 1 304#define PERI_MOUT_SCLK_I2SCOD 2 305#define PERI_MOUT_SCLK_PCM 3 306#define PERI_DOUT_I2S 4 307#define PERI_DOUT_PCM 5 308#define PERI_CLK_WDT_KFC 6 309#define PERI_CLK_WDT_EGL 7 310#define PERI_CLK_HSIC3 8 311#define PERI_CLK_HSIC2 9 312#define PERI_CLK_HSIC1 10 313#define PERI_CLK_HSIC0 11 314#define PERI_CLK_PCM 12 315#define PERI_CLK_MCT 13 316#define PERI_CLK_I2S 14 317#define PERI_CLK_I2CHDMI 15 318#define PERI_CLK_I2C7 16 319#define PERI_CLK_I2C6 17 320#define PERI_CLK_I2C5 18 321#define PERI_CLK_I2C4 19 322#define PERI_CLK_I2C9 20 323#define PERI_CLK_I2C8 21 324#define PERI_CLK_I2C11 22 325#define PERI_CLK_I2C10 23 326#define PERI_CLK_HDMICEC 24 327#define PERI_CLK_EFUSE_WRITER 25 328#define PERI_CLK_ABB 26 329#define PERI_CLK_UART2 27 330#define PERI_CLK_UART1 28 331#define PERI_CLK_UART0 29 332#define PERI_CLK_ADC 30 333#define PERI_CLK_TMU4 31 334#define PERI_CLK_TMU3 32 335#define PERI_CLK_TMU2 33 336#define PERI_CLK_TMU1 34 337#define PERI_CLK_TMU0 35 338#define PERI_CLK_SPI2 36 339#define PERI_CLK_SPI1 37 340#define PERI_CLK_SPI0 38 341#define PERI_CLK_SPDIF 39 342#define PERI_CLK_PWM 40 343#define PERI_CLK_UART4 41 344#define PERI_CLK_CHIPID 42 345#define PERI_CLK_PROVKEY0 43 346#define PERI_CLK_PROVKEY1 44 347#define PERI_CLK_SECKEY 45 348#define PERI_CLK_TOP_RTC 46 349#define PERI_CLK_TZPC10 47 350#define PERI_CLK_TZPC9 48 351#define PERI_CLK_TZPC8 49 352#define PERI_CLK_TZPC7 50 353#define PERI_CLK_TZPC6 51 354#define PERI_CLK_TZPC5 52 355#define PERI_CLK_TZPC4 53 356#define PERI_CLK_TZPC3 54 357#define PERI_CLK_TZPC2 55 358#define PERI_CLK_TZPC1 56 359#define PERI_CLK_TZPC0 57 360#define PERI_SCLK_UART2 58 361#define PERI_SCLK_UART1 59 362#define PERI_SCLK_UART0 60 363#define PERI_SCLK_SPI2 61 364#define PERI_SCLK_SPI1 62 365#define PERI_SCLK_SPI0 63 366#define PERI_SCLK_SPDIF 64 367#define PERI_SCLK_I2S 65 368#define PERI_SCLK_PCM1 66 369#define PERI_NR_CLK 67 370 371 372/* List Of Clocks For CMU_DISP */ 373 374#define DISP_MOUT_SCLK_HDMI_SPDIF 1 375#define DISP_MOUT_SCLK_HDMI_PIXEL 2 376#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 377#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 378#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 379#define DISP_MOUT_HDMI_PHY_PIXEL 6 380#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 381#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 382#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 383#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 384#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 385#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 386#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 387#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 388#define DISP_MOUT_ACLK_DISP_222_USER 15 389#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 390#define DISP_MOUT_ACLK_DISP_333_USER 17 391#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 392#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 393#define DISP_DOUT_PCLK_DISP_111 20 394#define DISP_CLK_SMMU_TV 21 395#define DISP_CLK_SMMU_FIMD1M1 22 396#define DISP_CLK_SMMU_FIMD1M0 23 397#define DISP_CLK_PIXEL_MIXER 24 398#define DISP_CLK_PIXEL_DISP 25 399#define DISP_CLK_MIXER 26 400#define DISP_CLK_MIPIPHY 27 401#define DISP_CLK_HDMIPHY 28 402#define DISP_CLK_HDMI 29 403#define DISP_CLK_FIMD1 30 404#define DISP_CLK_DSIM1 31 405#define DISP_CLK_DPPHY 32 406#define DISP_CLK_DP 33 407#define DISP_SCLK_PIXEL 34 408#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 409#define DISP_NR_CLK 36 410 411 412/* List Of Clocks For CMU_G2D */ 413 414#define G2D_MOUT_ACLK_G2D_333_USER 1 415#define G2D_DOUT_PCLK_G2D_83 2 416#define G2D_CLK_SMMU3_JPEG 3 417#define G2D_CLK_MDMA 4 418#define G2D_CLK_JPEG 5 419#define G2D_CLK_G2D 6 420#define G2D_CLK_SSS 7 421#define G2D_CLK_SLIM_SSS 8 422#define G2D_CLK_SMMU_SLIM_SSS 9 423#define G2D_CLK_SMMU_SSS 10 424#define G2D_CLK_SMMU_MDMA 11 425#define G2D_CLK_SMMU3_G2D 12 426#define G2D_NR_CLK 13 427 428 429/* List Of Clocks For CMU_ISP */ 430 431#define ISP_MOUT_ISP_400_USER 1 432#define ISP_MOUT_ISP_266_USER 2 433#define ISP_DOUT_SCLK_MPWM 3 434#define ISP_DOUT_CA5_PCLKDBG 4 435#define ISP_DOUT_CA5_ATCLKIN 5 436#define ISP_DOUT_PCLK_ISP_133 6 437#define ISP_DOUT_PCLK_ISP_66 7 438#define ISP_CLK_GIC 8 439#define ISP_CLK_WDT 9 440#define ISP_CLK_UART 10 441#define ISP_CLK_SPI1 11 442#define ISP_CLK_SPI0 12 443#define ISP_CLK_SMMU_SCALERP 13 444#define ISP_CLK_SMMU_SCALERC 14 445#define ISP_CLK_SMMU_ISPCX 15 446#define ISP_CLK_SMMU_ISP 16 447#define ISP_CLK_SMMU_FD 17 448#define ISP_CLK_SMMU_DRC 18 449#define ISP_CLK_PWM 19 450#define ISP_CLK_MTCADC 20 451#define ISP_CLK_MPWM 21 452#define ISP_CLK_MCUCTL 22 453#define ISP_CLK_I2C1 23 454#define ISP_CLK_I2C0 24 455#define ISP_CLK_FIMC_SCALERP 25 456#define ISP_CLK_FIMC_SCALERC 26 457#define ISP_CLK_FIMC 27 458#define ISP_CLK_FIMC_FD 28 459#define ISP_CLK_FIMC_DRC 29 460#define ISP_CLK_CA5 30 461#define ISP_SCLK_SPI0_EXT 31 462#define ISP_SCLK_SPI1_EXT 32 463#define ISP_SCLK_UART_EXT 33 464#define ISP_NR_CLK 34 465 466#endif 467