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23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
26
27#include <linux/mod_devicetable.h>
28
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/list.h>
33#include <linux/compiler.h>
34#include <linux/errno.h>
35#include <linux/kobject.h>
36#include <linux/atomic.h>
37#include <linux/device.h>
38#include <linux/interrupt.h>
39#include <linux/io.h>
40#include <linux/resource_ext.h>
41#include <uapi/linux/pci.h>
42
43#include <linux/pci_ids.h>
44
45#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52
53
54
55
56
57
58
59
60
61
62
63
64#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65
66#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67
68
69struct pci_slot {
70 struct pci_bus *bus;
71 struct list_head list;
72 struct hotplug_slot *hotplug;
73 unsigned char number;
74 struct kobject kobj;
75};
76
77static inline const char *pci_slot_name(const struct pci_slot *slot)
78{
79 return kobject_name(&slot->kobj);
80}
81
82
83enum pci_mmap_state {
84 pci_mmap_io,
85 pci_mmap_mem
86};
87
88
89enum {
90
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93
94
95 PCI_ROM_RESOURCE,
96
97
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
103
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110
111 PCI_NUM_RESOURCES,
112
113
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
115};
116
117
118
119
120
121
122
123
124
125
126
127
128enum pci_interrupt_pin {
129 PCI_INTERRUPT_UNKNOWN,
130 PCI_INTERRUPT_INTA,
131 PCI_INTERRUPT_INTB,
132 PCI_INTERRUPT_INTC,
133 PCI_INTERRUPT_INTD,
134};
135
136
137#define PCI_NUM_INTX 4
138
139
140
141
142
143typedef int __bitwise pci_power_t;
144
145#define PCI_D0 ((pci_power_t __force) 0)
146#define PCI_D1 ((pci_power_t __force) 1)
147#define PCI_D2 ((pci_power_t __force) 2)
148#define PCI_D3hot ((pci_power_t __force) 3)
149#define PCI_D3cold ((pci_power_t __force) 4)
150#define PCI_UNKNOWN ((pci_power_t __force) 5)
151#define PCI_POWER_ERROR ((pci_power_t __force) -1)
152
153
154extern const char *pci_power_names[];
155
156static inline const char *pci_power_name(pci_power_t state)
157{
158 return pci_power_names[1 + (__force int) state];
159}
160
161
162
163
164
165
166
167
168typedef unsigned int __bitwise pci_channel_state_t;
169
170enum pci_channel_state {
171
172 pci_channel_io_normal = (__force pci_channel_state_t) 1,
173
174
175 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
176
177
178 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
179};
180
181typedef unsigned int __bitwise pcie_reset_state_t;
182
183enum pcie_reset_state {
184
185 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
186
187
188 pcie_warm_reset = (__force pcie_reset_state_t) 2,
189
190
191 pcie_hot_reset = (__force pcie_reset_state_t) 3
192};
193
194typedef unsigned short __bitwise pci_dev_flags_t;
195enum pci_dev_flags {
196
197 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
198
199 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
200
201 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
202
203 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
204
205 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
206
207 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
208
209 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
210
211 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
212
213 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
214
215 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
216
217 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
218};
219
220enum pci_irq_reroute_variant {
221 INTEL_IRQ_REROUTE_VARIANT = 1,
222 MAX_IRQ_REROUTE_VARIANTS = 3
223};
224
225typedef unsigned short __bitwise pci_bus_flags_t;
226enum pci_bus_flags {
227 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
228 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
229 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
230 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
231};
232
233
234enum pcie_link_width {
235 PCIE_LNK_WIDTH_RESRV = 0x00,
236 PCIE_LNK_X1 = 0x01,
237 PCIE_LNK_X2 = 0x02,
238 PCIE_LNK_X4 = 0x04,
239 PCIE_LNK_X8 = 0x08,
240 PCIE_LNK_X12 = 0x0c,
241 PCIE_LNK_X16 = 0x10,
242 PCIE_LNK_X32 = 0x20,
243 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
244};
245
246
247enum pci_bus_speed {
248 PCI_SPEED_33MHz = 0x00,
249 PCI_SPEED_66MHz = 0x01,
250 PCI_SPEED_66MHz_PCIX = 0x02,
251 PCI_SPEED_100MHz_PCIX = 0x03,
252 PCI_SPEED_133MHz_PCIX = 0x04,
253 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
254 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
255 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
256 PCI_SPEED_66MHz_PCIX_266 = 0x09,
257 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
258 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
259 AGP_UNKNOWN = 0x0c,
260 AGP_1X = 0x0d,
261 AGP_2X = 0x0e,
262 AGP_4X = 0x0f,
263 AGP_8X = 0x10,
264 PCI_SPEED_66MHz_PCIX_533 = 0x11,
265 PCI_SPEED_100MHz_PCIX_533 = 0x12,
266 PCI_SPEED_133MHz_PCIX_533 = 0x13,
267 PCIE_SPEED_2_5GT = 0x14,
268 PCIE_SPEED_5_0GT = 0x15,
269 PCIE_SPEED_8_0GT = 0x16,
270 PCIE_SPEED_16_0GT = 0x17,
271 PCIE_SPEED_32_0GT = 0x18,
272 PCI_SPEED_UNKNOWN = 0xff,
273};
274
275enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
276enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
277
278struct pci_cap_saved_data {
279 u16 cap_nr;
280 bool cap_extended;
281 unsigned int size;
282 u32 data[0];
283};
284
285struct pci_cap_saved_state {
286 struct hlist_node next;
287 struct pci_cap_saved_data cap;
288};
289
290struct irq_affinity;
291struct pcie_link_state;
292struct pci_vpd;
293struct pci_sriov;
294struct pci_p2pdma;
295
296
297struct pci_dev {
298 struct list_head bus_list;
299 struct pci_bus *bus;
300 struct pci_bus *subordinate;
301
302 void *sysdata;
303 struct proc_dir_entry *procent;
304 struct pci_slot *slot;
305
306 unsigned int devfn;
307 unsigned short vendor;
308 unsigned short device;
309 unsigned short subsystem_vendor;
310 unsigned short subsystem_device;
311 unsigned int class;
312 u8 revision;
313 u8 hdr_type;
314#ifdef CONFIG_PCIEAER
315 u16 aer_cap;
316 struct aer_stats *aer_stats;
317#endif
318 u8 pcie_cap;
319 u8 msi_cap;
320 u8 msix_cap;
321 u8 pcie_mpss:3;
322 u8 rom_base_reg;
323 u8 pin;
324 u16 pcie_flags_reg;
325 unsigned long *dma_alias_mask;
326
327 struct pci_driver *driver;
328 u64 dma_mask;
329
330
331
332
333
334 struct device_dma_parameters dma_parms;
335
336 pci_power_t current_state;
337
338
339 unsigned int imm_ready:1;
340 u8 pm_cap;
341 unsigned int pme_support:5;
342
343 unsigned int pme_poll:1;
344 unsigned int d1_support:1;
345 unsigned int d2_support:1;
346 unsigned int no_d1d2:1;
347 unsigned int no_d3cold:1;
348 unsigned int bridge_d3:1;
349 unsigned int d3cold_allowed:1;
350 unsigned int mmio_always_on:1;
351
352 unsigned int wakeup_prepared:1;
353 unsigned int runtime_d3cold:1;
354
355
356
357 unsigned int skip_bus_pm:1;
358 unsigned int ignore_hotplug:1;
359 unsigned int hotplug_user_indicators:1;
360
361
362 unsigned int clear_retrain_link:1;
363
364 unsigned int d3_delay;
365 unsigned int d3cold_delay;
366
367#ifdef CONFIG_PCIEASPM
368 struct pcie_link_state *link_state;
369 unsigned int ltr_path:1;
370
371#endif
372 unsigned int eetlp_prefix_path:1;
373
374 pci_channel_state_t error_state;
375 struct device dev;
376
377 int cfg_size;
378
379
380
381
382
383 unsigned int irq;
384 struct resource resource[DEVICE_COUNT_RESOURCE];
385
386 bool match_driver;
387
388 unsigned int transparent:1;
389 unsigned int io_window:1;
390 unsigned int pref_window:1;
391 unsigned int pref_64_window:1;
392 unsigned int multifunction:1;
393
394 unsigned int is_busmaster:1;
395 unsigned int no_msi:1;
396 unsigned int no_64bit_msi:1;
397 unsigned int block_cfg_access:1;
398 unsigned int broken_parity_status:1;
399 unsigned int irq_reroute_variant:2;
400 unsigned int msi_enabled:1;
401 unsigned int msix_enabled:1;
402 unsigned int ari_enabled:1;
403 unsigned int ats_enabled:1;
404 unsigned int pasid_enabled:1;
405 unsigned int pri_enabled:1;
406 unsigned int is_managed:1;
407 unsigned int needs_freset:1;
408 unsigned int state_saved:1;
409 unsigned int is_physfn:1;
410 unsigned int is_virtfn:1;
411 unsigned int reset_fn:1;
412 unsigned int is_hotplug_bridge:1;
413 unsigned int shpc_managed:1;
414 unsigned int is_thunderbolt:1;
415
416
417
418
419
420
421
422 unsigned int untrusted:1;
423 unsigned int __aer_firmware_first_valid:1;
424 unsigned int __aer_firmware_first:1;
425 unsigned int broken_intx_masking:1;
426 unsigned int io_window_1k:1;
427 unsigned int irq_managed:1;
428 unsigned int non_compliant_bars:1;
429 unsigned int is_probed:1;
430 unsigned int link_active_reporting:1;
431 unsigned int no_vf_scan:1;
432 pci_dev_flags_t dev_flags;
433 atomic_t enable_cnt;
434
435 u32 saved_config_space[16];
436 struct hlist_head saved_cap_space;
437 struct bin_attribute *rom_attr;
438 int rom_attr_enabled;
439 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
440 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
441
442#ifdef CONFIG_HOTPLUG_PCI_PCIE
443 unsigned int broken_cmd_compl:1;
444#endif
445#ifdef CONFIG_PCIE_PTM
446 unsigned int ptm_root:1;
447 unsigned int ptm_enabled:1;
448 u8 ptm_granularity;
449#endif
450#ifdef CONFIG_PCI_MSI
451 const struct attribute_group **msi_irq_groups;
452#endif
453 struct pci_vpd *vpd;
454#ifdef CONFIG_PCIE_DPC
455 u16 dpc_cap;
456 unsigned int dpc_rp_extensions:1;
457 u8 dpc_rp_log_size;
458#endif
459#ifdef CONFIG_PCI_ATS
460 union {
461 struct pci_sriov *sriov;
462 struct pci_dev *physfn;
463 };
464 u16 ats_cap;
465 u8 ats_stu;
466#endif
467#ifdef CONFIG_PCI_PRI
468 u16 pri_cap;
469 u32 pri_reqs_alloc;
470 unsigned int pasid_required:1;
471#endif
472#ifdef CONFIG_PCI_PASID
473 u16 pasid_cap;
474 u16 pasid_features;
475#endif
476#ifdef CONFIG_PCI_P2PDMA
477 struct pci_p2pdma *p2pdma;
478#endif
479 phys_addr_t rom;
480 size_t romlen;
481 char *driver_override;
482
483 unsigned long priv_flags;
484};
485
486static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
487{
488#ifdef CONFIG_PCI_IOV
489 if (dev->is_virtfn)
490 dev = dev->physfn;
491#endif
492 return dev;
493}
494
495struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
496
497#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
498#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
499
500static inline int pci_channel_offline(struct pci_dev *pdev)
501{
502 return (pdev->error_state != pci_channel_io_normal);
503}
504
505struct pci_host_bridge {
506 struct device dev;
507 struct pci_bus *bus;
508 struct pci_ops *ops;
509 void *sysdata;
510 int busnr;
511 struct list_head windows;
512 struct list_head dma_ranges;
513 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
514 int (*map_irq)(const struct pci_dev *, u8, u8);
515 void (*release_fn)(struct pci_host_bridge *);
516 void *release_data;
517 struct msi_controller *msi;
518 unsigned int ignore_reset_delay:1;
519 unsigned int no_ext_tags:1;
520 unsigned int native_aer:1;
521 unsigned int native_pcie_hotplug:1;
522 unsigned int native_shpc_hotplug:1;
523 unsigned int native_pme:1;
524 unsigned int native_ltr:1;
525 unsigned int native_dpc:1;
526 unsigned int preserve_config:1;
527 unsigned int size_windows:1;
528
529
530 resource_size_t (*align_resource)(struct pci_dev *dev,
531 const struct resource *res,
532 resource_size_t start,
533 resource_size_t size,
534 resource_size_t align);
535 unsigned long private[0] ____cacheline_aligned;
536};
537
538#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
539
540static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
541{
542 return (void *)bridge->private;
543}
544
545static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
546{
547 return container_of(priv, struct pci_host_bridge, private);
548}
549
550struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
551struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
552 size_t priv);
553void pci_free_host_bridge(struct pci_host_bridge *bridge);
554struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
555
556void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
557 void (*release_fn)(struct pci_host_bridge *),
558 void *release_data);
559
560int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
561
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574
575#define PCI_SUBTRACTIVE_DECODE 0x1
576
577struct pci_bus_resource {
578 struct list_head list;
579 struct resource *res;
580 unsigned int flags;
581};
582
583#define PCI_REGION_FLAG_MASK 0x0fU
584
585struct pci_bus {
586 struct list_head node;
587 struct pci_bus *parent;
588 struct list_head children;
589 struct list_head devices;
590 struct pci_dev *self;
591 struct list_head slots;
592
593 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
594 struct list_head resources;
595 struct resource busn_res;
596
597 struct pci_ops *ops;
598 struct msi_controller *msi;
599 void *sysdata;
600 struct proc_dir_entry *procdir;
601
602 unsigned char number;
603 unsigned char primary;
604 unsigned char max_bus_speed;
605 unsigned char cur_bus_speed;
606#ifdef CONFIG_PCI_DOMAINS_GENERIC
607 int domain_nr;
608#endif
609
610 char name[48];
611
612 unsigned short bridge_ctl;
613 pci_bus_flags_t bus_flags;
614 struct device *bridge;
615 struct device dev;
616 struct bin_attribute *legacy_io;
617 struct bin_attribute *legacy_mem;
618 unsigned int is_added:1;
619};
620
621#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
622
623static inline u16 pci_dev_id(struct pci_dev *dev)
624{
625 return PCI_DEVID(dev->bus->number, dev->devfn);
626}
627
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635
636static inline bool pci_is_root_bus(struct pci_bus *pbus)
637{
638 return !(pbus->parent);
639}
640
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646
647
648static inline bool pci_is_bridge(struct pci_dev *dev)
649{
650 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
651 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
652}
653
654#define for_each_pci_bridge(dev, bus) \
655 list_for_each_entry(dev, &bus->devices, bus_list) \
656 if (!pci_is_bridge(dev)) {} else
657
658static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
659{
660 dev = pci_physfn(dev);
661 if (pci_is_root_bus(dev->bus))
662 return NULL;
663
664 return dev->bus->self;
665}
666
667#ifdef CONFIG_PCI_MSI
668static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
669{
670 return pci_dev->msi_enabled || pci_dev->msix_enabled;
671}
672#else
673static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
674#endif
675
676
677#define PCIBIOS_SUCCESSFUL 0x00
678#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
679#define PCIBIOS_BAD_VENDOR_ID 0x83
680#define PCIBIOS_DEVICE_NOT_FOUND 0x86
681#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
682#define PCIBIOS_SET_FAILED 0x88
683#define PCIBIOS_BUFFER_TOO_SMALL 0x89
684
685
686static inline int pcibios_err_to_errno(int err)
687{
688 if (err <= PCIBIOS_SUCCESSFUL)
689 return err;
690
691 switch (err) {
692 case PCIBIOS_FUNC_NOT_SUPPORTED:
693 return -ENOENT;
694 case PCIBIOS_BAD_VENDOR_ID:
695 return -ENOTTY;
696 case PCIBIOS_DEVICE_NOT_FOUND:
697 return -ENODEV;
698 case PCIBIOS_BAD_REGISTER_NUMBER:
699 return -EFAULT;
700 case PCIBIOS_SET_FAILED:
701 return -EIO;
702 case PCIBIOS_BUFFER_TOO_SMALL:
703 return -ENOSPC;
704 }
705
706 return -ERANGE;
707}
708
709
710
711struct pci_ops {
712 int (*add_bus)(struct pci_bus *bus);
713 void (*remove_bus)(struct pci_bus *bus);
714 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
715 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
716 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
717};
718
719
720
721
722
723int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
724 int reg, int len, u32 *val);
725int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
726 int reg, int len, u32 val);
727
728#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
729typedef u64 pci_bus_addr_t;
730#else
731typedef u32 pci_bus_addr_t;
732#endif
733
734struct pci_bus_region {
735 pci_bus_addr_t start;
736 pci_bus_addr_t end;
737};
738
739struct pci_dynids {
740 spinlock_t lock;
741 struct list_head list;
742};
743
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750
751
752typedef unsigned int __bitwise pci_ers_result_t;
753
754enum pci_ers_result {
755
756 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
757
758
759 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
760
761
762 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
763
764
765 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
766
767
768 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
769
770
771 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
772};
773
774
775struct pci_error_handlers {
776
777 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
778 enum pci_channel_state error);
779
780
781 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
782
783
784 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
785
786
787 void (*reset_prepare)(struct pci_dev *dev);
788 void (*reset_done)(struct pci_dev *dev);
789
790
791 void (*resume)(struct pci_dev *dev);
792};
793
794
795struct module;
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838struct pci_driver {
839 struct list_head node;
840 const char *name;
841 const struct pci_device_id *id_table;
842 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
843 void (*remove)(struct pci_dev *dev);
844 int (*suspend)(struct pci_dev *dev, pm_message_t state);
845 int (*resume)(struct pci_dev *dev);
846 void (*shutdown)(struct pci_dev *dev);
847 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
848 const struct pci_error_handlers *err_handler;
849 const struct attribute_group **groups;
850 struct device_driver driver;
851 struct pci_dynids dynids;
852};
853
854#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
855
856
857
858
859
860
861
862
863
864
865#define PCI_DEVICE(vend,dev) \
866 .vendor = (vend), .device = (dev), \
867 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
868
869
870
871
872
873
874
875
876
877
878
879#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
880 .vendor = (vend), .device = (dev), \
881 .subvendor = (subvend), .subdevice = (subdev)
882
883
884
885
886
887
888
889
890
891
892#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
893 .class = (dev_class), .class_mask = (dev_class_mask), \
894 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
895 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
896
897
898
899
900
901
902
903
904
905
906
907#define PCI_VDEVICE(vend, dev) \
908 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
909 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
910
911
912
913
914
915
916
917
918
919
920
921#define PCI_DEVICE_DATA(vend, dev, data) \
922 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
923 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
924 .driver_data = (kernel_ulong_t)(data)
925
926enum {
927 PCI_REASSIGN_ALL_RSRC = 0x00000001,
928 PCI_REASSIGN_ALL_BUS = 0x00000002,
929 PCI_PROBE_ONLY = 0x00000004,
930 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
931 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
932 PCI_COMPAT_DOMAIN_0 = 0x00000020,
933 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
934};
935
936#define PCI_IRQ_LEGACY (1 << 0)
937#define PCI_IRQ_MSI (1 << 1)
938#define PCI_IRQ_MSIX (1 << 2)
939#define PCI_IRQ_AFFINITY (1 << 3)
940
941
942#ifdef CONFIG_PCI
943
944extern unsigned int pci_flags;
945
946static inline void pci_set_flags(int flags) { pci_flags = flags; }
947static inline void pci_add_flags(int flags) { pci_flags |= flags; }
948static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
949static inline int pci_has_flag(int flag) { return pci_flags & flag; }
950
951void pcie_bus_configure_settings(struct pci_bus *bus);
952
953enum pcie_bus_config_types {
954 PCIE_BUS_TUNE_OFF,
955 PCIE_BUS_DEFAULT,
956 PCIE_BUS_SAFE,
957 PCIE_BUS_PERFORMANCE,
958 PCIE_BUS_PEER2PEER,
959};
960
961extern enum pcie_bus_config_types pcie_bus_config;
962
963extern struct bus_type pci_bus_type;
964
965
966
967extern struct list_head pci_root_buses;
968
969int no_pci_devices(void);
970
971void pcibios_resource_survey_bus(struct pci_bus *bus);
972void pcibios_bus_add_device(struct pci_dev *pdev);
973void pcibios_add_bus(struct pci_bus *bus);
974void pcibios_remove_bus(struct pci_bus *bus);
975void pcibios_fixup_bus(struct pci_bus *);
976int __must_check pcibios_enable_device(struct pci_dev *, int mask);
977
978char *pcibios_setup(char *str);
979
980
981resource_size_t pcibios_align_resource(void *, const struct resource *,
982 resource_size_t,
983 resource_size_t);
984
985
986void pci_fixup_cardbus(struct pci_bus *);
987
988
989
990void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
991 struct resource *res);
992void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
993 struct pci_bus_region *region);
994void pcibios_scan_specific_bus(int busn);
995struct pci_bus *pci_find_bus(int domain, int busnr);
996void pci_bus_add_devices(const struct pci_bus *bus);
997struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
998struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
999 struct pci_ops *ops, void *sysdata,
1000 struct list_head *resources);
1001int pci_host_probe(struct pci_host_bridge *bridge);
1002int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1003int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1004void pci_bus_release_busn_res(struct pci_bus *b);
1005struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1006 struct pci_ops *ops, void *sysdata,
1007 struct list_head *resources);
1008int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1009struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1010 int busnr);
1011struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1012 const char *name,
1013 struct hotplug_slot *hotplug);
1014void pci_destroy_slot(struct pci_slot *slot);
1015#ifdef CONFIG_SYSFS
1016void pci_dev_assign_slot(struct pci_dev *dev);
1017#else
1018static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1019#endif
1020int pci_scan_slot(struct pci_bus *bus, int devfn);
1021struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1022void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1023unsigned int pci_scan_child_bus(struct pci_bus *bus);
1024void pci_bus_add_device(struct pci_dev *dev);
1025void pci_read_bridge_bases(struct pci_bus *child);
1026struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1027 struct resource *res);
1028struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
1029u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1030int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1031u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1032struct pci_dev *pci_dev_get(struct pci_dev *dev);
1033void pci_dev_put(struct pci_dev *dev);
1034void pci_remove_bus(struct pci_bus *b);
1035void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1036void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1037void pci_stop_root_bus(struct pci_bus *bus);
1038void pci_remove_root_bus(struct pci_bus *bus);
1039void pci_setup_cardbus(struct pci_bus *bus);
1040void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1041void pci_sort_breadthfirst(void);
1042#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1043#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1044
1045
1046
1047enum pci_lost_interrupt_reason {
1048 PCI_LOST_IRQ_NO_INFORMATION = 0,
1049 PCI_LOST_IRQ_DISABLE_MSI,
1050 PCI_LOST_IRQ_DISABLE_MSIX,
1051 PCI_LOST_IRQ_DISABLE_ACPI,
1052};
1053enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
1054int pci_find_capability(struct pci_dev *dev, int cap);
1055int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1056int pci_find_ext_capability(struct pci_dev *dev, int cap);
1057int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1058int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1059int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1060struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1061
1062u64 pci_get_dsn(struct pci_dev *dev);
1063
1064struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1065 struct pci_dev *from);
1066struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1067 unsigned int ss_vendor, unsigned int ss_device,
1068 struct pci_dev *from);
1069struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1070struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1071 unsigned int devfn);
1072struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1073int pci_dev_present(const struct pci_device_id *ids);
1074
1075int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1076 int where, u8 *val);
1077int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1078 int where, u16 *val);
1079int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1080 int where, u32 *val);
1081int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1082 int where, u8 val);
1083int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1084 int where, u16 val);
1085int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1086 int where, u32 val);
1087
1088int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1089 int where, int size, u32 *val);
1090int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1091 int where, int size, u32 val);
1092int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1093 int where, int size, u32 *val);
1094int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1095 int where, int size, u32 val);
1096
1097struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1098
1099int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1100int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1101int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1102int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1103int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1104int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1105
1106int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1107int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1108int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1109int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1110int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1111 u16 clear, u16 set);
1112int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1113 u32 clear, u32 set);
1114
1115static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1116 u16 set)
1117{
1118 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1119}
1120
1121static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1122 u32 set)
1123{
1124 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1125}
1126
1127static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1128 u16 clear)
1129{
1130 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1131}
1132
1133static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1134 u32 clear)
1135{
1136 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1137}
1138
1139
1140int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1141int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1142int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1143int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1144int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1145int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1146
1147int __must_check pci_enable_device(struct pci_dev *dev);
1148int __must_check pci_enable_device_io(struct pci_dev *dev);
1149int __must_check pci_enable_device_mem(struct pci_dev *dev);
1150int __must_check pci_reenable_device(struct pci_dev *);
1151int __must_check pcim_enable_device(struct pci_dev *pdev);
1152void pcim_pin_device(struct pci_dev *pdev);
1153
1154static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1155{
1156
1157
1158
1159
1160 return !pdev->broken_intx_masking;
1161}
1162
1163static inline int pci_is_enabled(struct pci_dev *pdev)
1164{
1165 return (atomic_read(&pdev->enable_cnt) > 0);
1166}
1167
1168static inline int pci_is_managed(struct pci_dev *pdev)
1169{
1170 return pdev->is_managed;
1171}
1172
1173void pci_disable_device(struct pci_dev *dev);
1174
1175extern unsigned int pcibios_max_latency;
1176void pci_set_master(struct pci_dev *dev);
1177void pci_clear_master(struct pci_dev *dev);
1178
1179int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1180int pci_set_cacheline_size(struct pci_dev *dev);
1181#define HAVE_PCI_SET_MWI
1182int __must_check pci_set_mwi(struct pci_dev *dev);
1183int __must_check pcim_set_mwi(struct pci_dev *dev);
1184int pci_try_set_mwi(struct pci_dev *dev);
1185void pci_clear_mwi(struct pci_dev *dev);
1186void pci_intx(struct pci_dev *dev, int enable);
1187bool pci_check_and_mask_intx(struct pci_dev *dev);
1188bool pci_check_and_unmask_intx(struct pci_dev *dev);
1189int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1190int pci_wait_for_pending_transaction(struct pci_dev *dev);
1191int pcix_get_max_mmrbc(struct pci_dev *dev);
1192int pcix_get_mmrbc(struct pci_dev *dev);
1193int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1194int pcie_get_readrq(struct pci_dev *dev);
1195int pcie_set_readrq(struct pci_dev *dev, int rq);
1196int pcie_get_mps(struct pci_dev *dev);
1197int pcie_set_mps(struct pci_dev *dev, int mps);
1198u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1199 enum pci_bus_speed *speed,
1200 enum pcie_link_width *width);
1201void pcie_print_link_status(struct pci_dev *dev);
1202bool pcie_has_flr(struct pci_dev *dev);
1203int pcie_flr(struct pci_dev *dev);
1204int __pci_reset_function_locked(struct pci_dev *dev);
1205int pci_reset_function(struct pci_dev *dev);
1206int pci_reset_function_locked(struct pci_dev *dev);
1207int pci_try_reset_function(struct pci_dev *dev);
1208int pci_probe_reset_slot(struct pci_slot *slot);
1209int pci_probe_reset_bus(struct pci_bus *bus);
1210int pci_reset_bus(struct pci_dev *dev);
1211void pci_reset_secondary_bus(struct pci_dev *dev);
1212void pcibios_reset_secondary_bus(struct pci_dev *dev);
1213void pci_update_resource(struct pci_dev *dev, int resno);
1214int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1215int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1216void pci_release_resource(struct pci_dev *dev, int resno);
1217int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1218int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1219bool pci_device_is_present(struct pci_dev *pdev);
1220void pci_ignore_hotplug(struct pci_dev *dev);
1221struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1222int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1223
1224int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1225 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1226 const char *fmt, ...);
1227void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1228
1229
1230int pci_enable_rom(struct pci_dev *pdev);
1231void pci_disable_rom(struct pci_dev *pdev);
1232void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1233void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1234
1235
1236int pci_save_state(struct pci_dev *dev);
1237void pci_restore_state(struct pci_dev *dev);
1238struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1239int pci_load_saved_state(struct pci_dev *dev,
1240 struct pci_saved_state *state);
1241int pci_load_and_free_saved_state(struct pci_dev *dev,
1242 struct pci_saved_state **state);
1243struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1244struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1245 u16 cap);
1246int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1247int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1248 u16 cap, unsigned int size);
1249int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1250int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1251pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1252bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1253void pci_pme_active(struct pci_dev *dev, bool enable);
1254int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1255int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1256int pci_prepare_to_sleep(struct pci_dev *dev);
1257int pci_back_from_sleep(struct pci_dev *dev);
1258bool pci_dev_run_wake(struct pci_dev *dev);
1259void pci_d3cold_enable(struct pci_dev *dev);
1260void pci_d3cold_disable(struct pci_dev *dev);
1261bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1262void pci_wakeup_bus(struct pci_bus *bus);
1263void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1264
1265
1266void set_pcie_port_type(struct pci_dev *pdev);
1267void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1268
1269
1270int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1271unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1272unsigned int pci_rescan_bus(struct pci_bus *bus);
1273void pci_lock_rescan_remove(void);
1274void pci_unlock_rescan_remove(void);
1275
1276
1277ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1278ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1279int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1280
1281
1282resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1283void pci_bus_assign_resources(const struct pci_bus *bus);
1284void pci_bus_claim_resources(struct pci_bus *bus);
1285void pci_bus_size_bridges(struct pci_bus *bus);
1286int pci_claim_resource(struct pci_dev *, int);
1287int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1288void pci_assign_unassigned_resources(void);
1289void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1290void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1291void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1292int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1293void pdev_enable_device(struct pci_dev *);
1294int pci_enable_resources(struct pci_dev *, int mask);
1295void pci_assign_irq(struct pci_dev *dev);
1296struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1297#define HAVE_PCI_REQ_REGIONS 2
1298int __must_check pci_request_regions(struct pci_dev *, const char *);
1299int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1300void pci_release_regions(struct pci_dev *);
1301int __must_check pci_request_region(struct pci_dev *, int, const char *);
1302void pci_release_region(struct pci_dev *, int);
1303int pci_request_selected_regions(struct pci_dev *, int, const char *);
1304int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1305void pci_release_selected_regions(struct pci_dev *, int);
1306
1307
1308void pci_add_resource(struct list_head *resources, struct resource *res);
1309void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1310 resource_size_t offset);
1311void pci_free_resource_list(struct list_head *resources);
1312void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1313 unsigned int flags);
1314struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1315void pci_bus_remove_resources(struct pci_bus *bus);
1316int devm_request_pci_bus_resources(struct device *dev,
1317 struct list_head *resources);
1318
1319
1320int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1321
1322#define pci_bus_for_each_resource(bus, res, i) \
1323 for (i = 0; \
1324 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1325 i++)
1326
1327int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1328 struct resource *res, resource_size_t size,
1329 resource_size_t align, resource_size_t min,
1330 unsigned long type_mask,
1331 resource_size_t (*alignf)(void *,
1332 const struct resource *,
1333 resource_size_t,
1334 resource_size_t),
1335 void *alignf_data);
1336
1337
1338int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1339 resource_size_t size);
1340unsigned long pci_address_to_pio(phys_addr_t addr);
1341phys_addr_t pci_pio_to_address(unsigned long pio);
1342int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1343int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1344 phys_addr_t phys_addr);
1345void pci_unmap_iospace(struct resource *res);
1346void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1347 resource_size_t offset,
1348 resource_size_t size);
1349void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1350 struct resource *res);
1351
1352static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1353{
1354 struct pci_bus_region region;
1355
1356 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1357 return region.start;
1358}
1359
1360
1361int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1362 const char *mod_name);
1363
1364
1365#define pci_register_driver(driver) \
1366 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1367
1368void pci_unregister_driver(struct pci_driver *dev);
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378#define module_pci_driver(__pci_driver) \
1379 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389#define builtin_pci_driver(__pci_driver) \
1390 builtin_driver(__pci_driver, pci_register_driver)
1391
1392struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1393int pci_add_dynid(struct pci_driver *drv,
1394 unsigned int vendor, unsigned int device,
1395 unsigned int subvendor, unsigned int subdevice,
1396 unsigned int class, unsigned int class_mask,
1397 unsigned long driver_data);
1398const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1399 struct pci_dev *dev);
1400int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1401 int pass);
1402
1403void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1404 void *userdata);
1405int pci_cfg_space_size(struct pci_dev *dev);
1406unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1407void pci_setup_bridge(struct pci_bus *bus);
1408resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1409 unsigned long type);
1410
1411#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1412#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1413
1414int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1415 unsigned int command_bits, u32 flags);
1416
1417
1418
1419
1420
1421
1422
1423#define PCI_IRQ_VIRTUAL (1 << 4)
1424
1425#define PCI_IRQ_ALL_TYPES \
1426 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1427
1428
1429
1430#include <linux/dmapool.h>
1431
1432#define pci_pool dma_pool
1433#define pci_pool_create(name, pdev, size, align, allocation) \
1434 dma_pool_create(name, &pdev->dev, size, align, allocation)
1435#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1436#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1437#define pci_pool_zalloc(pool, flags, handle) \
1438 dma_pool_zalloc(pool, flags, handle)
1439#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1440
1441struct msix_entry {
1442 u32 vector;
1443 u16 entry;
1444};
1445
1446#ifdef CONFIG_PCI_MSI
1447int pci_msi_vec_count(struct pci_dev *dev);
1448void pci_disable_msi(struct pci_dev *dev);
1449int pci_msix_vec_count(struct pci_dev *dev);
1450void pci_disable_msix(struct pci_dev *dev);
1451void pci_restore_msi_state(struct pci_dev *dev);
1452int pci_msi_enabled(void);
1453int pci_enable_msi(struct pci_dev *dev);
1454int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1455 int minvec, int maxvec);
1456static inline int pci_enable_msix_exact(struct pci_dev *dev,
1457 struct msix_entry *entries, int nvec)
1458{
1459 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1460 if (rc < 0)
1461 return rc;
1462 return 0;
1463}
1464int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1465 unsigned int max_vecs, unsigned int flags,
1466 struct irq_affinity *affd);
1467
1468void pci_free_irq_vectors(struct pci_dev *dev);
1469int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1470const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1471
1472#else
1473static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1474static inline void pci_disable_msi(struct pci_dev *dev) { }
1475static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1476static inline void pci_disable_msix(struct pci_dev *dev) { }
1477static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1478static inline int pci_msi_enabled(void) { return 0; }
1479static inline int pci_enable_msi(struct pci_dev *dev)
1480{ return -ENOSYS; }
1481static inline int pci_enable_msix_range(struct pci_dev *dev,
1482 struct msix_entry *entries, int minvec, int maxvec)
1483{ return -ENOSYS; }
1484static inline int pci_enable_msix_exact(struct pci_dev *dev,
1485 struct msix_entry *entries, int nvec)
1486{ return -ENOSYS; }
1487
1488static inline int
1489pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1490 unsigned int max_vecs, unsigned int flags,
1491 struct irq_affinity *aff_desc)
1492{
1493 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1494 return 1;
1495 return -ENOSPC;
1496}
1497
1498static inline void pci_free_irq_vectors(struct pci_dev *dev)
1499{
1500}
1501
1502static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1503{
1504 if (WARN_ON_ONCE(nr > 0))
1505 return -EINVAL;
1506 return dev->irq;
1507}
1508static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1509 int vec)
1510{
1511 return cpu_possible_mask;
1512}
1513#endif
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1532 struct device_node *node,
1533 const u32 *intspec,
1534 unsigned int intsize,
1535 unsigned long *out_hwirq,
1536 unsigned int *out_type)
1537{
1538 const u32 intx = intspec[0];
1539
1540 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1541 return -EINVAL;
1542
1543 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1544 return 0;
1545}
1546
1547#ifdef CONFIG_PCIEPORTBUS
1548extern bool pcie_ports_disabled;
1549extern bool pcie_ports_native;
1550#else
1551#define pcie_ports_disabled true
1552#define pcie_ports_native false
1553#endif
1554
1555#define PCIE_LINK_STATE_L0S BIT(0)
1556#define PCIE_LINK_STATE_L1 BIT(1)
1557#define PCIE_LINK_STATE_CLKPM BIT(2)
1558#define PCIE_LINK_STATE_L1_1 BIT(3)
1559#define PCIE_LINK_STATE_L1_2 BIT(4)
1560#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1561#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1562
1563#ifdef CONFIG_PCIEASPM
1564int pci_disable_link_state(struct pci_dev *pdev, int state);
1565int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1566void pcie_no_aspm(void);
1567bool pcie_aspm_support_enabled(void);
1568bool pcie_aspm_enabled(struct pci_dev *pdev);
1569#else
1570static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1571{ return 0; }
1572static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1573{ return 0; }
1574static inline void pcie_no_aspm(void) { }
1575static inline bool pcie_aspm_support_enabled(void) { return false; }
1576static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1577#endif
1578
1579#ifdef CONFIG_PCIEAER
1580bool pci_aer_available(void);
1581#else
1582static inline bool pci_aer_available(void) { return false; }
1583#endif
1584
1585bool pci_ats_disabled(void);
1586
1587void pci_cfg_access_lock(struct pci_dev *dev);
1588bool pci_cfg_access_trylock(struct pci_dev *dev);
1589void pci_cfg_access_unlock(struct pci_dev *dev);
1590
1591
1592
1593
1594
1595
1596#ifdef CONFIG_PCI_DOMAINS
1597extern int pci_domains_supported;
1598#else
1599enum { pci_domains_supported = 0 };
1600static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1601static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1602#endif
1603
1604
1605
1606
1607
1608
1609#ifdef CONFIG_PCI_DOMAINS_GENERIC
1610static inline int pci_domain_nr(struct pci_bus *bus)
1611{
1612 return bus->domain_nr;
1613}
1614#ifdef CONFIG_ACPI
1615int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1616#else
1617static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1618{ return 0; }
1619#endif
1620int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1621#endif
1622
1623
1624typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1625 unsigned int command_bits, u32 flags);
1626void pci_register_set_vga_state(arch_set_vga_state_t func);
1627
1628static inline int
1629pci_request_io_regions(struct pci_dev *pdev, const char *name)
1630{
1631 return pci_request_selected_regions(pdev,
1632 pci_select_bars(pdev, IORESOURCE_IO), name);
1633}
1634
1635static inline void
1636pci_release_io_regions(struct pci_dev *pdev)
1637{
1638 return pci_release_selected_regions(pdev,
1639 pci_select_bars(pdev, IORESOURCE_IO));
1640}
1641
1642static inline int
1643pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1644{
1645 return pci_request_selected_regions(pdev,
1646 pci_select_bars(pdev, IORESOURCE_MEM), name);
1647}
1648
1649static inline void
1650pci_release_mem_regions(struct pci_dev *pdev)
1651{
1652 return pci_release_selected_regions(pdev,
1653 pci_select_bars(pdev, IORESOURCE_MEM));
1654}
1655
1656#else
1657
1658static inline void pci_set_flags(int flags) { }
1659static inline void pci_add_flags(int flags) { }
1660static inline void pci_clear_flags(int flags) { }
1661static inline int pci_has_flag(int flag) { return 0; }
1662
1663
1664
1665
1666
1667#define _PCI_NOP(o, s, t) \
1668 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1669 int where, t val) \
1670 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1671
1672#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1673 _PCI_NOP(o, word, u16 x) \
1674 _PCI_NOP(o, dword, u32 x)
1675_PCI_NOP_ALL(read, *)
1676_PCI_NOP_ALL(write,)
1677
1678static inline struct pci_dev *pci_get_device(unsigned int vendor,
1679 unsigned int device,
1680 struct pci_dev *from)
1681{ return NULL; }
1682
1683static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1684 unsigned int device,
1685 unsigned int ss_vendor,
1686 unsigned int ss_device,
1687 struct pci_dev *from)
1688{ return NULL; }
1689
1690static inline struct pci_dev *pci_get_class(unsigned int class,
1691 struct pci_dev *from)
1692{ return NULL; }
1693
1694#define pci_dev_present(ids) (0)
1695#define no_pci_devices() (1)
1696#define pci_dev_put(dev) do { } while (0)
1697
1698static inline void pci_set_master(struct pci_dev *dev) { }
1699static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1700static inline void pci_disable_device(struct pci_dev *dev) { }
1701static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1702static inline int pci_assign_resource(struct pci_dev *dev, int i)
1703{ return -EBUSY; }
1704static inline int __pci_register_driver(struct pci_driver *drv,
1705 struct module *owner)
1706{ return 0; }
1707static inline int pci_register_driver(struct pci_driver *drv)
1708{ return 0; }
1709static inline void pci_unregister_driver(struct pci_driver *drv) { }
1710static inline int pci_find_capability(struct pci_dev *dev, int cap)
1711{ return 0; }
1712static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1713 int cap)
1714{ return 0; }
1715static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1716{ return 0; }
1717
1718static inline u64 pci_get_dsn(struct pci_dev *dev)
1719{ return 0; }
1720
1721
1722static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1723static inline void pci_restore_state(struct pci_dev *dev) { }
1724static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1725{ return 0; }
1726static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1727{ return 0; }
1728static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1729 pm_message_t state)
1730{ return PCI_D0; }
1731static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1732 int enable)
1733{ return 0; }
1734
1735static inline struct resource *pci_find_resource(struct pci_dev *dev,
1736 struct resource *res)
1737{ return NULL; }
1738static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1739{ return -EIO; }
1740static inline void pci_release_regions(struct pci_dev *dev) { }
1741
1742static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1743
1744static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1745{ return NULL; }
1746static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1747 unsigned int devfn)
1748{ return NULL; }
1749static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1750 unsigned int bus, unsigned int devfn)
1751{ return NULL; }
1752
1753static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1754static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1755
1756#define dev_is_pci(d) (false)
1757#define dev_is_pf(d) (false)
1758static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1759{ return false; }
1760static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1761 struct device_node *node,
1762 const u32 *intspec,
1763 unsigned int intsize,
1764 unsigned long *out_hwirq,
1765 unsigned int *out_type)
1766{ return -EINVAL; }
1767
1768static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1769 struct pci_dev *dev)
1770{ return NULL; }
1771static inline bool pci_ats_disabled(void) { return true; }
1772
1773static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1774{
1775 return -EINVAL;
1776}
1777
1778static inline int
1779pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1780 unsigned int max_vecs, unsigned int flags,
1781 struct irq_affinity *aff_desc)
1782{
1783 return -ENOSPC;
1784}
1785#endif
1786
1787static inline int
1788pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1789 unsigned int max_vecs, unsigned int flags)
1790{
1791 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1792 NULL);
1793}
1794
1795
1796
1797#include <asm/pci.h>
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1812 struct vm_area_struct *vma,
1813 enum pci_mmap_state mmap_state, int write_combine);
1814int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1815 struct vm_area_struct *vma,
1816 enum pci_mmap_state mmap_state, int write_combine);
1817
1818#ifndef arch_can_pci_mmap_wc
1819#define arch_can_pci_mmap_wc() 0
1820#endif
1821
1822#ifndef arch_can_pci_mmap_io
1823#define arch_can_pci_mmap_io() 0
1824#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1825#else
1826int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1827#endif
1828
1829#ifndef pci_root_bus_fwnode
1830#define pci_root_bus_fwnode(bus) NULL
1831#endif
1832
1833
1834
1835
1836
1837#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1838#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1839#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1840#define pci_resource_len(dev,bar) \
1841 ((pci_resource_start((dev), (bar)) == 0 && \
1842 pci_resource_end((dev), (bar)) == \
1843 pci_resource_start((dev), (bar))) ? 0 : \
1844 \
1845 (pci_resource_end((dev), (bar)) - \
1846 pci_resource_start((dev), (bar)) + 1))
1847
1848
1849
1850
1851
1852
1853static inline void *pci_get_drvdata(struct pci_dev *pdev)
1854{
1855 return dev_get_drvdata(&pdev->dev);
1856}
1857
1858static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1859{
1860 dev_set_drvdata(&pdev->dev, data);
1861}
1862
1863static inline const char *pci_name(const struct pci_dev *pdev)
1864{
1865 return dev_name(&pdev->dev);
1866}
1867
1868void pci_resource_to_user(const struct pci_dev *dev, int bar,
1869 const struct resource *rsrc,
1870 resource_size_t *start, resource_size_t *end);
1871
1872
1873
1874
1875
1876
1877
1878
1879struct pci_fixup {
1880 u16 vendor;
1881 u16 device;
1882 u32 class;
1883 unsigned int class_shift;
1884#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1885 int hook_offset;
1886#else
1887 void (*hook)(struct pci_dev *dev);
1888#endif
1889};
1890
1891enum pci_fixup_pass {
1892 pci_fixup_early,
1893 pci_fixup_header,
1894 pci_fixup_final,
1895 pci_fixup_enable,
1896 pci_fixup_resume,
1897 pci_fixup_suspend,
1898 pci_fixup_resume_early,
1899 pci_fixup_suspend_late,
1900};
1901
1902#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1903#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1904 class_shift, hook) \
1905 __ADDRESSABLE(hook) \
1906 asm(".section " #sec ", \"a\" \n" \
1907 ".balign 16 \n" \
1908 ".short " #vendor ", " #device " \n" \
1909 ".long " #class ", " #class_shift " \n" \
1910 ".long " #hook " - . \n" \
1911 ".previous \n");
1912#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1913 class_shift, hook) \
1914 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1915 class_shift, hook)
1916#else
1917
1918#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1919 class_shift, hook) \
1920 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1921 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1922 = { vendor, device, class, class_shift, hook };
1923#endif
1924
1925#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1926 class_shift, hook) \
1927 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1928 hook, vendor, device, class, class_shift, hook)
1929#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1930 class_shift, hook) \
1931 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1932 hook, vendor, device, class, class_shift, hook)
1933#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1934 class_shift, hook) \
1935 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1936 hook, vendor, device, class, class_shift, hook)
1937#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1938 class_shift, hook) \
1939 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1940 hook, vendor, device, class, class_shift, hook)
1941#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1942 class_shift, hook) \
1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1944 resume##hook, vendor, device, class, class_shift, hook)
1945#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1946 class_shift, hook) \
1947 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1948 resume_early##hook, vendor, device, class, class_shift, hook)
1949#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1950 class_shift, hook) \
1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1952 suspend##hook, vendor, device, class, class_shift, hook)
1953#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1954 class_shift, hook) \
1955 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1956 suspend_late##hook, vendor, device, class, class_shift, hook)
1957
1958#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1960 hook, vendor, device, PCI_ANY_ID, 0, hook)
1961#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1963 hook, vendor, device, PCI_ANY_ID, 0, hook)
1964#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1966 hook, vendor, device, PCI_ANY_ID, 0, hook)
1967#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1969 hook, vendor, device, PCI_ANY_ID, 0, hook)
1970#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1972 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1973#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1975 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1976#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1977 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1978 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1979#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1980 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1981 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1982
1983#ifdef CONFIG_PCI_QUIRKS
1984void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1985#else
1986static inline void pci_fixup_device(enum pci_fixup_pass pass,
1987 struct pci_dev *dev) { }
1988#endif
1989
1990void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1991void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1992void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1993int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1994int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1995 const char *name);
1996void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1997
1998extern int pci_pci_problems;
1999#define PCIPCI_FAIL 1
2000#define PCIPCI_TRITON 2
2001#define PCIPCI_NATOMA 4
2002#define PCIPCI_VIAETBF 8
2003#define PCIPCI_VSFX 16
2004#define PCIPCI_ALIMAGIK 32
2005#define PCIAGP_FAIL 64
2006
2007extern unsigned long pci_cardbus_io_size;
2008extern unsigned long pci_cardbus_mem_size;
2009extern u8 pci_dfl_cache_line_size;
2010extern u8 pci_cache_line_size;
2011
2012
2013void pcibios_disable_device(struct pci_dev *dev);
2014void pcibios_set_master(struct pci_dev *dev);
2015int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2016 enum pcie_reset_state state);
2017int pcibios_add_device(struct pci_dev *dev);
2018void pcibios_release_device(struct pci_dev *dev);
2019#ifdef CONFIG_PCI
2020void pcibios_penalize_isa_irq(int irq, int active);
2021#else
2022static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2023#endif
2024int pcibios_alloc_irq(struct pci_dev *dev);
2025void pcibios_free_irq(struct pci_dev *dev);
2026resource_size_t pcibios_default_alignment(void);
2027
2028#ifdef CONFIG_HIBERNATE_CALLBACKS
2029extern struct dev_pm_ops pcibios_pm_ops;
2030#endif
2031
2032#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2033void __init pci_mmcfg_early_init(void);
2034void __init pci_mmcfg_late_init(void);
2035#else
2036static inline void pci_mmcfg_early_init(void) { }
2037static inline void pci_mmcfg_late_init(void) { }
2038#endif
2039
2040int pci_ext_cfg_avail(void);
2041
2042void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2043void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2044
2045#ifdef CONFIG_PCI_IOV
2046int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2047int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2048
2049int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2050void pci_disable_sriov(struct pci_dev *dev);
2051int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2052void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2053int pci_num_vf(struct pci_dev *dev);
2054int pci_vfs_assigned(struct pci_dev *dev);
2055int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2056int pci_sriov_get_totalvfs(struct pci_dev *dev);
2057int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2058resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2059void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2060
2061
2062int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2063int pcibios_sriov_disable(struct pci_dev *pdev);
2064resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2065#else
2066static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2067{
2068 return -ENOSYS;
2069}
2070static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2071{
2072 return -ENOSYS;
2073}
2074static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2075{ return -ENODEV; }
2076static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2077{
2078 return -ENOSYS;
2079}
2080static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2081 int id) { }
2082static inline void pci_disable_sriov(struct pci_dev *dev) { }
2083static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2084static inline int pci_vfs_assigned(struct pci_dev *dev)
2085{ return 0; }
2086static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2087{ return 0; }
2088static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2089{ return 0; }
2090#define pci_sriov_configure_simple NULL
2091static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2092{ return 0; }
2093static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2094#endif
2095
2096#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2097void pci_hp_create_module_link(struct pci_slot *pci_slot);
2098void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2099#endif
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112static inline int pci_pcie_cap(struct pci_dev *dev)
2113{
2114 return dev->pcie_cap;
2115}
2116
2117
2118
2119
2120
2121
2122
2123static inline bool pci_is_pcie(struct pci_dev *dev)
2124{
2125 return pci_pcie_cap(dev);
2126}
2127
2128
2129
2130
2131
2132static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2133{
2134 return dev->pcie_flags_reg;
2135}
2136
2137
2138
2139
2140
2141static inline int pci_pcie_type(const struct pci_dev *dev)
2142{
2143 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2144}
2145
2146static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2147{
2148 while (1) {
2149 if (!pci_is_pcie(dev))
2150 break;
2151 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2152 return dev;
2153 if (!dev->bus->self)
2154 break;
2155 dev = dev->bus->self;
2156 }
2157 return NULL;
2158}
2159
2160void pci_request_acs(void);
2161bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2162bool pci_acs_path_enabled(struct pci_dev *start,
2163 struct pci_dev *end, u16 acs_flags);
2164int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2165
2166#define PCI_VPD_LRDT 0x80
2167#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2168
2169
2170#define PCI_VPD_LTIN_ID_STRING 0x02
2171#define PCI_VPD_LTIN_RO_DATA 0x10
2172#define PCI_VPD_LTIN_RW_DATA 0x11
2173
2174#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2175#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2176#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2177
2178
2179#define PCI_VPD_STIN_END 0x0f
2180
2181#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2182
2183#define PCI_VPD_SRDT_TIN_MASK 0x78
2184#define PCI_VPD_SRDT_LEN_MASK 0x07
2185#define PCI_VPD_LRDT_TIN_MASK 0x7f
2186
2187#define PCI_VPD_LRDT_TAG_SIZE 3
2188#define PCI_VPD_SRDT_TAG_SIZE 1
2189
2190#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2191
2192#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2193#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2194#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2195#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2196#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2197
2198
2199
2200
2201
2202
2203
2204static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2205{
2206 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2207}
2208
2209
2210
2211
2212
2213
2214
2215static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2216{
2217 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2218}
2219
2220
2221
2222
2223
2224
2225
2226static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2227{
2228 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2229}
2230
2231
2232
2233
2234
2235
2236
2237static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2238{
2239 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2240}
2241
2242
2243
2244
2245
2246
2247
2248static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2249{
2250 return info_field[2];
2251}
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2276 unsigned int len, const char *kw);
2277
2278
2279#ifdef CONFIG_OF
2280struct device_node;
2281struct irq_domain;
2282struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2283int pci_parse_request_of_pci_ranges(struct device *dev,
2284 struct list_head *resources,
2285 struct list_head *ib_resources,
2286 struct resource **bus_range);
2287
2288
2289struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2290
2291#else
2292static inline struct irq_domain *
2293pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2294static inline int
2295pci_parse_request_of_pci_ranges(struct device *dev,
2296 struct list_head *resources,
2297 struct list_head *ib_resources,
2298 struct resource **bus_range)
2299{
2300 return -EINVAL;
2301}
2302#endif
2303
2304static inline struct device_node *
2305pci_device_to_OF_node(const struct pci_dev *pdev)
2306{
2307 return pdev ? pdev->dev.of_node : NULL;
2308}
2309
2310static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2311{
2312 return bus ? bus->dev.of_node : NULL;
2313}
2314
2315#ifdef CONFIG_ACPI
2316struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2317
2318void
2319pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2320bool pci_pr3_present(struct pci_dev *pdev);
2321#else
2322static inline struct irq_domain *
2323pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2324static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2325#endif
2326
2327#ifdef CONFIG_EEH
2328static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2329{
2330 return pdev->dev.archdata.edev;
2331}
2332#endif
2333
2334void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2335bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2336int pci_for_each_dma_alias(struct pci_dev *pdev,
2337 int (*fn)(struct pci_dev *pdev,
2338 u16 alias, void *data), void *data);
2339
2340
2341static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2342{
2343 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2344}
2345static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2346{
2347 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2348}
2349static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2350{
2351 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2352}
2353
2354
2355
2356
2357
2358
2359
2360static inline bool pci_ari_enabled(struct pci_bus *bus)
2361{
2362 return bus->self && bus->self->ari_enabled;
2363}
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2374{
2375 struct pci_dev *parent = pdev;
2376
2377 if (pdev->is_thunderbolt)
2378 return true;
2379
2380 while ((parent = pci_upstream_bridge(parent)))
2381 if (parent->is_thunderbolt)
2382 return true;
2383
2384 return false;
2385}
2386
2387#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2388void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2389#endif
2390
2391
2392#include <linux/pci-dma-compat.h>
2393
2394#define pci_printk(level, pdev, fmt, arg...) \
2395 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2396
2397#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2398#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2399#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2400#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2401#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2402#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2403#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2404#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2405
2406#define pci_notice_ratelimited(pdev, fmt, arg...) \
2407 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2408
2409#define pci_info_ratelimited(pdev, fmt, arg...) \
2410 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2411
2412#define pci_WARN(pdev, condition, fmt, arg...) \
2413 WARN(condition, "%s %s: " fmt, \
2414 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2415
2416#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2417 WARN_ONCE(condition, "%s %s: " fmt, \
2418 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2419
2420#endif
2421