linux/sound/soc/intel/skylake/bxt-sst.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  bxt-sst.c - DSP library functions for BXT platform
   4 *
   5 *  Copyright (C) 2015-16 Intel Corp
   6 *  Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
   7 *         Jeeja KP <jeeja.kp@intel.com>
   8 */
   9
  10#include <linux/module.h>
  11#include <linux/delay.h>
  12#include <linux/firmware.h>
  13#include <linux/device.h>
  14
  15#include "../common/sst-dsp.h"
  16#include "../common/sst-dsp-priv.h"
  17#include "skl.h"
  18
  19#define BXT_BASEFW_TIMEOUT      3000
  20#define BXT_ROM_INIT_TIMEOUT    70
  21#define BXT_IPC_PURGE_FW        0x01004000
  22
  23#define BXT_ROM_INIT            0x5
  24#define BXT_ADSP_SRAM0_BASE     0x80000
  25
  26/* Firmware status window */
  27#define BXT_ADSP_FW_STATUS      BXT_ADSP_SRAM0_BASE
  28#define BXT_ADSP_ERROR_CODE     (BXT_ADSP_FW_STATUS + 0x4)
  29
  30#define BXT_ADSP_SRAM1_BASE     0xA0000
  31
  32#define BXT_INSTANCE_ID 0
  33#define BXT_BASE_FW_MODULE_ID 0
  34
  35#define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
  36
  37/* Delay before scheduling D0i3 entry */
  38#define BXT_D0I3_DELAY 5000
  39
  40static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
  41{
  42         return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
  43}
  44
  45static int
  46bxt_load_library(struct sst_dsp *ctx, struct skl_lib_info *linfo, int lib_count)
  47{
  48        struct snd_dma_buffer dmab;
  49        struct skl_dev *skl = ctx->thread_context;
  50        struct firmware stripped_fw;
  51        int ret = 0, i, dma_id, stream_tag;
  52
  53        /* library indices start from 1 to N. 0 represents base FW */
  54        for (i = 1; i < lib_count; i++) {
  55                ret = skl_prepare_lib_load(skl, &skl->lib_info[i], &stripped_fw,
  56                                        BXT_ADSP_FW_BIN_HDR_OFFSET, i);
  57                if (ret < 0)
  58                        goto load_library_failed;
  59
  60                stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40,
  61                                        stripped_fw.size, &dmab);
  62                if (stream_tag <= 0) {
  63                        dev_err(ctx->dev, "Lib prepare DMA err: %x\n",
  64                                        stream_tag);
  65                        ret = stream_tag;
  66                        goto load_library_failed;
  67                }
  68
  69                dma_id = stream_tag - 1;
  70                memcpy(dmab.area, stripped_fw.data, stripped_fw.size);
  71
  72                ctx->dsp_ops.trigger(ctx->dev, true, stream_tag);
  73                ret = skl_sst_ipc_load_library(&skl->ipc, dma_id, i, true);
  74                if (ret < 0)
  75                        dev_err(ctx->dev, "IPC Load Lib for %s fail: %d\n",
  76                                        linfo[i].name, ret);
  77
  78                ctx->dsp_ops.trigger(ctx->dev, false, stream_tag);
  79                ctx->dsp_ops.cleanup(ctx->dev, &dmab, stream_tag);
  80        }
  81
  82        return ret;
  83
  84load_library_failed:
  85        skl_release_library(linfo, lib_count);
  86        return ret;
  87}
  88
  89/*
  90 * First boot sequence has some extra steps. Core 0 waits for power
  91 * status on core 1, so power up core 1 also momentarily, keep it in
  92 * reset/stall and then turn it off
  93 */
  94static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
  95                        const void *fwdata, u32 fwsize)
  96{
  97        int stream_tag, ret;
  98
  99        stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
 100        if (stream_tag <= 0) {
 101                dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
 102                                stream_tag);
 103                return stream_tag;
 104        }
 105
 106        ctx->dsp_ops.stream_tag = stream_tag;
 107        memcpy(ctx->dmab.area, fwdata, fwsize);
 108
 109        /* Step 1: Power up core 0 and core1 */
 110        ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
 111                                SKL_DSP_CORE_MASK(1));
 112        if (ret < 0) {
 113                dev_err(ctx->dev, "dsp core0/1 power up failed\n");
 114                goto base_fw_load_failed;
 115        }
 116
 117        /* Step 2: Purge FW request */
 118        sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
 119                                (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
 120
 121        /* Step 3: Unset core0 reset state & unstall/run core0 */
 122        ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
 123        if (ret < 0) {
 124                dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
 125                ret = -EIO;
 126                goto base_fw_load_failed;
 127        }
 128
 129        /* Step 4: Wait for DONE Bit */
 130        ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_HIPCIE,
 131                                        SKL_ADSP_REG_HIPCIE_DONE,
 132                                        SKL_ADSP_REG_HIPCIE_DONE,
 133                                        BXT_INIT_TIMEOUT, "HIPCIE Done");
 134        if (ret < 0) {
 135                dev_err(ctx->dev, "Timeout for Purge Request%d\n", ret);
 136                goto base_fw_load_failed;
 137        }
 138
 139        /* Step 5: power down core1 */
 140        ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
 141        if (ret < 0) {
 142                dev_err(ctx->dev, "dsp core1 power down failed\n");
 143                goto base_fw_load_failed;
 144        }
 145
 146        /* Step 6: Enable Interrupt */
 147        skl_ipc_int_enable(ctx);
 148        skl_ipc_op_int_enable(ctx);
 149
 150        /* Step 7: Wait for ROM init */
 151        ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
 152                        SKL_FW_INIT, BXT_ROM_INIT_TIMEOUT, "ROM Load");
 153        if (ret < 0) {
 154                dev_err(ctx->dev, "Timeout for ROM init, ret:%d\n", ret);
 155                goto base_fw_load_failed;
 156        }
 157
 158        return ret;
 159
 160base_fw_load_failed:
 161        ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
 162        skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
 163        skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
 164        return ret;
 165}
 166
 167static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
 168{
 169        int ret;
 170
 171        ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
 172        ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
 173                        BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
 174
 175        ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
 176        ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
 177
 178        return ret;
 179}
 180
 181static int bxt_load_base_firmware(struct sst_dsp *ctx)
 182{
 183        struct firmware stripped_fw;
 184        struct skl_dev *skl = ctx->thread_context;
 185        int ret, i;
 186
 187        if (ctx->fw == NULL) {
 188                ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
 189                if (ret < 0) {
 190                        dev_err(ctx->dev, "Request firmware failed %d\n", ret);
 191                        return ret;
 192                }
 193        }
 194
 195        /* prase uuids on first boot */
 196        if (skl->is_first_boot) {
 197                ret = snd_skl_parse_uuids(ctx, ctx->fw, BXT_ADSP_FW_BIN_HDR_OFFSET, 0);
 198                if (ret < 0)
 199                        goto sst_load_base_firmware_failed;
 200        }
 201
 202        stripped_fw.data = ctx->fw->data;
 203        stripped_fw.size = ctx->fw->size;
 204        skl_dsp_strip_extended_manifest(&stripped_fw);
 205
 206
 207        for (i = 0; i < BXT_FW_ROM_INIT_RETRY; i++) {
 208                ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
 209                if (ret == 0)
 210                        break;
 211        }
 212
 213        if (ret < 0) {
 214                dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
 215                        sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
 216                        sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
 217
 218                dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
 219                goto sst_load_base_firmware_failed;
 220        }
 221
 222        ret = sst_transfer_fw_host_dma(ctx);
 223        if (ret < 0) {
 224                dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
 225                dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
 226                        sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
 227                        sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
 228
 229                skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
 230        } else {
 231                dev_dbg(ctx->dev, "Firmware download successful\n");
 232                ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
 233                                        msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
 234                if (ret == 0) {
 235                        dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
 236                        skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
 237                        ret = -EIO;
 238                } else {
 239                        ret = 0;
 240                        skl->fw_loaded = true;
 241                }
 242        }
 243
 244        return ret;
 245
 246sst_load_base_firmware_failed:
 247        release_firmware(ctx->fw);
 248        ctx->fw = NULL;
 249        return ret;
 250}
 251
 252/*
 253 * Decide the D0i3 state that can be targeted based on the usecase
 254 * ref counts and DSP state
 255 *
 256 * Decision Matrix:  (X= dont care; state = target state)
 257 *
 258 * DSP state != SKL_DSP_RUNNING ; state = no d0i3
 259 *
 260 * DSP state == SKL_DSP_RUNNING , the following matrix applies
 261 * non_d0i3 >0; streaming =X; non_streaming =X; state = no d0i3
 262 * non_d0i3 =X; streaming =0; non_streaming =0; state = no d0i3
 263 * non_d0i3 =0; streaming >0; non_streaming =X; state = streaming d0i3
 264 * non_d0i3 =0; streaming =0; non_streaming =X; state = non-streaming d0i3
 265 */
 266static int bxt_d0i3_target_state(struct sst_dsp *ctx)
 267{
 268        struct skl_dev *skl = ctx->thread_context;
 269        struct skl_d0i3_data *d0i3 = &skl->d0i3;
 270
 271        if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING)
 272                return SKL_DSP_D0I3_NONE;
 273
 274        if (d0i3->non_d0i3)
 275                return SKL_DSP_D0I3_NONE;
 276        else if (d0i3->streaming)
 277                return SKL_DSP_D0I3_STREAMING;
 278        else if (d0i3->non_streaming)
 279                return SKL_DSP_D0I3_NON_STREAMING;
 280        else
 281                return SKL_DSP_D0I3_NONE;
 282}
 283
 284static void bxt_set_dsp_D0i3(struct work_struct *work)
 285{
 286        int ret;
 287        struct skl_ipc_d0ix_msg msg;
 288        struct skl_dev *skl = container_of(work,
 289                        struct skl_dev, d0i3.work.work);
 290        struct sst_dsp *ctx = skl->dsp;
 291        struct skl_d0i3_data *d0i3 = &skl->d0i3;
 292        int target_state;
 293
 294        dev_dbg(ctx->dev, "In %s:\n", __func__);
 295
 296        /* D0i3 entry allowed only if core 0 alone is running */
 297        if (skl_dsp_get_enabled_cores(ctx) !=  SKL_DSP_CORE0_MASK) {
 298                dev_warn(ctx->dev,
 299                                "D0i3 allowed when only core0 running:Exit\n");
 300                return;
 301        }
 302
 303        target_state = bxt_d0i3_target_state(ctx);
 304        if (target_state == SKL_DSP_D0I3_NONE)
 305                return;
 306
 307        msg.instance_id = 0;
 308        msg.module_id = 0;
 309        msg.wake = 1;
 310        msg.streaming = 0;
 311        if (target_state == SKL_DSP_D0I3_STREAMING)
 312                msg.streaming = 1;
 313
 314        ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);
 315
 316        if (ret < 0) {
 317                dev_err(ctx->dev, "Failed to set DSP to D0i3 state\n");
 318                return;
 319        }
 320
 321        /* Set Vendor specific register D0I3C.I3 to enable D0i3*/
 322        if (skl->update_d0i3c)
 323                skl->update_d0i3c(skl->dev, true);
 324
 325        d0i3->state = target_state;
 326        skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3;
 327}
 328
 329static int bxt_schedule_dsp_D0i3(struct sst_dsp *ctx)
 330{
 331        struct skl_dev *skl = ctx->thread_context;
 332        struct skl_d0i3_data *d0i3 = &skl->d0i3;
 333
 334        /* Schedule D0i3 only if the usecase ref counts are appropriate */
 335        if (bxt_d0i3_target_state(ctx) != SKL_DSP_D0I3_NONE) {
 336
 337                dev_dbg(ctx->dev, "%s: Schedule D0i3\n", __func__);
 338
 339                schedule_delayed_work(&d0i3->work,
 340                                msecs_to_jiffies(BXT_D0I3_DELAY));
 341        }
 342
 343        return 0;
 344}
 345
 346static int bxt_set_dsp_D0i0(struct sst_dsp *ctx)
 347{
 348        int ret;
 349        struct skl_ipc_d0ix_msg msg;
 350        struct skl_dev *skl = ctx->thread_context;
 351
 352        dev_dbg(ctx->dev, "In %s:\n", __func__);
 353
 354        /* First Cancel any pending attempt to put DSP to D0i3 */
 355        cancel_delayed_work_sync(&skl->d0i3.work);
 356
 357        /* If DSP is currently in D0i3, bring it to D0i0 */
 358        if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3)
 359                return 0;
 360
 361        dev_dbg(ctx->dev, "Set DSP to D0i0\n");
 362
 363        msg.instance_id = 0;
 364        msg.module_id = 0;
 365        msg.streaming = 0;
 366        msg.wake = 0;
 367
 368        if (skl->d0i3.state == SKL_DSP_D0I3_STREAMING)
 369                msg.streaming = 1;
 370
 371        /* Clear Vendor specific register D0I3C.I3 to disable D0i3*/
 372        if (skl->update_d0i3c)
 373                skl->update_d0i3c(skl->dev, false);
 374
 375        ret =  skl_ipc_set_d0ix(&skl->ipc, &msg);
 376        if (ret < 0) {
 377                dev_err(ctx->dev, "Failed to set DSP to D0i0\n");
 378                return ret;
 379        }
 380
 381        skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;
 382        skl->d0i3.state = SKL_DSP_D0I3_NONE;
 383
 384        return 0;
 385}
 386
 387static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
 388{
 389        struct skl_dev *skl = ctx->thread_context;
 390        int ret;
 391        struct skl_ipc_dxstate_info dx;
 392        unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
 393
 394        if (skl->fw_loaded == false) {
 395                skl->boot_complete = false;
 396                ret = bxt_load_base_firmware(ctx);
 397                if (ret < 0) {
 398                        dev_err(ctx->dev, "reload fw failed: %d\n", ret);
 399                        return ret;
 400                }
 401
 402                if (skl->lib_count > 1) {
 403                        ret = bxt_load_library(ctx, skl->lib_info,
 404                                                skl->lib_count);
 405                        if (ret < 0) {
 406                                dev_err(ctx->dev, "reload libs failed: %d\n", ret);
 407                                return ret;
 408                        }
 409                }
 410                skl->cores.state[core_id] = SKL_DSP_RUNNING;
 411                return ret;
 412        }
 413
 414        /* If core 0 is being turned on, turn on core 1 as well */
 415        if (core_id == SKL_DSP_CORE0_ID)
 416                ret = skl_dsp_core_power_up(ctx, core_mask |
 417                                SKL_DSP_CORE_MASK(1));
 418        else
 419                ret = skl_dsp_core_power_up(ctx, core_mask);
 420
 421        if (ret < 0)
 422                goto err;
 423
 424        if (core_id == SKL_DSP_CORE0_ID) {
 425
 426                /*
 427                 * Enable interrupt after SPA is set and before
 428                 * DSP is unstalled
 429                 */
 430                skl_ipc_int_enable(ctx);
 431                skl_ipc_op_int_enable(ctx);
 432                skl->boot_complete = false;
 433        }
 434
 435        ret = skl_dsp_start_core(ctx, core_mask);
 436        if (ret < 0)
 437                goto err;
 438
 439        if (core_id == SKL_DSP_CORE0_ID) {
 440                ret = wait_event_timeout(skl->boot_wait,
 441                                skl->boot_complete,
 442                                msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
 443
 444        /* If core 1 was turned on for booting core 0, turn it off */
 445                skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
 446                if (ret == 0) {
 447                        dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
 448                        dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
 449                                sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
 450                                sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
 451                        dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
 452                        ret = -EIO;
 453                        goto err;
 454                }
 455        }
 456
 457        /* Tell FW if additional core in now On */
 458
 459        if (core_id != SKL_DSP_CORE0_ID) {
 460                dx.core_mask = core_mask;
 461                dx.dx_mask = core_mask;
 462
 463                ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
 464                                        BXT_BASE_FW_MODULE_ID, &dx);
 465                if (ret < 0) {
 466                        dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
 467                                                                core_id, ret);
 468                        goto err;
 469                }
 470        }
 471
 472        skl->cores.state[core_id] = SKL_DSP_RUNNING;
 473        return 0;
 474err:
 475        if (core_id == SKL_DSP_CORE0_ID)
 476                core_mask |= SKL_DSP_CORE_MASK(1);
 477        skl_dsp_disable_core(ctx, core_mask);
 478
 479        return ret;
 480}
 481
 482static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
 483{
 484        int ret;
 485        struct skl_ipc_dxstate_info dx;
 486        struct skl_dev *skl = ctx->thread_context;
 487        unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
 488
 489        dx.core_mask = core_mask;
 490        dx.dx_mask = SKL_IPC_D3_MASK;
 491
 492        dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
 493                        dx.core_mask, dx.dx_mask);
 494
 495        ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
 496                                BXT_BASE_FW_MODULE_ID, &dx);
 497        if (ret < 0) {
 498                dev_err(ctx->dev,
 499                "Failed to set DSP to D3:core id = %d;Continue reset\n",
 500                core_id);
 501                /*
 502                 * In case of D3 failure, re-download the firmware, so set
 503                 * fw_loaded to false.
 504                 */
 505                skl->fw_loaded = false;
 506        }
 507
 508        if (core_id == SKL_DSP_CORE0_ID) {
 509                /* disable Interrupt */
 510                skl_ipc_op_int_disable(ctx);
 511                skl_ipc_int_disable(ctx);
 512        }
 513        ret = skl_dsp_disable_core(ctx, core_mask);
 514        if (ret < 0) {
 515                dev_err(ctx->dev, "Failed to disable core %d\n", ret);
 516                return ret;
 517        }
 518        skl->cores.state[core_id] = SKL_DSP_RESET;
 519        return 0;
 520}
 521
 522static const struct skl_dsp_fw_ops bxt_fw_ops = {
 523        .set_state_D0 = bxt_set_dsp_D0,
 524        .set_state_D3 = bxt_set_dsp_D3,
 525        .set_state_D0i3 = bxt_schedule_dsp_D0i3,
 526        .set_state_D0i0 = bxt_set_dsp_D0i0,
 527        .load_fw = bxt_load_base_firmware,
 528        .get_fw_errcode = bxt_get_errorcode,
 529        .load_library = bxt_load_library,
 530};
 531
 532static struct sst_ops skl_ops = {
 533        .irq_handler = skl_dsp_sst_interrupt,
 534        .write = sst_shim32_write,
 535        .read = sst_shim32_read,
 536        .ram_read = sst_memcpy_fromio_32,
 537        .ram_write = sst_memcpy_toio_32,
 538        .free = skl_dsp_free,
 539};
 540
 541static struct sst_dsp_device skl_dev = {
 542        .thread = skl_dsp_irq_thread_handler,
 543        .ops = &skl_ops,
 544};
 545
 546int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 547                        const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 548                        struct skl_dev **dsp)
 549{
 550        struct skl_dev *skl;
 551        struct sst_dsp *sst;
 552        int ret;
 553
 554        ret = skl_sst_ctx_init(dev, irq, fw_name, dsp_ops, dsp, &skl_dev);
 555        if (ret < 0) {
 556                dev_err(dev, "%s: no device\n", __func__);
 557                return ret;
 558        }
 559
 560        skl = *dsp;
 561        sst = skl->dsp;
 562        sst->fw_ops = bxt_fw_ops;
 563        sst->addr.lpe = mmio_base;
 564        sst->addr.shim = mmio_base;
 565        sst->addr.sram0_base = BXT_ADSP_SRAM0_BASE;
 566        sst->addr.sram1_base = BXT_ADSP_SRAM1_BASE;
 567        sst->addr.w0_stat_sz = SKL_ADSP_W0_STAT_SZ;
 568        sst->addr.w0_up_sz = SKL_ADSP_W0_UP_SZ;
 569
 570        sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
 571                        SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
 572
 573        ret = skl_ipc_init(dev, skl);
 574        if (ret) {
 575                skl_dsp_free(sst);
 576                return ret;
 577        }
 578
 579        /* set the D0i3 check */
 580        skl->ipc.ops.check_dsp_lp_on = skl_ipc_check_D0i0;
 581
 582        skl->boot_complete = false;
 583        init_waitqueue_head(&skl->boot_wait);
 584        INIT_DELAYED_WORK(&skl->d0i3.work, bxt_set_dsp_D0i3);
 585        skl->d0i3.state = SKL_DSP_D0I3_NONE;
 586
 587        return skl_dsp_acquire_irq(sst);
 588}
 589EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
 590
 591int bxt_sst_init_fw(struct device *dev, struct skl_dev *skl)
 592{
 593        int ret;
 594        struct sst_dsp *sst = skl->dsp;
 595
 596        ret = sst->fw_ops.load_fw(sst);
 597        if (ret < 0) {
 598                dev_err(dev, "Load base fw failed: %x\n", ret);
 599                return ret;
 600        }
 601
 602        skl_dsp_init_core_state(sst);
 603
 604        if (skl->lib_count > 1) {
 605                ret = sst->fw_ops.load_library(sst, skl->lib_info,
 606                                                skl->lib_count);
 607                if (ret < 0) {
 608                        dev_err(dev, "Load Library failed : %x\n", ret);
 609                        return ret;
 610                }
 611        }
 612        skl->is_first_boot = false;
 613
 614        return 0;
 615}
 616EXPORT_SYMBOL_GPL(bxt_sst_init_fw);
 617
 618void bxt_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl)
 619{
 620
 621        skl_release_library(skl->lib_info, skl->lib_count);
 622        if (skl->dsp->fw)
 623                release_firmware(skl->dsp->fw);
 624        skl_freeup_uuid_list(skl);
 625        skl_ipc_free(&skl->ipc);
 626        skl->dsp->ops->free(skl->dsp);
 627}
 628EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
 629
 630MODULE_LICENSE("GPL v2");
 631MODULE_DESCRIPTION("Intel Broxton IPC driver");
 632